1 /*
2 * Copyright (c) 2015-2025, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <string.h>
9
10 #include <arch.h>
11 #include <arch_helpers.h>
12 #include <common/debug.h>
13 #include <lib/bakery_lock.h>
14 #include <lib/mmio.h>
15 #include <lib/xlat_tables/xlat_tables_v2.h>
16 #include <plat/common/platform.h>
17
18 #include "iic_dvfs.h"
19 #include "micro_delay.h"
20 #include "pwrc.h"
21 #include "timer.h"
22
23 #include "cpg_registers.h"
24 #include "rcar_def.h"
25 #include "rcar_private.h"
26
27 /*
28 * Someday there will be a generic power controller api. At the moment each
29 * platform has its own pwrc so just exporting functions should be acceptable.
30 */
31 RCAR_INSTANTIATE_LOCK
32
33 #define WUP_IRQ_SHIFT (0U)
34 #define WUP_FIQ_SHIFT (8U)
35 #define WUP_CSD_SHIFT (16U)
36 #define BIT_SOFTRESET (1U << 15)
37 #define BIT_CA53_SCU (1U << 21)
38 #define BIT_CA57_SCU (1U << 12)
39 #define REQ_RESUME (1U << 1)
40 #define REQ_OFF (1U << 0)
41 #define STATUS_PWRUP (1U << 4)
42 #define STATUS_PWRDOWN (1U << 0)
43 #define STATE_CA57_CPU (27U)
44 #define STATE_CA53_CPU (22U)
45 #define MODE_L2_DOWN (0x00000002U)
46 #define CPU_PWR_OFF (0x00000003U)
47 #define RCAR_PSTR_MASK (0x00000003U)
48 #define ST_ALL_STANDBY (0x00003333U)
49 #define SYSCEXTMASK_EXTMSK0 (0x00000001U)
50 /* Suspend to ram */
51 #define DBSC4_REG_BASE (0xE6790000U)
52 #define DBSC4_REG_DBSYSCNT0 (DBSC4_REG_BASE + 0x0100U)
53 #define DBSC4_REG_DBACEN (DBSC4_REG_BASE + 0x0200U)
54 #define DBSC4_REG_DBCMD (DBSC4_REG_BASE + 0x0208U)
55 #define DBSC4_REG_DBRFEN (DBSC4_REG_BASE + 0x0204U)
56 #define DBSC4_REG_DBWAIT (DBSC4_REG_BASE + 0x0210U)
57 #define DBSC4_REG_DBCALCNF (DBSC4_REG_BASE + 0x0424U)
58 #define DBSC4_REG_DBDFIPMSTRCNF (DBSC4_REG_BASE + 0x0520U)
59 #define DBSC4_REG_DBPDLK0 (DBSC4_REG_BASE + 0x0620U)
60 #define DBSC4_REG_DBPDRGA0 (DBSC4_REG_BASE + 0x0624U)
61 #define DBSC4_REG_DBPDRGD0 (DBSC4_REG_BASE + 0x0628U)
62 #define DBSC4_REG_DBCAM0CTRL0 (DBSC4_REG_BASE + 0x0940U)
63 #define DBSC4_REG_DBCAM0STAT0 (DBSC4_REG_BASE + 0x0980U)
64 #define DBSC4_REG_DBCAM1STAT0 (DBSC4_REG_BASE + 0x0990U)
65 #define DBSC4_REG_DBCAM2STAT0 (DBSC4_REG_BASE + 0x09A0U)
66 #define DBSC4_REG_DBCAM3STAT0 (DBSC4_REG_BASE + 0x09B0U)
67 #define DBSC4_BIT_DBACEN_ACCEN ((uint32_t)(1U << 0))
68 #define DBSC4_BIT_DBRFEN_ARFEN ((uint32_t)(1U << 0))
69 #define DBSC4_BIT_DBCAMxSTAT0 (0x00000001U)
70 #define DBSC4_BIT_DBDFIPMSTRCNF_PMSTREN (0x00000001U)
71 #define DBSC4_SET_DBCMD_OPC_PRE (0x04000000U)
72 #define DBSC4_SET_DBCMD_OPC_SR (0x0A000000U)
73 #define DBSC4_SET_DBCMD_OPC_PD (0x08000000U)
74 #define DBSC4_SET_DBCMD_OPC_MRW (0x0E000000U)
75 #define DBSC4_SET_DBCMD_CH_ALL (0x00800000U)
76 #define DBSC4_SET_DBCMD_RANK_ALL (0x00040000U)
77 #define DBSC4_SET_DBCMD_ARG_ALL (0x00000010U)
78 #define DBSC4_SET_DBCMD_ARG_ENTER (0x00000000U)
79 #define DBSC4_SET_DBCMD_ARG_MRW_ODTC (0x00000B00U)
80 #define DBSC4_SET_DBSYSCNT0_WRITE_ENABLE (0x00001234U)
81 #define DBSC4_SET_DBSYSCNT0_WRITE_DISABLE (0x00000000U)
82 #define DBSC4_SET_DBPDLK0_PHY_ACCESS (0x0000A55AU)
83 #define DBSC4_SET_DBPDRGA0_ACIOCR0 (0x0000001AU)
84 #define DBSC4_SET_DBPDRGD0_ACIOCR0 (0x33C03C11U)
85 #define DBSC4_SET_DBPDRGA0_DXCCR (0x00000020U)
86 #define DBSC4_SET_DBPDRGD0_DXCCR (0x00181006U)
87 #define DBSC4_SET_DBPDRGA0_PGCR1 (0x00000003U)
88 #define DBSC4_SET_DBPDRGD0_PGCR1 (0x0380C600U)
89 #define DBSC4_SET_DBPDRGA0_ACIOCR1 (0x0000001BU)
90 #define DBSC4_SET_DBPDRGD0_ACIOCR1 (0xAAAAAAAAU)
91 #define DBSC4_SET_DBPDRGA0_ACIOCR3 (0x0000001DU)
92 #define DBSC4_SET_DBPDRGD0_ACIOCR3 (0xAAAAAAAAU)
93 #define DBSC4_SET_DBPDRGA0_ACIOCR5 (0x0000001FU)
94 #define DBSC4_SET_DBPDRGD0_ACIOCR5 (0x000000AAU)
95 #define DBSC4_SET_DBPDRGA0_DX0GCR2 (0x000000A2U)
96 #define DBSC4_SET_DBPDRGD0_DX0GCR2 (0xAAAA0000U)
97 #define DBSC4_SET_DBPDRGA0_DX1GCR2 (0x000000C2U)
98 #define DBSC4_SET_DBPDRGD0_DX1GCR2 (0xAAAA0000U)
99 #define DBSC4_SET_DBPDRGA0_DX2GCR2 (0x000000E2U)
100 #define DBSC4_SET_DBPDRGD0_DX2GCR2 (0xAAAA0000U)
101 #define DBSC4_SET_DBPDRGA0_DX3GCR2 (0x00000102U)
102 #define DBSC4_SET_DBPDRGD0_DX3GCR2 (0xAAAA0000U)
103 #define DBSC4_SET_DBPDRGA0_ZQCR (0x00000090U)
104 #define DBSC4_SET_DBPDRGD0_ZQCR_MD19_0 (0x04058904U)
105 #define DBSC4_SET_DBPDRGD0_ZQCR_MD19_1 (0x04058A04U)
106 #define DBSC4_SET_DBPDRGA0_DX0GCR0 (0x000000A0U)
107 #define DBSC4_SET_DBPDRGD0_DX0GCR0 (0x7C0002E5U)
108 #define DBSC4_SET_DBPDRGA0_DX1GCR0 (0x000000C0U)
109 #define DBSC4_SET_DBPDRGD0_DX1GCR0 (0x7C0002E5U)
110 #define DBSC4_SET_DBPDRGA0_DX2GCR0 (0x000000E0U)
111 #define DBSC4_SET_DBPDRGD0_DX2GCR0 (0x7C0002E5U)
112 #define DBSC4_SET_DBPDRGA0_DX3GCR0 (0x00000100U)
113 #define DBSC4_SET_DBPDRGD0_DX3GCR0 (0x7C0002E5U)
114 #define DBSC4_SET_DBPDRGA0_DX0GCR1 (0x000000A1U)
115 #define DBSC4_SET_DBPDRGD0_DX0GCR1 (0x55550000U)
116 #define DBSC4_SET_DBPDRGA0_DX1GCR1 (0x000000C1U)
117 #define DBSC4_SET_DBPDRGD0_DX1GCR1 (0x55550000U)
118 #define DBSC4_SET_DBPDRGA0_DX2GCR1 (0x000000E1U)
119 #define DBSC4_SET_DBPDRGD0_DX2GCR1 (0x55550000U)
120 #define DBSC4_SET_DBPDRGA0_DX3GCR1 (0x00000101U)
121 #define DBSC4_SET_DBPDRGD0_DX3GCR1 (0x55550000U)
122 #define DBSC4_SET_DBPDRGA0_DX0GCR3 (0x000000A3U)
123 #define DBSC4_SET_DBPDRGD0_DX0GCR3 (0x00008484U)
124 #define DBSC4_SET_DBPDRGA0_DX1GCR3 (0x000000C3U)
125 #define DBSC4_SET_DBPDRGD0_DX1GCR3 (0x00008484U)
126 #define DBSC4_SET_DBPDRGA0_DX2GCR3 (0x000000E3U)
127 #define DBSC4_SET_DBPDRGD0_DX2GCR3 (0x00008484U)
128 #define DBSC4_SET_DBPDRGA0_DX3GCR3 (0x00000103U)
129 #define DBSC4_SET_DBPDRGD0_DX3GCR3 (0x00008484U)
130 #define RST_BASE (0xE6160000U)
131 #define RST_MODEMR (RST_BASE + 0x0060U)
132 #define RST_MODEMR_BIT0 (0x00000001U)
133
134 #if PMIC_ROHM_BD9571
135 #define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4))
136 #define PMIC_BKUP_MODE_CNT (0x20U)
137 #define PMIC_QLLM_CNT (0x27U)
138 #define PMIC_RETRY_MAX (100U)
139 #endif /* PMIC_ROHM_BD9571 */
140 #define SCTLR_EL3_M_BIT ((uint32_t)1U << 0)
141 #define RCAR_CA53CPU_NUM_MAX (4U)
142 #define RCAR_CA57CPU_NUM_MAX (4U)
143 #define IS_A53A57(c) ((c) == RCAR_CLUSTER_A53A57)
144 #define IS_CA57(c) ((c) == RCAR_CLUSTER_CA57)
145 #define IS_CA53(c) ((c) == RCAR_CLUSTER_CA53)
146
147 #ifndef __ASSEMBLER__
148 IMPORT_SYM(unsigned long, __system_ram_start__, SYSTEM_RAM_START);
149 IMPORT_SYM(unsigned long, __system_ram_end__, SYSTEM_RAM_END);
150 IMPORT_SYM(unsigned long, __SRAM_COPY_START__, SRAM_COPY_START);
151 #endif
152
rcar_pwrc_status(u_register_t mpidr)153 uint32_t rcar_pwrc_status(u_register_t mpidr)
154 {
155 uint32_t ret = 0;
156 uint64_t cm, cpu;
157 uint32_t reg;
158 uint32_t c;
159
160 rcar_lock_get();
161
162 c = rcar_pwrc_get_cluster();
163 cm = mpidr & MPIDR_CLUSTER_MASK;
164
165 if (!IS_A53A57(c) && cm != 0) {
166 ret = RCAR_INVALID;
167 goto done;
168 }
169
170 reg = mmio_read_32(RCAR_PRR);
171 cpu = mpidr & MPIDR_CPU_MASK;
172
173 if (IS_CA53(c))
174 if (reg & (1 << (STATE_CA53_CPU + cpu)))
175 ret = RCAR_INVALID;
176 if (IS_CA57(c))
177 if (reg & (1 << (STATE_CA57_CPU + cpu)))
178 ret = RCAR_INVALID;
179 done:
180 rcar_lock_release();
181
182 return ret;
183 }
184
scu_power_up(u_register_t mpidr)185 static void scu_power_up(u_register_t mpidr)
186 {
187 uintptr_t reg_pwrsr, reg_cpumcr, reg_pwron, reg_pwrer;
188 uint32_t c, sysc_reg_bit;
189 uint32_t lsi_product;
190 uint32_t lsi_cut;
191
192 c = rcar_pwrc_get_mpidr_cluster(mpidr);
193 reg_cpumcr = IS_CA57(c) ? RCAR_CA57CPUCMCR : RCAR_CA53CPUCMCR;
194 sysc_reg_bit = IS_CA57(c) ? BIT_CA57_SCU : BIT_CA53_SCU;
195 reg_pwron = IS_CA57(c) ? RCAR_PWRONCR5 : RCAR_PWRONCR3;
196 reg_pwrer = IS_CA57(c) ? RCAR_PWRER5 : RCAR_PWRER3;
197 reg_pwrsr = IS_CA57(c) ? RCAR_PWRSR5 : RCAR_PWRSR3;
198
199 if ((mmio_read_32(reg_pwrsr) & STATUS_PWRDOWN) == 0)
200 return;
201
202 if (mmio_read_32(reg_cpumcr) != 0)
203 mmio_write_32(reg_cpumcr, 0);
204
205 lsi_product = mmio_read_32((uintptr_t)RCAR_PRR);
206 lsi_cut = lsi_product & PRR_CUT_MASK;
207 lsi_product &= PRR_PRODUCT_MASK;
208
209 if ((lsi_product == PRR_PRODUCT_M3 && lsi_cut >= PRR_PRODUCT_30) ||
210 lsi_product == PRR_PRODUCT_H3 ||
211 lsi_product == PRR_PRODUCT_M3N ||
212 lsi_product == PRR_PRODUCT_E3) {
213 mmio_setbits_32(RCAR_SYSCEXTMASK, SYSCEXTMASK_EXTMSK0);
214 }
215
216 mmio_setbits_32(RCAR_SYSCIER, sysc_reg_bit);
217 mmio_setbits_32(RCAR_SYSCIMR, sysc_reg_bit);
218
219 do {
220 while ((mmio_read_32(RCAR_SYSCSR) & REQ_RESUME) == 0)
221 ;
222 mmio_write_32(reg_pwron, 1);
223 } while (mmio_read_32(reg_pwrer) & 1);
224
225 while ((mmio_read_32(RCAR_SYSCISR) & sysc_reg_bit) == 0)
226 ;
227 mmio_write_32(RCAR_SYSCISCR, sysc_reg_bit);
228
229 if ((lsi_product == PRR_PRODUCT_M3 && lsi_cut >= PRR_PRODUCT_30) ||
230 lsi_product == PRR_PRODUCT_H3 ||
231 lsi_product == PRR_PRODUCT_M3N ||
232 lsi_product == PRR_PRODUCT_E3) {
233 mmio_clrbits_32(RCAR_SYSCEXTMASK, SYSCEXTMASK_EXTMSK0);
234 }
235
236 while ((mmio_read_32(reg_pwrsr) & STATUS_PWRUP) == 0)
237 ;
238 }
239
rcar_pwrc_cpuon(u_register_t mpidr)240 void rcar_pwrc_cpuon(u_register_t mpidr)
241 {
242 uint32_t res_data, on_data;
243 uintptr_t res_reg, on_reg;
244 uint32_t limit, c;
245 uint64_t cpu;
246
247 rcar_lock_get();
248
249 c = rcar_pwrc_get_mpidr_cluster(mpidr);
250 res_reg = IS_CA53(c) ? RCAR_CA53RESCNT : RCAR_CA57RESCNT;
251 on_reg = IS_CA53(c) ? RCAR_CA53WUPCR : RCAR_CA57WUPCR;
252 limit = IS_CA53(c) ? 0x5A5A0000 : 0xA5A50000;
253
254 res_data = mmio_read_32(res_reg) | limit;
255 scu_power_up(mpidr);
256 cpu = mpidr & MPIDR_CPU_MASK;
257 on_data = 1 << cpu;
258 mmio_write_32(CPG_CPGWPR, ~on_data);
259 mmio_write_32(on_reg, on_data);
260 mmio_write_32(res_reg, res_data & (~(1 << (3 - cpu))));
261
262 rcar_lock_release();
263 }
264
rcar_pwrc_cpuoff(u_register_t mpidr)265 void rcar_pwrc_cpuoff(u_register_t mpidr)
266 {
267 uint32_t c;
268 uintptr_t reg;
269 uint64_t cpu;
270
271 rcar_lock_get();
272
273 cpu = mpidr & MPIDR_CPU_MASK;
274 c = rcar_pwrc_get_mpidr_cluster(mpidr);
275 reg = IS_CA53(c) ? RCAR_CA53CPU0CR : RCAR_CA57CPU0CR;
276
277 if (read_mpidr_el1() != mpidr)
278 panic();
279
280 mmio_write_32(CPG_CPGWPR, ~CPU_PWR_OFF);
281 mmio_write_32(reg + cpu * 0x0010, CPU_PWR_OFF);
282
283 rcar_lock_release();
284 }
285
rcar_pwrc_enable_interrupt_wakeup(u_register_t mpidr)286 void rcar_pwrc_enable_interrupt_wakeup(u_register_t mpidr)
287 {
288 uint32_t c, shift_irq, shift_fiq;
289 uintptr_t reg;
290 uint64_t cpu;
291
292 rcar_lock_get();
293
294 cpu = mpidr & MPIDR_CPU_MASK;
295 c = rcar_pwrc_get_mpidr_cluster(mpidr);
296 reg = IS_CA53(c) ? RCAR_WUPMSKCA53 : RCAR_WUPMSKCA57;
297
298 shift_irq = WUP_IRQ_SHIFT + cpu;
299 shift_fiq = WUP_FIQ_SHIFT + cpu;
300
301 mmio_clrbits_32(reg, ((uint32_t) 1 << shift_irq) |
302 ((uint32_t) 1 << shift_fiq));
303 rcar_lock_release();
304 }
305
rcar_pwrc_disable_interrupt_wakeup(u_register_t mpidr)306 void rcar_pwrc_disable_interrupt_wakeup(u_register_t mpidr)
307 {
308 uint32_t c, shift_irq, shift_fiq;
309 uintptr_t reg;
310 uint64_t cpu;
311
312 rcar_lock_get();
313
314 cpu = mpidr & MPIDR_CPU_MASK;
315 c = rcar_pwrc_get_mpidr_cluster(mpidr);
316 reg = IS_CA53(c) ? RCAR_WUPMSKCA53 : RCAR_WUPMSKCA57;
317
318 shift_irq = WUP_IRQ_SHIFT + cpu;
319 shift_fiq = WUP_FIQ_SHIFT + cpu;
320
321 mmio_setbits_32(reg, ((uint32_t) 1 << shift_irq) |
322 ((uint32_t) 1 << shift_fiq));
323 rcar_lock_release();
324 }
325
rcar_pwrc_all_disable_interrupt_wakeup(void)326 void rcar_pwrc_all_disable_interrupt_wakeup(void)
327 {
328 uint32_t cpu_num;
329 u_register_t cl, cpu, mpidr;
330
331 const uint32_t cluster[PLATFORM_CLUSTER_COUNT] = {
332 RCAR_CLUSTER_CA57,
333 RCAR_CLUSTER_CA53
334 };
335
336 for (cl = 0; cl < PLATFORM_CLUSTER_COUNT; cl++) {
337 cpu_num = rcar_pwrc_get_cpu_num(cluster[cl]);
338 for (cpu = 0; cpu < cpu_num; cpu++) {
339 mpidr = ((cl << MPIDR_AFFINITY_BITS) | cpu);
340 if (mpidr == rcar_boot_mpidr) {
341 rcar_pwrc_enable_interrupt_wakeup(mpidr);
342 } else {
343 rcar_pwrc_disable_interrupt_wakeup(mpidr);
344 }
345 }
346 }
347 }
348
rcar_pwrc_clusteroff(u_register_t mpidr)349 void rcar_pwrc_clusteroff(u_register_t mpidr)
350 {
351 uint32_t c, product, cut, reg;
352 uintptr_t dst;
353
354 rcar_lock_get();
355
356 reg = mmio_read_32(RCAR_PRR);
357 product = reg & PRR_PRODUCT_MASK;
358 cut = reg & PRR_CUT_MASK;
359
360 c = rcar_pwrc_get_mpidr_cluster(mpidr);
361 dst = IS_CA53(c) ? RCAR_CA53CPUCMCR : RCAR_CA57CPUCMCR;
362
363 if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) {
364 goto done;
365 }
366
367 if (product == PRR_PRODUCT_H3 && cut <= PRR_PRODUCT_20) {
368 goto done;
369 }
370
371 /* all of the CPUs in the cluster is in the CoreStandby mode */
372 mmio_write_32(dst, MODE_L2_DOWN);
373 done:
374 rcar_lock_release();
375 }
376
377 #if !PMIC_ROHM_BD9571
rcar_pwrc_system_reset(void)378 void rcar_pwrc_system_reset(void)
379 {
380 mmio_write_32(RCAR_SRESCR, 0x5AA50000U | BIT_SOFTRESET);
381 }
382 #endif /* PMIC_ROHM_BD9571 */
383
384 #define RST_CA53_CPU0_BARH (0xE6160080U)
385 #define RST_CA53_CPU0_BARL (0xE6160084U)
386 #define RST_CA57_CPU0_BARH (0xE61600C0U)
387 #define RST_CA57_CPU0_BARL (0xE61600C4U)
388
rcar_pwrc_setup(void)389 void rcar_pwrc_setup(void)
390 {
391 uintptr_t rst_barh;
392 uintptr_t rst_barl;
393 uint32_t i, j;
394 uint64_t reset = (uint64_t) (&plat_secondary_reset) & 0xFFFFFFFF;
395
396 const uint32_t cluster[PLATFORM_CLUSTER_COUNT] = {
397 RCAR_CLUSTER_CA53,
398 RCAR_CLUSTER_CA57
399 };
400 const uintptr_t reg_barh[PLATFORM_CLUSTER_COUNT] = {
401 RST_CA53_CPU0_BARH,
402 RST_CA57_CPU0_BARH
403 };
404 const uintptr_t reg_barl[PLATFORM_CLUSTER_COUNT] = {
405 RST_CA53_CPU0_BARL,
406 RST_CA57_CPU0_BARL
407 };
408
409 for (i = 0; i < PLATFORM_CLUSTER_COUNT; i++) {
410 rst_barh = reg_barh[i];
411 rst_barl = reg_barl[i];
412 for (j = 0; j < rcar_pwrc_get_cpu_num(cluster[i]); j++) {
413 mmio_write_32(rst_barh, 0);
414 mmio_write_32(rst_barl, (uint32_t) reset);
415 rst_barh += 0x10;
416 rst_barl += 0x10;
417 }
418 }
419
420 rcar_lock_init();
421 }
422
423 #if RCAR_SYSTEM_SUSPEND
424 #define DBCAM_FLUSH(__bit) \
425 do { \
426 ; \
427 } while (!(mmio_read_32(DBSC4_REG_DBCAM##__bit##STAT0) & DBSC4_BIT_DBCAMxSTAT0))
428
429
430 static void __attribute__ ((section(".system_ram")))
rcar_pwrc_set_self_refresh(void)431 rcar_pwrc_set_self_refresh(void)
432 {
433 uint32_t reg = mmio_read_32(RCAR_PRR);
434 uint32_t cut, product;
435
436 product = reg & PRR_PRODUCT_MASK;
437 cut = reg & PRR_CUT_MASK;
438
439 if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) {
440 goto self_refresh;
441 }
442
443 if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20) {
444 goto self_refresh;
445 }
446
447 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE);
448
449 self_refresh:
450
451 /* DFI_PHYMSTR_ACK setting */
452 mmio_write_32(DBSC4_REG_DBDFIPMSTRCNF,
453 mmio_read_32(DBSC4_REG_DBDFIPMSTRCNF) &
454 (~DBSC4_BIT_DBDFIPMSTRCNF_PMSTREN));
455
456 /* Set the Self-Refresh mode */
457 mmio_write_32(DBSC4_REG_DBACEN, 0);
458
459 if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20)
460 rcar_micro_delay(100);
461 else if (product == PRR_PRODUCT_H3) {
462 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
463 DBCAM_FLUSH(0);
464 DBCAM_FLUSH(1);
465 DBCAM_FLUSH(2);
466 DBCAM_FLUSH(3);
467 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0);
468 } else if (product == PRR_PRODUCT_M3) {
469 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
470 DBCAM_FLUSH(0);
471 DBCAM_FLUSH(1);
472 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0);
473 } else {
474 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
475 DBCAM_FLUSH(0);
476 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0);
477 }
478
479 /* Set the SDRAM calibration configuration register */
480 mmio_write_32(DBSC4_REG_DBCALCNF, 0);
481
482 reg = DBSC4_SET_DBCMD_OPC_PRE | DBSC4_SET_DBCMD_CH_ALL |
483 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ALL;
484 mmio_write_32(DBSC4_REG_DBCMD, reg);
485 while (mmio_read_32(DBSC4_REG_DBWAIT))
486 ;
487
488 /* Self-Refresh entry command */
489 reg = DBSC4_SET_DBCMD_OPC_SR | DBSC4_SET_DBCMD_CH_ALL |
490 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER;
491 mmio_write_32(DBSC4_REG_DBCMD, reg);
492 while (mmio_read_32(DBSC4_REG_DBWAIT))
493 ;
494
495 /* Mode Register Write command. (ODT disabled) */
496 reg = DBSC4_SET_DBCMD_OPC_MRW | DBSC4_SET_DBCMD_CH_ALL |
497 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_MRW_ODTC;
498 mmio_write_32(DBSC4_REG_DBCMD, reg);
499 while (mmio_read_32(DBSC4_REG_DBWAIT))
500 ;
501
502 /* Power Down entry command */
503 reg = DBSC4_SET_DBCMD_OPC_PD | DBSC4_SET_DBCMD_CH_ALL |
504 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER;
505 mmio_write_32(DBSC4_REG_DBCMD, reg);
506 while (mmio_read_32(DBSC4_REG_DBWAIT))
507 ;
508
509 /* Set the auto-refresh enable register */
510 mmio_write_32(DBSC4_REG_DBRFEN, 0U);
511 rcar_micro_delay(1U);
512
513 if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30)
514 return;
515
516 if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20)
517 return;
518
519 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_DISABLE);
520 }
521
522 static void __attribute__ ((section(".system_ram")))
rcar_pwrc_set_self_refresh_e3(void)523 rcar_pwrc_set_self_refresh_e3(void)
524 {
525 uint32_t ddr_md;
526 uint32_t reg;
527
528 ddr_md = (mmio_read_32(RST_MODEMR) >> 19) & RST_MODEMR_BIT0;
529
530 /* Write enable */
531 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE);
532 mmio_write_32(DBSC4_REG_DBACEN, 0);
533 DBCAM_FLUSH(0);
534
535 reg = DBSC4_SET_DBCMD_OPC_PRE | DBSC4_SET_DBCMD_CH_ALL |
536 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ALL;
537 mmio_write_32(DBSC4_REG_DBCMD, reg);
538 while (mmio_read_32(DBSC4_REG_DBWAIT))
539 ;
540
541 reg = DBSC4_SET_DBCMD_OPC_SR | DBSC4_SET_DBCMD_CH_ALL |
542 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER;
543 mmio_write_32(DBSC4_REG_DBCMD, reg);
544 while (mmio_read_32(DBSC4_REG_DBWAIT))
545 ;
546
547 /*
548 * Set the auto-refresh enable register
549 * Set the ARFEN bit to 0 in the DBRFEN
550 */
551 mmio_write_32(DBSC4_REG_DBRFEN, 0);
552
553 mmio_write_32(DBSC4_REG_DBPDLK0, DBSC4_SET_DBPDLK0_PHY_ACCESS);
554
555 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR0);
556 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR0);
557
558 /* DDR_DXCCR */
559 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DXCCR);
560 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DXCCR);
561
562 /* DDR_PGCR1 */
563 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_PGCR1);
564 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_PGCR1);
565
566 /* DDR_ACIOCR1 */
567 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR1);
568 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR1);
569
570 /* DDR_ACIOCR3 */
571 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR3);
572 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR3);
573
574 /* DDR_ACIOCR5 */
575 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR5);
576 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR5);
577
578 /* DDR_DX0GCR2 */
579 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR2);
580 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR2);
581
582 /* DDR_DX1GCR2 */
583 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR2);
584 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR2);
585
586 /* DDR_DX2GCR2 */
587 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR2);
588 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR2);
589
590 /* DDR_DX3GCR2 */
591 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR2);
592 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR2);
593
594 /* DDR_ZQCR */
595 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ZQCR);
596
597 mmio_write_32(DBSC4_REG_DBPDRGD0, ddr_md == 0 ?
598 DBSC4_SET_DBPDRGD0_ZQCR_MD19_0 :
599 DBSC4_SET_DBPDRGD0_ZQCR_MD19_1);
600
601 /* DDR_DX0GCR0 */
602 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR0);
603 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR0);
604
605 /* DDR_DX1GCR0 */
606 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR0);
607 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR0);
608
609 /* DDR_DX2GCR0 */
610 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR0);
611 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR0);
612
613 /* DDR_DX3GCR0 */
614 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR0);
615 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR0);
616
617 /* DDR_DX0GCR1 */
618 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR1);
619 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR1);
620
621 /* DDR_DX1GCR1 */
622 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR1);
623 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR1);
624
625 /* DDR_DX2GCR1 */
626 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR1);
627 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR1);
628
629 /* DDR_DX3GCR1 */
630 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR1);
631 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR1);
632
633 /* DDR_DX0GCR3 */
634 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR3);
635 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR3);
636
637 /* DDR_DX1GCR3 */
638 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR3);
639 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR3);
640
641 /* DDR_DX2GCR3 */
642 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR3);
643 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR3);
644
645 /* DDR_DX3GCR3 */
646 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR3);
647 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR3);
648
649 /* Write disable */
650 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_DISABLE);
651 }
652
653 void __attribute__ ((section(".system_ram"))) __attribute__ ((noinline))
rcar_pwrc_go_suspend_to_ram(void)654 rcar_pwrc_go_suspend_to_ram(void)
655 {
656 #if PMIC_ROHM_BD9571
657 int32_t rc = -1, qllm = -1;
658 uint8_t mode;
659 uint32_t i;
660 #endif
661 uint32_t reg, product;
662
663 reg = mmio_read_32(RCAR_PRR);
664 product = reg & PRR_PRODUCT_MASK;
665
666 if (product != PRR_PRODUCT_E3)
667 rcar_pwrc_set_self_refresh();
668 else
669 rcar_pwrc_set_self_refresh_e3();
670
671 #if PMIC_ROHM_BD9571
672 /* Set QLLM Cnt Disable */
673 for (i = 0; (i < PMIC_RETRY_MAX) && (qllm != 0); i++)
674 qllm = rcar_iic_dvfs_send(PMIC, PMIC_QLLM_CNT, 0);
675
676 /* Set trigger of power down to PMIV */
677 for (i = 0; (i < PMIC_RETRY_MAX) && (rc != 0) && (qllm == 0); i++) {
678 rc = rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode);
679 if (rc == 0) {
680 mode |= BIT_BKUP_CTRL_OUT;
681 rc = rcar_iic_dvfs_send(PMIC, PMIC_BKUP_MODE_CNT, mode);
682 }
683 }
684 #endif
685 wfi();
686
687 while (1)
688 ;
689 }
690
rcar_pwrc_set_suspend_to_ram(void)691 void rcar_pwrc_set_suspend_to_ram(void)
692 {
693 uintptr_t jump = (uintptr_t) &rcar_pwrc_go_suspend_to_ram;
694 uintptr_t stack = (uintptr_t) (DEVICE_SRAM_STACK_BASE +
695 DEVICE_SRAM_STACK_SIZE);
696 uint32_t sctlr;
697
698 rcar_pwrc_save_timer_state();
699
700 /* disable MMU */
701 sctlr = (uint32_t) read_sctlr_el3();
702 sctlr &= (uint32_t) ~SCTLR_EL3_M_BIT;
703 write_sctlr_el3((uint64_t) sctlr);
704
705 rcar_pwrc_switch_stack(jump, stack, NULL);
706 }
707
rcar_pwrc_init_suspend_to_ram(void)708 void rcar_pwrc_init_suspend_to_ram(void)
709 {
710 #if PMIC_ROHM_BD9571
711 uint8_t mode;
712
713 if (rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode))
714 panic();
715
716 mode &= (uint8_t) (~BIT_BKUP_CTRL_OUT);
717 if (rcar_iic_dvfs_send(PMIC, PMIC_BKUP_MODE_CNT, mode))
718 panic();
719 #endif
720 }
721
rcar_pwrc_suspend_to_ram(void)722 void rcar_pwrc_suspend_to_ram(void)
723 {
724 #if RCAR_SYSTEM_RESET_KEEPON_DDR
725 int32_t error;
726
727 error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, 0);
728 if (error) {
729 ERROR("Failed send KEEP10 init ret=%d\n", error);
730 return;
731 }
732 #endif
733 rcar_pwrc_set_suspend_to_ram();
734 }
735 #endif
736
rcar_pwrc_code_copy_to_system_ram(void)737 void rcar_pwrc_code_copy_to_system_ram(void)
738 {
739 int ret __attribute__ ((unused)); /* in assert */
740 uint32_t attr;
741 struct device_sram_t {
742 uintptr_t base;
743 size_t len;
744 } sram = {
745 .base = (uintptr_t) DEVICE_SRAM_BASE,
746 .len = DEVICE_SRAM_SIZE,
747 };
748 struct ddr_code_t {
749 void *base;
750 size_t len;
751 } code = {
752 .base = (void *) SRAM_COPY_START,
753 .len = SYSTEM_RAM_END - SYSTEM_RAM_START,
754 };
755
756 attr = MT_MEMORY | MT_RW | MT_SECURE | MT_EXECUTE_NEVER;
757 ret = xlat_change_mem_attributes(sram.base, sram.len, attr);
758 assert(ret == 0);
759
760 memcpy((void *)sram.base, code.base, code.len);
761 flush_dcache_range((uint64_t) sram.base, code.len);
762
763 attr = MT_MEMORY | MT_RO | MT_SECURE | MT_EXECUTE;
764 ret = xlat_change_mem_attributes(sram.base, sram.len, attr);
765 assert(ret == 0);
766
767 /* Invalidate instruction cache */
768 plat_invalidate_icache();
769 dsb();
770 isb();
771 }
772
rcar_pwrc_get_cluster(void)773 uint32_t rcar_pwrc_get_cluster(void)
774 {
775 uint32_t reg;
776
777 reg = mmio_read_32(RCAR_PRR);
778
779 if (reg & (1U << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX)))
780 return RCAR_CLUSTER_CA57;
781
782 if (reg & (1U << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
783 return RCAR_CLUSTER_CA53;
784
785 return RCAR_CLUSTER_A53A57;
786 }
787
rcar_pwrc_get_mpidr_cluster(u_register_t mpidr)788 uint32_t rcar_pwrc_get_mpidr_cluster(u_register_t mpidr)
789 {
790 uint32_t c = rcar_pwrc_get_cluster();
791
792 if (IS_A53A57(c)) {
793 if (mpidr & MPIDR_CLUSTER_MASK)
794 return RCAR_CLUSTER_CA53;
795
796 return RCAR_CLUSTER_CA57;
797 }
798
799 return c;
800 }
801
802 #if RCAR_LSI == RCAR_D3
rcar_pwrc_get_cpu_num(uint32_t c)803 uint32_t rcar_pwrc_get_cpu_num(uint32_t c)
804 {
805 return 1;
806 }
807 #else
rcar_pwrc_get_cpu_num(uint32_t c)808 uint32_t rcar_pwrc_get_cpu_num(uint32_t c)
809 {
810 uint32_t reg = mmio_read_32(RCAR_PRR);
811 uint32_t count = 0, i;
812
813 if (IS_A53A57(c) || IS_CA53(c)) {
814 if (reg & (1 << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX)))
815 goto count_ca57;
816
817 for (i = 0; i < RCAR_CA53CPU_NUM_MAX; i++) {
818 if (reg & (1 << (STATE_CA53_CPU + i)))
819 continue;
820 count++;
821 }
822 }
823
824 count_ca57:
825 if (IS_A53A57(c) || IS_CA57(c)) {
826 if (reg & (1U << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
827 goto done;
828
829 for (i = 0; i < RCAR_CA57CPU_NUM_MAX; i++) {
830 if (reg & (1 << (STATE_CA57_CPU + i)))
831 continue;
832 count++;
833 }
834 }
835
836 done:
837 return count;
838 }
839 #endif
840
rcar_pwrc_cpu_on_check(u_register_t mpidr)841 int32_t rcar_pwrc_cpu_on_check(u_register_t mpidr)
842 {
843 uint64_t i;
844 uint64_t j;
845 uint64_t cpu_count;
846 uintptr_t reg_PSTR;
847 uint32_t status;
848 uint64_t my_cpu;
849 int32_t rtn;
850 uint32_t my_cluster_type;
851 const uint32_t cluster_type[PLATFORM_CLUSTER_COUNT] = {
852 RCAR_CLUSTER_CA53,
853 RCAR_CLUSTER_CA57
854 };
855 const uintptr_t registerPSTR[PLATFORM_CLUSTER_COUNT] = {
856 RCAR_CA53PSTR,
857 RCAR_CA57PSTR
858 };
859
860 my_cluster_type = rcar_pwrc_get_cluster();
861
862 rtn = 0;
863 my_cpu = mpidr & ((uint64_t)(MPIDR_CPU_MASK));
864 for (i = 0U; i < ((uint64_t)(PLATFORM_CLUSTER_COUNT)); i++) {
865 cpu_count = rcar_pwrc_get_cpu_num(cluster_type[i]);
866 reg_PSTR = registerPSTR[i];
867 for (j = 0U; j < cpu_count; j++) {
868 if ((my_cluster_type != cluster_type[i]) || (my_cpu != j)) {
869 status = mmio_read_32(reg_PSTR) >> (j * 4U);
870 if ((status & 0x00000003U) == 0U) {
871 rtn--;
872 }
873 }
874 }
875 }
876
877 return rtn;
878 }
879