1 /*
2 * drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
3 * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
4 *
5 * Copyright (C) 2009 for Samsung Electronics
6 *
7 * BSP Support for Samsung's UDC driver
8 * available at:
9 * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
10 *
11 * State machine bugfixes:
12 * Marek Szyprowski <m.szyprowski@samsung.com>
13 *
14 * Ported to u-boot:
15 * Marek Szyprowski <m.szyprowski@samsung.com>
16 * Lukasz Majewski <l.majewski@samsumg.com>
17 *
18 * SPDX-License-Identifier: GPL-2.0+
19 */
20
21 static u8 clear_feature_num;
22 int clear_feature_flag;
23
24 /* Bulk-Only Mass Storage Reset (class-specific request) */
25 #define GET_MAX_LUN_REQUEST 0xFE
26 #define BOT_RESET_REQUEST 0xFF
27
dwc2_udc_ep0_zlp(struct dwc2_udc * dev)28 static inline void dwc2_udc_ep0_zlp(struct dwc2_udc *dev)
29 {
30 u32 ep_ctrl;
31
32 writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma);
33 writel(DIEPT_SIZ_PKT_CNT(1), ®->in_endp[EP0_CON].dieptsiz);
34
35 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
36 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
37 ®->in_endp[EP0_CON].diepctl);
38
39 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
40 __func__, readl(®->in_endp[EP0_CON].diepctl));
41 dev->ep0state = WAIT_FOR_IN_COMPLETE;
42 }
43
dwc2_udc_pre_setup(void)44 static void dwc2_udc_pre_setup(void)
45 {
46 u32 ep_ctrl;
47
48 debug_cond(DEBUG_IN_EP,
49 "%s : Prepare Setup packets.\n", __func__);
50
51 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
52 ®->out_endp[EP0_CON].doeptsiz);
53 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma);
54
55 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl);
56 writel(ep_ctrl|DEPCTL_EPENA, ®->out_endp[EP0_CON].doepctl);
57
58 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
59 __func__, readl(®->in_endp[EP0_CON].diepctl));
60 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
61 __func__, readl(®->out_endp[EP0_CON].doepctl));
62
63 }
64
dwc2_ep0_complete_out(void)65 static inline void dwc2_ep0_complete_out(void)
66 {
67 u32 ep_ctrl;
68
69 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
70 __func__, readl(®->in_endp[EP0_CON].diepctl));
71 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
72 __func__, readl(®->out_endp[EP0_CON].doepctl));
73
74 debug_cond(DEBUG_IN_EP,
75 "%s : Prepare Complete Out packet.\n", __func__);
76
77 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
78 ®->out_endp[EP0_CON].doeptsiz);
79 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma);
80
81 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl);
82 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
83 ®->out_endp[EP0_CON].doepctl);
84
85 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
86 __func__, readl(®->in_endp[EP0_CON].diepctl));
87 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
88 __func__, readl(®->out_endp[EP0_CON].doepctl));
89
90 }
91
92
setdma_rx(struct dwc2_ep * ep,struct dwc2_request * req)93 static int setdma_rx(struct dwc2_ep *ep, struct dwc2_request *req)
94 {
95 u32 *buf, ctrl;
96 u32 length, pktcnt;
97 u32 ep_num = ep_index(ep);
98
99 buf = req->req.buf + req->req.actual;
100 length = min_t(u32, req->req.length - req->req.actual,
101 ep_num ? DOEPT_SIZ_XFER_SIZE_MAX_EP : ep->ep.maxpacket);
102
103 ep->len = length;
104 ep->dma_buf = buf;
105
106 if (ep_num == EP0_CON || length == 0)
107 pktcnt = 1;
108 else
109 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
110
111 ctrl = readl(®->out_endp[ep_num].doepctl);
112
113 invalidate_dcache_range((unsigned long) ep->dma_buf,
114 (unsigned long) ep->dma_buf +
115 ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
116
117 writel((unsigned long) ep->dma_buf, ®->out_endp[ep_num].doepdma);
118 writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
119 ®->out_endp[ep_num].doeptsiz);
120 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->out_endp[ep_num].doepctl);
121
122 debug_cond(DEBUG_OUT_EP != 0,
123 "%s: EP%d RX DMA start : DOEPDMA = 0x%x,"
124 "DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n"
125 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
126 __func__, ep_num,
127 readl(®->out_endp[ep_num].doepdma),
128 readl(®->out_endp[ep_num].doeptsiz),
129 readl(®->out_endp[ep_num].doepctl),
130 buf, pktcnt, length);
131 return 0;
132
133 }
134
setdma_tx(struct dwc2_ep * ep,struct dwc2_request * req)135 static int setdma_tx(struct dwc2_ep *ep, struct dwc2_request *req)
136 {
137 u32 *buf, ctrl = 0;
138 u32 length, pktcnt;
139 u32 ep_num = ep_index(ep);
140
141 buf = req->req.buf + req->req.actual;
142 length = req->req.length - req->req.actual;
143
144 if (ep_num == EP0_CON)
145 length = min(length, (u32)ep_maxpacket(ep));
146
147 ep->len = length;
148 ep->dma_buf = buf;
149
150 flush_dcache_range((unsigned long) ep->dma_buf,
151 (unsigned long) ep->dma_buf +
152 ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
153
154 if (length == 0)
155 pktcnt = 1;
156 else
157 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
158
159 /* Flush the endpoint's Tx FIFO */
160 writel(TX_FIFO_NUMBER(ep->fifo_num), ®->grstctl);
161 writel(TX_FIFO_NUMBER(ep->fifo_num) | TX_FIFO_FLUSH, ®->grstctl);
162 while (readl(®->grstctl) & TX_FIFO_FLUSH)
163 ;
164
165 writel((unsigned long) ep->dma_buf, ®->in_endp[ep_num].diepdma);
166 writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length),
167 ®->in_endp[ep_num].dieptsiz);
168
169 ctrl = readl(®->in_endp[ep_num].diepctl);
170
171 /* Write the FIFO number to be used for this endpoint */
172 ctrl &= DIEPCTL_TX_FIFO_NUM_MASK;
173 ctrl |= DIEPCTL_TX_FIFO_NUM(ep->fifo_num);
174
175 /* Clear reserved (Next EP) bits */
176 ctrl = (ctrl&~(EP_MASK<<DEPCTL_NEXT_EP_BIT));
177
178 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->in_endp[ep_num].diepctl);
179
180 debug_cond(DEBUG_IN_EP,
181 "%s:EP%d TX DMA start : DIEPDMA0 = 0x%x,"
182 "DIEPTSIZ0 = 0x%x, DIEPCTL0 = 0x%x\n"
183 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
184 __func__, ep_num,
185 readl(®->in_endp[ep_num].diepdma),
186 readl(®->in_endp[ep_num].dieptsiz),
187 readl(®->in_endp[ep_num].diepctl),
188 buf, pktcnt, length);
189
190 return length;
191 }
192
complete_rx(struct dwc2_udc * dev,u8 ep_num)193 static void complete_rx(struct dwc2_udc *dev, u8 ep_num)
194 {
195 struct dwc2_ep *ep = &dev->ep[ep_num];
196 struct dwc2_request *req = NULL;
197 u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
198
199 if (list_empty(&ep->queue)) {
200 debug_cond(DEBUG_OUT_EP != 0,
201 "%s: RX DMA done : NULL REQ on OUT EP-%d\n",
202 __func__, ep_num);
203 return;
204
205 }
206
207 req = list_entry(ep->queue.next, struct dwc2_request, queue);
208 ep_tsr = readl(®->out_endp[ep_num].doeptsiz);
209
210 if (ep_num == EP0_CON)
211 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP0);
212 else
213 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP);
214
215 xfer_size = ep->len - xfer_size;
216
217 /*
218 * NOTE:
219 *
220 * Please be careful with proper buffer allocation for USB request,
221 * which needs to be aligned to CONFIG_SYS_CACHELINE_SIZE, not only
222 * with starting address, but also its size shall be a cache line
223 * multiplication.
224 *
225 * This will prevent from corruption of data allocated immediatelly
226 * before or after the buffer.
227 *
228 * For armv7, the cache_v7.c provides proper code to emit "ERROR"
229 * message to warn users.
230 */
231 invalidate_dcache_range((unsigned long) ep->dma_buf,
232 (unsigned long) ep->dma_buf +
233 ROUND(xfer_size, CONFIG_SYS_CACHELINE_SIZE));
234
235 req->req.actual += min(xfer_size, req->req.length - req->req.actual);
236 is_short = !!(xfer_size % ep->ep.maxpacket);
237
238 debug_cond(DEBUG_OUT_EP != 0,
239 "%s: RX DMA done : ep = %d, rx bytes = %d/%d, "
240 "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n",
241 __func__, ep_num, req->req.actual, req->req.length,
242 is_short, ep_tsr, req->req.length - req->req.actual);
243
244 if (is_short || req->req.actual == req->req.length) {
245 if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) {
246 debug_cond(DEBUG_OUT_EP != 0, " => Send ZLP\n");
247 dwc2_udc_ep0_zlp(dev);
248 /* packet will be completed in complete_tx() */
249 dev->ep0state = WAIT_FOR_IN_COMPLETE;
250 } else {
251 done(ep, req, 0);
252
253 if (!list_empty(&ep->queue)) {
254 req = list_entry(ep->queue.next,
255 struct dwc2_request, queue);
256 debug_cond(DEBUG_OUT_EP != 0,
257 "%s: Next Rx request start...\n",
258 __func__);
259 setdma_rx(ep, req);
260 }
261 }
262 } else
263 setdma_rx(ep, req);
264 }
265
complete_tx(struct dwc2_udc * dev,u8 ep_num)266 static void complete_tx(struct dwc2_udc *dev, u8 ep_num)
267 {
268 struct dwc2_ep *ep = &dev->ep[ep_num];
269 struct dwc2_request *req;
270 u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
271 u32 last;
272
273 if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) {
274 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
275 dwc2_ep0_complete_out();
276 return;
277 }
278
279 if (list_empty(&ep->queue)) {
280 debug_cond(DEBUG_IN_EP,
281 "%s: TX DMA done : NULL REQ on IN EP-%d\n",
282 __func__, ep_num);
283 return;
284
285 }
286
287 req = list_entry(ep->queue.next, struct dwc2_request, queue);
288
289 ep_tsr = readl(®->in_endp[ep_num].dieptsiz);
290
291 xfer_size = ep->len;
292 is_short = (xfer_size < ep->ep.maxpacket);
293 req->req.actual += min(xfer_size, req->req.length - req->req.actual);
294
295 debug_cond(DEBUG_IN_EP,
296 "%s: TX DMA done : ep = %d, tx bytes = %d/%d, "
297 "is_short = %d, DIEPTSIZ = 0x%x, remained bytes = %d\n",
298 __func__, ep_num, req->req.actual, req->req.length,
299 is_short, ep_tsr, req->req.length - req->req.actual);
300
301 if (ep_num == 0) {
302 if (dev->ep0state == DATA_STATE_XMIT) {
303 debug_cond(DEBUG_IN_EP,
304 "%s: ep_num = %d, ep0stat =="
305 "DATA_STATE_XMIT\n",
306 __func__, ep_num);
307 last = write_fifo_ep0(ep, req);
308 if (last)
309 dev->ep0state = WAIT_FOR_COMPLETE;
310 } else if (dev->ep0state == WAIT_FOR_IN_COMPLETE) {
311 debug_cond(DEBUG_IN_EP,
312 "%s: ep_num = %d, completing request\n",
313 __func__, ep_num);
314 done(ep, req, 0);
315 dev->ep0state = WAIT_FOR_SETUP;
316 } else if (dev->ep0state == WAIT_FOR_COMPLETE) {
317 debug_cond(DEBUG_IN_EP,
318 "%s: ep_num = %d, completing request\n",
319 __func__, ep_num);
320 done(ep, req, 0);
321 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
322 dwc2_ep0_complete_out();
323 } else {
324 debug_cond(DEBUG_IN_EP,
325 "%s: ep_num = %d, invalid ep state\n",
326 __func__, ep_num);
327 }
328 return;
329 }
330
331 if (req->req.actual == req->req.length)
332 done(ep, req, 0);
333
334 if (!list_empty(&ep->queue)) {
335 req = list_entry(ep->queue.next, struct dwc2_request, queue);
336 debug_cond(DEBUG_IN_EP,
337 "%s: Next Tx request start...\n", __func__);
338 setdma_tx(ep, req);
339 }
340 }
341
dwc2_udc_check_tx_queue(struct dwc2_udc * dev,u8 ep_num)342 static inline void dwc2_udc_check_tx_queue(struct dwc2_udc *dev, u8 ep_num)
343 {
344 struct dwc2_ep *ep = &dev->ep[ep_num];
345 struct dwc2_request *req;
346
347 debug_cond(DEBUG_IN_EP,
348 "%s: Check queue, ep_num = %d\n", __func__, ep_num);
349
350 if (!list_empty(&ep->queue)) {
351 req = list_entry(ep->queue.next, struct dwc2_request, queue);
352 debug_cond(DEBUG_IN_EP,
353 "%s: Next Tx request(0x%p) start...\n",
354 __func__, req);
355
356 if (ep_is_in(ep))
357 setdma_tx(ep, req);
358 else
359 setdma_rx(ep, req);
360 } else {
361 debug_cond(DEBUG_IN_EP,
362 "%s: NULL REQ on IN EP-%d\n", __func__, ep_num);
363
364 return;
365 }
366
367 }
368
process_ep_in_intr(struct dwc2_udc * dev)369 static void process_ep_in_intr(struct dwc2_udc *dev)
370 {
371 u32 ep_intr, ep_intr_status;
372 u8 ep_num = 0;
373
374 ep_intr = readl(®->daint);
375 debug_cond(DEBUG_IN_EP,
376 "*** %s: EP In interrupt : DAINT = 0x%x\n", __func__, ep_intr);
377
378 ep_intr &= DAINT_MASK;
379
380 while (ep_intr) {
381 if (ep_intr & DAINT_IN_EP_INT(1)) {
382 ep_intr_status = readl(®->in_endp[ep_num].diepint);
383 debug_cond(DEBUG_IN_EP,
384 "\tEP%d-IN : DIEPINT = 0x%x\n",
385 ep_num, ep_intr_status);
386
387 /* Interrupt Clear */
388 writel(ep_intr_status, ®->in_endp[ep_num].diepint);
389
390 if (ep_intr_status & TRANSFER_DONE) {
391 complete_tx(dev, ep_num);
392
393 if (ep_num == 0) {
394 if (dev->ep0state ==
395 WAIT_FOR_IN_COMPLETE)
396 dev->ep0state = WAIT_FOR_SETUP;
397
398 if (dev->ep0state == WAIT_FOR_SETUP)
399 dwc2_udc_pre_setup();
400
401 /* continue transfer after
402 set_clear_halt for DMA mode */
403 if (clear_feature_flag == 1) {
404 dwc2_udc_check_tx_queue(dev,
405 clear_feature_num);
406 clear_feature_flag = 0;
407 }
408 }
409 }
410 }
411 ep_num++;
412 ep_intr >>= 1;
413 }
414 }
415
process_ep_out_intr(struct dwc2_udc * dev)416 static void process_ep_out_intr(struct dwc2_udc *dev)
417 {
418 u32 ep_intr, ep_intr_status;
419 u8 ep_num = 0;
420
421 ep_intr = readl(®->daint);
422 debug_cond(DEBUG_OUT_EP != 0,
423 "*** %s: EP OUT interrupt : DAINT = 0x%x\n",
424 __func__, ep_intr);
425
426 ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK;
427
428 while (ep_intr) {
429 if (ep_intr & 0x1) {
430 ep_intr_status = readl(®->out_endp[ep_num].doepint);
431 debug_cond(DEBUG_OUT_EP != 0,
432 "\tEP%d-OUT : DOEPINT = 0x%x\n",
433 ep_num, ep_intr_status);
434
435 /* Interrupt Clear */
436 writel(ep_intr_status, ®->out_endp[ep_num].doepint);
437
438 if (ep_num == 0) {
439 if (ep_intr_status & TRANSFER_DONE) {
440 if (dev->ep0state !=
441 WAIT_FOR_OUT_COMPLETE)
442 complete_rx(dev, ep_num);
443 else {
444 dev->ep0state = WAIT_FOR_SETUP;
445 dwc2_udc_pre_setup();
446 }
447 }
448
449 if (ep_intr_status &
450 CTRL_OUT_EP_SETUP_PHASE_DONE) {
451 debug_cond(DEBUG_OUT_EP != 0,
452 "SETUP packet arrived\n");
453 dwc2_handle_ep0(dev);
454 }
455 } else {
456 if (ep_intr_status & TRANSFER_DONE)
457 complete_rx(dev, ep_num);
458 }
459 }
460 ep_num++;
461 ep_intr >>= 1;
462 }
463 }
464
465 /*
466 * usb client interrupt handler.
467 */
dwc2_udc_irq(int irq,void * _dev)468 static int dwc2_udc_irq(int irq, void *_dev)
469 {
470 struct dwc2_udc *dev = _dev;
471 u32 intr_status, gotgint;
472 u32 usb_status, gintmsk;
473 unsigned long flags = 0;
474
475 spin_lock_irqsave(&dev->lock, flags);
476
477 intr_status = readl(®->gintsts);
478 gintmsk = readl(®->gintmsk);
479
480 debug_cond(DEBUG_ISR,
481 "\n*** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x,"
482 "DAINT : 0x%x, DAINTMSK : 0x%x\n",
483 __func__, intr_status, state_names[dev->ep0state], gintmsk,
484 readl(®->daint), readl(®->daintmsk));
485
486 if (!intr_status) {
487 spin_unlock_irqrestore(&dev->lock, flags);
488 return IRQ_HANDLED;
489 }
490
491 if (intr_status & INT_ENUMDONE) {
492 debug_cond(DEBUG_ISR, "\tSpeed Detection interrupt\n");
493
494 writel(INT_ENUMDONE, ®->gintsts);
495 usb_status = (readl(®->dsts) & 0x6);
496
497 if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) {
498 debug_cond(DEBUG_ISR,
499 "\t\tFull Speed Detection\n");
500 set_max_pktsize(dev, USB_SPEED_FULL);
501
502 } else {
503 debug_cond(DEBUG_ISR,
504 "\t\tHigh Speed Detection : 0x%x\n",
505 usb_status);
506 set_max_pktsize(dev, USB_SPEED_HIGH);
507 }
508 }
509
510 if (intr_status & INT_EARLY_SUSPEND) {
511 debug_cond(DEBUG_ISR, "\tEarly suspend interrupt\n");
512 writel(INT_EARLY_SUSPEND, ®->gintsts);
513 }
514
515 if (intr_status & INT_SUSPEND) {
516 usb_status = readl(®->dsts);
517 debug_cond(DEBUG_ISR,
518 "\tSuspend interrupt :(DSTS):0x%x\n", usb_status);
519 writel(INT_SUSPEND, ®->gintsts);
520
521 if (dev->gadget.speed != USB_SPEED_UNKNOWN
522 && dev->driver) {
523 if (dev->driver->suspend)
524 dev->driver->suspend(&dev->gadget);
525 }
526 }
527
528 if (intr_status & INT_OTG) {
529 gotgint = readl(®->gotgint);
530 debug_cond(DEBUG_ISR,
531 "\tOTG interrupt: (GOTGINT):0x%x\n", gotgint);
532
533 if (gotgint & GOTGINT_SES_END_DET) {
534 debug_cond(DEBUG_ISR, "\t\tSession End Detected\n");
535 /* Let gadget detect disconnected state */
536 if (dev->driver->disconnect) {
537 spin_unlock_irqrestore(&dev->lock, flags);
538 dev->driver->disconnect(&dev->gadget);
539 spin_lock_irqsave(&dev->lock, flags);
540 }
541 }
542 writel(gotgint, ®->gotgint);
543 }
544
545 if (intr_status & INT_RESUME) {
546 debug_cond(DEBUG_ISR, "\tResume interrupt\n");
547 writel(INT_RESUME, ®->gintsts);
548
549 if (dev->gadget.speed != USB_SPEED_UNKNOWN
550 && dev->driver
551 && dev->driver->resume) {
552
553 dev->driver->resume(&dev->gadget);
554 }
555 }
556
557 if (intr_status & INT_RESET) {
558 u32 temp;
559 u32 connected = dev->connected;
560
561 usb_status = readl(®->gotgctl);
562 debug_cond(DEBUG_ISR,
563 "\tReset interrupt - (GOTGCTL):0x%x\n", usb_status);
564 writel(INT_RESET, ®->gintsts);
565
566 if (((usb_status & 0xc0000) == (0x3 << 18)) ||
567 dev->pdata->force_b_session_valid) {
568 if (reset_available) {
569 debug_cond(DEBUG_ISR,
570 "\t\tOTG core got reset (%d)!!\n",
571 reset_available);
572 /* Reset device address to zero */
573 temp = readl(®->dcfg);
574 temp &= ~DCFG_DEVADDR_MASK;
575 writel(temp, ®->dcfg);
576
577 /* Soft reset the core if connected */
578 if (connected)
579 reconfig_usbd(dev);
580
581 dev->ep0state = WAIT_FOR_SETUP;
582 reset_available = 0;
583 dwc2_udc_pre_setup();
584 } else
585 reset_available = 1;
586
587 } else {
588 reset_available = 1;
589 debug_cond(DEBUG_ISR,
590 "\t\tRESET handling skipped\n");
591 }
592 }
593
594 if (intr_status & INT_IN_EP)
595 process_ep_in_intr(dev);
596
597 if (intr_status & INT_OUT_EP)
598 process_ep_out_intr(dev);
599
600 spin_unlock_irqrestore(&dev->lock, flags);
601
602 return IRQ_HANDLED;
603 }
604
605 /** Queue one request
606 * Kickstart transfer if needed
607 */
dwc2_queue(struct usb_ep * _ep,struct usb_request * _req,gfp_t gfp_flags)608 static int dwc2_queue(struct usb_ep *_ep, struct usb_request *_req,
609 gfp_t gfp_flags)
610 {
611 struct dwc2_request *req;
612 struct dwc2_ep *ep;
613 struct dwc2_udc *dev;
614 unsigned long flags = 0;
615 u32 ep_num, gintsts;
616
617 req = container_of(_req, struct dwc2_request, req);
618 if (unlikely(!_req || !_req->complete || !_req->buf
619 || !list_empty(&req->queue))) {
620
621 debug("%s: bad params\n", __func__);
622 return -EINVAL;
623 }
624
625 ep = container_of(_ep, struct dwc2_ep, ep);
626
627 if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
628
629 debug("%s: bad ep: %s, %d, %p\n", __func__,
630 ep->ep.name, !ep->desc, _ep);
631 return -EINVAL;
632 }
633
634 ep_num = ep_index(ep);
635 dev = ep->dev;
636 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
637
638 debug("%s: bogus device state %p\n", __func__, dev->driver);
639 return -ESHUTDOWN;
640 }
641
642 spin_lock_irqsave(&dev->lock, flags);
643
644 _req->status = -EINPROGRESS;
645 _req->actual = 0;
646
647 /* kickstart this i/o queue? */
648 debug("\n*** %s: %s-%s req = %p, len = %d, buf = %p"
649 "Q empty = %d, stopped = %d\n",
650 __func__, _ep->name, ep_is_in(ep) ? "in" : "out",
651 _req, _req->length, _req->buf,
652 list_empty(&ep->queue), ep->stopped);
653
654 #ifdef DEBUG
655 {
656 int i, len = _req->length;
657
658 printf("pkt = ");
659 if (len > 64)
660 len = 64;
661 for (i = 0; i < len; i++) {
662 printf("%02x", ((u8 *)_req->buf)[i]);
663 if ((i & 7) == 7)
664 printf(" ");
665 }
666 printf("\n");
667 }
668 #endif
669
670 if (list_empty(&ep->queue) && !ep->stopped) {
671
672 if (ep_num == 0) {
673 /* EP0 */
674 list_add_tail(&req->queue, &ep->queue);
675 dwc2_ep0_kick(dev, ep);
676 req = 0;
677
678 } else if (ep_is_in(ep)) {
679 gintsts = readl(®->gintsts);
680 debug_cond(DEBUG_IN_EP,
681 "%s: ep_is_in, DWC2_UDC_OTG_GINTSTS=0x%x\n",
682 __func__, gintsts);
683
684 setdma_tx(ep, req);
685 } else {
686 gintsts = readl(®->gintsts);
687 debug_cond(DEBUG_OUT_EP != 0,
688 "%s:ep_is_out, DWC2_UDC_OTG_GINTSTS=0x%x\n",
689 __func__, gintsts);
690
691 setdma_rx(ep, req);
692 }
693 }
694
695 /* pio or dma irq handler advances the queue. */
696 if (likely(req != 0))
697 list_add_tail(&req->queue, &ep->queue);
698
699 spin_unlock_irqrestore(&dev->lock, flags);
700
701 return 0;
702 }
703
704 /****************************************************************/
705 /* End Point 0 related functions */
706 /****************************************************************/
707
708 /* return: 0 = still running, 1 = completed, negative = errno */
write_fifo_ep0(struct dwc2_ep * ep,struct dwc2_request * req)709 static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req)
710 {
711 u32 max;
712 unsigned count;
713 int is_last;
714
715 max = ep_maxpacket(ep);
716
717 debug_cond(DEBUG_EP0 != 0, "%s: max = %d\n", __func__, max);
718
719 count = setdma_tx(ep, req);
720
721 /* last packet is usually short (or a zlp) */
722 if (likely(count != max))
723 is_last = 1;
724 else {
725 if (likely(req->req.length != req->req.actual + count)
726 || req->req.zero)
727 is_last = 0;
728 else
729 is_last = 1;
730 }
731
732 debug_cond(DEBUG_EP0 != 0,
733 "%s: wrote %s %d bytes%s %d left %p\n", __func__,
734 ep->ep.name, count,
735 is_last ? "/L" : "",
736 req->req.length - req->req.actual - count, req);
737
738 /* requests complete when all IN data is in the FIFO */
739 if (is_last) {
740 ep->dev->ep0state = WAIT_FOR_SETUP;
741 return 1;
742 }
743
744 return 0;
745 }
746
dwc2_fifo_read(struct dwc2_ep * ep,void * cp,int max)747 static int dwc2_fifo_read(struct dwc2_ep *ep, void *cp, int max)
748 {
749 invalidate_dcache_range((unsigned long)cp, (unsigned long)cp +
750 ROUND(max, CONFIG_SYS_CACHELINE_SIZE));
751
752 debug_cond(DEBUG_EP0 != 0,
753 "%s: bytes=%d, ep_index=%d 0x%p\n", __func__,
754 max, ep_index(ep), cp);
755
756 return max;
757 }
758
759 /**
760 * udc_set_address - set the USB address for this device
761 * @address:
762 *
763 * Called from control endpoint function
764 * after it decodes a set address setup packet.
765 */
udc_set_address(struct dwc2_udc * dev,unsigned char address)766 static void udc_set_address(struct dwc2_udc *dev, unsigned char address)
767 {
768 u32 ctrl = readl(®->dcfg);
769 writel(DEVICE_ADDRESS(address) | ctrl, ®->dcfg);
770
771 dwc2_udc_ep0_zlp(dev);
772
773 debug_cond(DEBUG_EP0 != 0,
774 "%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n",
775 __func__, address, readl(®->dcfg));
776
777 dev->usb_address = address;
778 }
779
dwc2_udc_ep0_set_stall(struct dwc2_ep * ep)780 static inline void dwc2_udc_ep0_set_stall(struct dwc2_ep *ep)
781 {
782 struct dwc2_udc *dev;
783 u32 ep_ctrl = 0;
784
785 dev = ep->dev;
786 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
787
788 /* set the disable and stall bits */
789 if (ep_ctrl & DEPCTL_EPENA)
790 ep_ctrl |= DEPCTL_EPDIS;
791
792 ep_ctrl |= DEPCTL_STALL;
793
794 writel(ep_ctrl, ®->in_endp[EP0_CON].diepctl);
795
796 debug_cond(DEBUG_EP0 != 0,
797 "%s: set ep%d stall, DIEPCTL0 = 0x%p\n",
798 __func__, ep_index(ep), ®->in_endp[EP0_CON].diepctl);
799 /*
800 * The application can only set this bit, and the core clears it,
801 * when a SETUP token is received for this endpoint
802 */
803 dev->ep0state = WAIT_FOR_SETUP;
804
805 dwc2_udc_pre_setup();
806 }
807
dwc2_ep0_read(struct dwc2_udc * dev)808 static void dwc2_ep0_read(struct dwc2_udc *dev)
809 {
810 struct dwc2_request *req;
811 struct dwc2_ep *ep = &dev->ep[0];
812
813 if (!list_empty(&ep->queue)) {
814 req = list_entry(ep->queue.next, struct dwc2_request, queue);
815
816 } else {
817 debug("%s: ---> BUG\n", __func__);
818 BUG();
819 return;
820 }
821
822 debug_cond(DEBUG_EP0 != 0,
823 "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
824 __func__, req, req->req.length, req->req.actual);
825
826 if (req->req.length == 0) {
827 /* zlp for Set_configuration, Set_interface,
828 * or Bulk-Only mass storge reset */
829
830 ep->len = 0;
831 dwc2_udc_ep0_zlp(dev);
832
833 debug_cond(DEBUG_EP0 != 0,
834 "%s: req.length = 0, bRequest = %d\n",
835 __func__, usb_ctrl->bRequest);
836 return;
837 }
838
839 setdma_rx(ep, req);
840 }
841
842 /*
843 * DATA_STATE_XMIT
844 */
dwc2_ep0_write(struct dwc2_udc * dev)845 static int dwc2_ep0_write(struct dwc2_udc *dev)
846 {
847 struct dwc2_request *req;
848 struct dwc2_ep *ep = &dev->ep[0];
849 int ret, need_zlp = 0;
850
851 if (list_empty(&ep->queue))
852 req = 0;
853 else
854 req = list_entry(ep->queue.next, struct dwc2_request, queue);
855
856 if (!req) {
857 debug_cond(DEBUG_EP0 != 0, "%s: NULL REQ\n", __func__);
858 return 0;
859 }
860
861 debug_cond(DEBUG_EP0 != 0,
862 "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
863 __func__, req, req->req.length, req->req.actual);
864
865 if (req->req.length - req->req.actual == ep0_fifo_size) {
866 /* Next write will end with the packet size, */
867 /* so we need Zero-length-packet */
868 need_zlp = 1;
869 }
870
871 ret = write_fifo_ep0(ep, req);
872
873 if ((ret == 1) && !need_zlp) {
874 /* Last packet */
875 dev->ep0state = WAIT_FOR_COMPLETE;
876 debug_cond(DEBUG_EP0 != 0,
877 "%s: finished, waiting for status\n", __func__);
878
879 } else {
880 dev->ep0state = DATA_STATE_XMIT;
881 debug_cond(DEBUG_EP0 != 0,
882 "%s: not finished\n", __func__);
883 }
884
885 return 1;
886 }
887
dwc2_udc_get_status(struct dwc2_udc * dev,struct usb_ctrlrequest * crq)888 static int dwc2_udc_get_status(struct dwc2_udc *dev,
889 struct usb_ctrlrequest *crq)
890 {
891 u8 ep_num = crq->wIndex & 0x7F;
892 u16 g_status = 0;
893 u32 ep_ctrl;
894
895 debug_cond(DEBUG_SETUP != 0,
896 "%s: *** USB_REQ_GET_STATUS\n", __func__);
897 printf("crq->brequest:0x%x\n", crq->bRequestType & USB_RECIP_MASK);
898 switch (crq->bRequestType & USB_RECIP_MASK) {
899 case USB_RECIP_INTERFACE:
900 g_status = 0;
901 debug_cond(DEBUG_SETUP != 0,
902 "\tGET_STATUS:USB_RECIP_INTERFACE, g_stauts = %d\n",
903 g_status);
904 break;
905
906 case USB_RECIP_DEVICE:
907 g_status = 0x1; /* Self powered */
908 debug_cond(DEBUG_SETUP != 0,
909 "\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n",
910 g_status);
911 break;
912
913 case USB_RECIP_ENDPOINT:
914 if (crq->wLength > 2) {
915 debug_cond(DEBUG_SETUP != 0,
916 "\tGET_STATUS:Not support EP or wLength\n");
917 return 1;
918 }
919
920 g_status = dev->ep[ep_num].stopped;
921 debug_cond(DEBUG_SETUP != 0,
922 "\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n",
923 g_status);
924
925 break;
926
927 default:
928 return 1;
929 }
930
931 memcpy(usb_ctrl, &g_status, sizeof(g_status));
932
933 flush_dcache_range((unsigned long) usb_ctrl,
934 (unsigned long) usb_ctrl +
935 ROUND(sizeof(g_status), CONFIG_SYS_CACHELINE_SIZE));
936
937 writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma);
938 writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2),
939 ®->in_endp[EP0_CON].dieptsiz);
940
941 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
942 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
943 ®->in_endp[EP0_CON].diepctl);
944 dev->ep0state = WAIT_FOR_NULL_COMPLETE;
945
946 return 0;
947 }
948
dwc2_udc_set_nak(struct dwc2_ep * ep)949 static void dwc2_udc_set_nak(struct dwc2_ep *ep)
950 {
951 u8 ep_num;
952 u32 ep_ctrl = 0;
953
954 ep_num = ep_index(ep);
955 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
956
957 if (ep_is_in(ep)) {
958 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
959 ep_ctrl |= DEPCTL_SNAK;
960 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
961 debug("%s: set NAK, DIEPCTL%d = 0x%x\n",
962 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
963 } else {
964 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
965 ep_ctrl |= DEPCTL_SNAK;
966 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
967 debug("%s: set NAK, DOEPCTL%d = 0x%x\n",
968 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
969 }
970
971 return;
972 }
973
974
dwc2_udc_ep_set_stall(struct dwc2_ep * ep)975 static void dwc2_udc_ep_set_stall(struct dwc2_ep *ep)
976 {
977 u8 ep_num;
978 u32 ep_ctrl = 0;
979
980 ep_num = ep_index(ep);
981 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
982
983 if (ep_is_in(ep)) {
984 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
985
986 /* set the disable and stall bits */
987 if (ep_ctrl & DEPCTL_EPENA)
988 ep_ctrl |= DEPCTL_EPDIS;
989
990 ep_ctrl |= DEPCTL_STALL;
991
992 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
993 debug("%s: set stall, DIEPCTL%d = 0x%x\n",
994 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
995
996 } else {
997 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
998
999 /* set the stall bit */
1000 ep_ctrl |= DEPCTL_STALL;
1001
1002 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1003 debug("%s: set stall, DOEPCTL%d = 0x%x\n",
1004 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
1005 }
1006
1007 return;
1008 }
1009
dwc2_udc_ep_clear_stall(struct dwc2_ep * ep)1010 static void dwc2_udc_ep_clear_stall(struct dwc2_ep *ep)
1011 {
1012 u8 ep_num;
1013 u32 ep_ctrl = 0;
1014
1015 ep_num = ep_index(ep);
1016 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
1017
1018 if (ep_is_in(ep)) {
1019 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
1020
1021 /* clear stall bit */
1022 ep_ctrl &= ~DEPCTL_STALL;
1023
1024 /*
1025 * USB Spec 9.4.5: For endpoints using data toggle, regardless
1026 * of whether an endpoint has the Halt feature set, a
1027 * ClearFeature(ENDPOINT_HALT) request always results in the
1028 * data toggle being reinitialized to DATA0.
1029 */
1030 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1031 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1032 ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1033 }
1034
1035 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
1036 debug("%s: cleared stall, DIEPCTL%d = 0x%x\n",
1037 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
1038
1039 } else {
1040 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
1041
1042 /* clear stall bit */
1043 ep_ctrl &= ~DEPCTL_STALL;
1044
1045 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1046 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1047 ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1048 }
1049
1050 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1051 debug("%s: cleared stall, DOEPCTL%d = 0x%x\n",
1052 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
1053 }
1054
1055 return;
1056 }
1057
dwc2_udc_set_halt(struct usb_ep * _ep,int value)1058 static int dwc2_udc_set_halt(struct usb_ep *_ep, int value)
1059 {
1060 struct dwc2_ep *ep;
1061 struct dwc2_udc *dev;
1062 unsigned long flags = 0;
1063 u8 ep_num;
1064
1065 ep = container_of(_ep, struct dwc2_ep, ep);
1066 ep_num = ep_index(ep);
1067
1068 if (unlikely(!_ep || !ep->desc || ep_num == EP0_CON ||
1069 ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC)) {
1070 debug("%s: %s bad ep or descriptor\n", __func__, ep->ep.name);
1071 return -EINVAL;
1072 }
1073
1074 /* Attempt to halt IN ep will fail if any transfer requests
1075 * are still queue */
1076 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1077 debug("%s: %s queue not empty, req = %p\n",
1078 __func__, ep->ep.name,
1079 list_entry(ep->queue.next, struct dwc2_request, queue));
1080
1081 return -EAGAIN;
1082 }
1083
1084 dev = ep->dev;
1085 debug("%s: ep_num = %d, value = %d\n", __func__, ep_num, value);
1086
1087 spin_lock_irqsave(&dev->lock, flags);
1088
1089 if (value == 0) {
1090 ep->stopped = 0;
1091 dwc2_udc_ep_clear_stall(ep);
1092 } else {
1093 if (ep_num == 0)
1094 dev->ep0state = WAIT_FOR_SETUP;
1095
1096 ep->stopped = 1;
1097 dwc2_udc_ep_set_stall(ep);
1098 }
1099
1100 spin_unlock_irqrestore(&dev->lock, flags);
1101
1102 return 0;
1103 }
1104
dwc2_udc_ep_activate(struct dwc2_ep * ep)1105 static void dwc2_udc_ep_activate(struct dwc2_ep *ep)
1106 {
1107 u8 ep_num;
1108 u32 ep_ctrl = 0, daintmsk = 0;
1109
1110 ep_num = ep_index(ep);
1111
1112 /* Read DEPCTLn register */
1113 if (ep_is_in(ep)) {
1114 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
1115 daintmsk = 1 << ep_num;
1116 } else {
1117 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
1118 daintmsk = (1 << ep_num) << DAINT_OUT_BIT;
1119 }
1120
1121 debug("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n",
1122 __func__, ep_num, ep_ctrl, ep_is_in(ep));
1123
1124 /* If the EP is already active don't change the EP Control
1125 * register. */
1126 if (!(ep_ctrl & DEPCTL_USBACTEP)) {
1127 ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) |
1128 (ep->bmAttributes << DEPCTL_TYPE_BIT);
1129 ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) |
1130 (ep->ep.maxpacket << DEPCTL_MPS_BIT);
1131 ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK);
1132
1133 if (ep_is_in(ep)) {
1134 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
1135 debug("%s: USB Ative EP%d, DIEPCTRL%d = 0x%x\n",
1136 __func__, ep_num, ep_num,
1137 readl(®->in_endp[ep_num].diepctl));
1138 } else {
1139 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1140 debug("%s: USB Ative EP%d, DOEPCTRL%d = 0x%x\n",
1141 __func__, ep_num, ep_num,
1142 readl(®->out_endp[ep_num].doepctl));
1143 }
1144 }
1145
1146 /* Unmask EP Interrtupt */
1147 writel(readl(®->daintmsk)|daintmsk, ®->daintmsk);
1148 debug("%s: DAINTMSK = 0x%x\n", __func__, readl(®->daintmsk));
1149
1150 }
1151
dwc2_udc_clear_feature(struct usb_ep * _ep)1152 static int dwc2_udc_clear_feature(struct usb_ep *_ep)
1153 {
1154 struct dwc2_udc *dev;
1155 struct dwc2_ep *ep;
1156 u8 ep_num;
1157
1158 ep = container_of(_ep, struct dwc2_ep, ep);
1159 ep_num = ep_index(ep);
1160
1161 dev = ep->dev;
1162 debug_cond(DEBUG_SETUP != 0,
1163 "%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n",
1164 __func__, ep_num, ep_is_in(ep), clear_feature_flag);
1165
1166 if (usb_ctrl->wLength != 0) {
1167 debug_cond(DEBUG_SETUP != 0,
1168 "\tCLEAR_FEATURE: wLength is not zero.....\n");
1169 return 1;
1170 }
1171
1172 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1173 case USB_RECIP_DEVICE:
1174 switch (usb_ctrl->wValue) {
1175 case USB_DEVICE_REMOTE_WAKEUP:
1176 debug_cond(DEBUG_SETUP != 0,
1177 "\tOFF:USB_DEVICE_REMOTE_WAKEUP\n");
1178 break;
1179
1180 case USB_DEVICE_TEST_MODE:
1181 debug_cond(DEBUG_SETUP != 0,
1182 "\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n");
1183 /** @todo Add CLEAR_FEATURE for TEST modes. */
1184 break;
1185 }
1186
1187 dwc2_udc_ep0_zlp(dev);
1188 break;
1189
1190 case USB_RECIP_ENDPOINT:
1191 debug_cond(DEBUG_SETUP != 0,
1192 "\tCLEAR_FEATURE:USB_RECIP_ENDPOINT, wValue = %d\n",
1193 usb_ctrl->wValue);
1194
1195 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1196 if (ep_num == 0) {
1197 dwc2_udc_ep0_set_stall(ep);
1198 return 0;
1199 }
1200
1201 dwc2_udc_ep0_zlp(dev);
1202
1203 dwc2_udc_ep_clear_stall(ep);
1204 dwc2_udc_ep_activate(ep);
1205 ep->stopped = 0;
1206
1207 clear_feature_num = ep_num;
1208 clear_feature_flag = 1;
1209 }
1210 break;
1211 }
1212
1213 return 0;
1214 }
1215
dwc2_udc_set_feature(struct usb_ep * _ep)1216 static int dwc2_udc_set_feature(struct usb_ep *_ep)
1217 {
1218 struct dwc2_udc *dev;
1219 struct dwc2_ep *ep;
1220 u8 ep_num;
1221
1222 ep = container_of(_ep, struct dwc2_ep, ep);
1223 ep_num = ep_index(ep);
1224 dev = ep->dev;
1225
1226 debug_cond(DEBUG_SETUP != 0,
1227 "%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n",
1228 __func__, ep_num);
1229
1230 if (usb_ctrl->wLength != 0) {
1231 debug_cond(DEBUG_SETUP != 0,
1232 "\tSET_FEATURE: wLength is not zero.....\n");
1233 return 1;
1234 }
1235
1236 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1237 case USB_RECIP_DEVICE:
1238 switch (usb_ctrl->wValue) {
1239 case USB_DEVICE_REMOTE_WAKEUP:
1240 debug_cond(DEBUG_SETUP != 0,
1241 "\tSET_FEATURE:USB_DEVICE_REMOTE_WAKEUP\n");
1242 break;
1243 case USB_DEVICE_B_HNP_ENABLE:
1244 debug_cond(DEBUG_SETUP != 0,
1245 "\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
1246 break;
1247
1248 case USB_DEVICE_A_HNP_SUPPORT:
1249 /* RH port supports HNP */
1250 debug_cond(DEBUG_SETUP != 0,
1251 "\tSET_FEATURE:USB_DEVICE_A_HNP_SUPPORT\n");
1252 break;
1253
1254 case USB_DEVICE_A_ALT_HNP_SUPPORT:
1255 /* other RH port does */
1256 debug_cond(DEBUG_SETUP != 0,
1257 "\tSET: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
1258 break;
1259 }
1260
1261 dwc2_udc_ep0_zlp(dev);
1262 return 0;
1263
1264 case USB_RECIP_INTERFACE:
1265 debug_cond(DEBUG_SETUP != 0,
1266 "\tSET_FEATURE: USB_RECIP_INTERFACE\n");
1267 break;
1268
1269 case USB_RECIP_ENDPOINT:
1270 debug_cond(DEBUG_SETUP != 0,
1271 "\tSET_FEATURE: USB_RECIP_ENDPOINT\n");
1272 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1273 if (ep_num == 0) {
1274 dwc2_udc_ep0_set_stall(ep);
1275 return 0;
1276 }
1277 ep->stopped = 1;
1278 dwc2_udc_ep_set_stall(ep);
1279 }
1280
1281 dwc2_udc_ep0_zlp(dev);
1282 return 0;
1283 }
1284
1285 return 1;
1286 }
1287
1288 /*
1289 * WAIT_FOR_SETUP (OUT_PKT_RDY)
1290 */
dwc2_ep0_setup(struct dwc2_udc * dev)1291 static void dwc2_ep0_setup(struct dwc2_udc *dev)
1292 {
1293 struct dwc2_ep *ep = &dev->ep[0];
1294 int i;
1295 u8 ep_num;
1296
1297 /* Nuke all previous transfers */
1298 nuke(ep, -EPROTO);
1299
1300 /* read control req from fifo (8 bytes) */
1301 dwc2_fifo_read(ep, usb_ctrl, 8);
1302
1303 debug_cond(DEBUG_SETUP != 0,
1304 "%s: bRequestType = 0x%x(%s), bRequest = 0x%x"
1305 "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n",
1306 __func__, usb_ctrl->bRequestType,
1307 (usb_ctrl->bRequestType & USB_DIR_IN) ? "IN" : "OUT",
1308 usb_ctrl->bRequest,
1309 usb_ctrl->wLength, usb_ctrl->wValue, usb_ctrl->wIndex);
1310
1311 #ifdef DEBUG
1312 {
1313 int i, len = sizeof(*usb_ctrl);
1314 char *p = (char *)usb_ctrl;
1315
1316 printf("pkt = ");
1317 for (i = 0; i < len; i++) {
1318 printf("%02x", ((u8 *)p)[i]);
1319 if ((i & 7) == 7)
1320 printf(" ");
1321 }
1322 printf("\n");
1323 }
1324 #endif
1325
1326 if (usb_ctrl->bRequest == GET_MAX_LUN_REQUEST &&
1327 usb_ctrl->wLength != 1) {
1328 debug_cond(DEBUG_SETUP != 0,
1329 "\t%s:GET_MAX_LUN_REQUEST:invalid",
1330 __func__);
1331 debug_cond(DEBUG_SETUP != 0,
1332 "wLength = %d, setup returned\n",
1333 usb_ctrl->wLength);
1334
1335 dwc2_udc_ep0_set_stall(ep);
1336 dev->ep0state = WAIT_FOR_SETUP;
1337
1338 return;
1339 } else if (usb_ctrl->bRequest == BOT_RESET_REQUEST &&
1340 usb_ctrl->wLength != 0) {
1341 /* Bulk-Only *mass storge reset of class-specific request */
1342 debug_cond(DEBUG_SETUP != 0,
1343 "%s:BOT Rest:invalid wLength =%d, setup returned\n",
1344 __func__, usb_ctrl->wLength);
1345
1346 dwc2_udc_ep0_set_stall(ep);
1347 dev->ep0state = WAIT_FOR_SETUP;
1348
1349 return;
1350 }
1351
1352 /* Set direction of EP0 */
1353 if (likely(usb_ctrl->bRequestType & USB_DIR_IN)) {
1354 ep->bEndpointAddress |= USB_DIR_IN;
1355 } else {
1356 ep->bEndpointAddress &= ~USB_DIR_IN;
1357 }
1358 /* cope with automagic for some standard requests. */
1359 dev->req_std = (usb_ctrl->bRequestType & USB_TYPE_MASK)
1360 == USB_TYPE_STANDARD;
1361
1362 dev->req_pending = 1;
1363
1364 /* Handle some SETUP packets ourselves */
1365 if (dev->req_std) {
1366 switch (usb_ctrl->bRequest) {
1367 case USB_REQ_SET_ADDRESS:
1368 debug_cond(DEBUG_SETUP != 0,
1369 "%s: *** USB_REQ_SET_ADDRESS (%d)\n",
1370 __func__, usb_ctrl->wValue);
1371 if (usb_ctrl->bRequestType
1372 != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1373 break;
1374 dev->connected = 1;
1375 udc_set_address(dev, usb_ctrl->wValue);
1376 return;
1377
1378 case USB_REQ_SET_CONFIGURATION:
1379 debug_cond(DEBUG_SETUP != 0,
1380 "=====================================\n");
1381 debug_cond(DEBUG_SETUP != 0,
1382 "%s: USB_REQ_SET_CONFIGURATION (%d)\n",
1383 __func__, usb_ctrl->wValue);
1384
1385 if (usb_ctrl->bRequestType == USB_RECIP_DEVICE)
1386 reset_available = 1;
1387
1388 break;
1389
1390 case USB_REQ_GET_DESCRIPTOR:
1391 debug_cond(DEBUG_SETUP != 0,
1392 "%s: *** USB_REQ_GET_DESCRIPTOR\n",
1393 __func__);
1394 break;
1395
1396 case USB_REQ_SET_INTERFACE:
1397 debug_cond(DEBUG_SETUP != 0,
1398 "%s: *** USB_REQ_SET_INTERFACE (%d)\n",
1399 __func__, usb_ctrl->wValue);
1400
1401 if (usb_ctrl->bRequestType == USB_RECIP_INTERFACE)
1402 reset_available = 1;
1403
1404 break;
1405
1406 case USB_REQ_GET_CONFIGURATION:
1407 debug_cond(DEBUG_SETUP != 0,
1408 "%s: *** USB_REQ_GET_CONFIGURATION\n",
1409 __func__);
1410 break;
1411
1412 case USB_REQ_GET_STATUS:
1413 if (!dwc2_udc_get_status(dev, usb_ctrl))
1414 return;
1415
1416 break;
1417
1418 case USB_REQ_CLEAR_FEATURE:
1419 ep_num = usb_ctrl->wIndex & 0x7f;
1420
1421 if (!dwc2_udc_clear_feature(&dev->ep[ep_num].ep))
1422 return;
1423
1424 break;
1425
1426 case USB_REQ_SET_FEATURE:
1427 ep_num = usb_ctrl->wIndex & 0x7f;
1428
1429 if (!dwc2_udc_set_feature(&dev->ep[ep_num].ep))
1430 return;
1431
1432 break;
1433
1434 default:
1435 debug_cond(DEBUG_SETUP != 0,
1436 "%s: *** Default of usb_ctrl->bRequest=0x%x"
1437 "happened.\n", __func__, usb_ctrl->bRequest);
1438 break;
1439 }
1440 }
1441
1442
1443 if (likely(dev->driver)) {
1444 /* device-2-host (IN) or no data setup command,
1445 * process immediately */
1446 debug_cond(DEBUG_SETUP != 0,
1447 "%s:usb_ctrlreq will be passed to fsg_setup()\n",
1448 __func__);
1449
1450 spin_unlock(&dev->lock);
1451 i = dev->driver->setup(&dev->gadget, usb_ctrl);
1452 spin_lock(&dev->lock);
1453
1454 if (i < 0) {
1455 /* setup processing failed, force stall */
1456 dwc2_udc_ep0_set_stall(ep);
1457 dev->ep0state = WAIT_FOR_SETUP;
1458
1459 debug_cond(DEBUG_SETUP != 0,
1460 "\tdev->driver->setup failed (%d),"
1461 " bRequest = %d\n",
1462 i, usb_ctrl->bRequest);
1463
1464
1465 } else if (dev->req_pending) {
1466 dev->req_pending = 0;
1467 debug_cond(DEBUG_SETUP != 0,
1468 "\tdev->req_pending...\n");
1469 }
1470
1471 debug_cond(DEBUG_SETUP != 0,
1472 "\tep0state = %s\n", state_names[dev->ep0state]);
1473
1474 }
1475 }
1476
1477 /*
1478 * handle ep0 interrupt
1479 */
dwc2_handle_ep0(struct dwc2_udc * dev)1480 static void dwc2_handle_ep0(struct dwc2_udc *dev)
1481 {
1482 if (dev->ep0state == WAIT_FOR_SETUP) {
1483 debug_cond(DEBUG_OUT_EP != 0,
1484 "%s: WAIT_FOR_SETUP\n", __func__);
1485 dwc2_ep0_setup(dev);
1486
1487 } else {
1488 debug_cond(DEBUG_OUT_EP != 0,
1489 "%s: strange state!!(state = %s)\n",
1490 __func__, state_names[dev->ep0state]);
1491 }
1492 }
1493
dwc2_ep0_kick(struct dwc2_udc * dev,struct dwc2_ep * ep)1494 static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep)
1495 {
1496 debug_cond(DEBUG_EP0 != 0,
1497 "%s: ep_is_in = %d\n", __func__, ep_is_in(ep));
1498 if (ep_is_in(ep)) {
1499 dev->ep0state = DATA_STATE_XMIT;
1500 dwc2_ep0_write(dev);
1501
1502 } else {
1503 dev->ep0state = DATA_STATE_RECV;
1504 dwc2_ep0_read(dev);
1505 }
1506 }
1507