1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
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28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
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40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 #ifdef MSOS_TYPE_LINUX_KERNEL
79 #include <linux/module.h>
80 #include <linux/kernel.h>
81 #include <linux/time.h>
82 #else
83 #include <stdio.h>
84 #include <stdlib.h>
85 #endif
86 #include "MsCommon.h"
87 #include "gpd_reg.h"
88 #include "drvgpd.h"
89 #include "MsOS.h"
90 #include "osalGPD.h"
91 #include "halCHIP.h"
92
93 MS_VIRT READBITBASE;
94 static MS_U32 g_iwidth;
95 static MS_U32 g_iheight;
96 static MS_U32 g_gpd_cacheable = TRUE;
97 static MS_VIRT gRIU_REG_BASE;
98
99 #define DRVGPD_FLIP_GO
100
101
_GPD_PrintMem(MS_U32 u32Addr,MS_U32 u32Size)102 void _GPD_PrintMem(MS_U32 u32Addr, MS_U32 u32Size)
103 {
104 MS_U32 u32i;
105 console_printf("===========================================================\n");
106 console_printf("print memory addr=0x%tx, size=0x%tx\n", (ptrdiff_t)u32Addr, (ptrdiff_t)u32Size);
107 console_printf("===========================================================\n");
108
109 for(u32i=0; u32i<u32Size/16+((u32Size%16)? 1:0); u32i++)
110 {
111 console_printf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x \n",
112 *((MS_U8*)(MS_VIRT)(u32Addr+u32i*16)), *((MS_U8*)(MS_VIRT)(u32Addr+u32i*16+1)), *((MS_U8*)(MS_VIRT)(u32Addr+u32i*16+2)), *((MS_U8*)(MS_VIRT)(u32Addr+u32i*16+3)),
113 *((MS_U8*)(MS_VIRT)(u32Addr+u32i*16+4)), *((MS_U8*)(MS_VIRT)(u32Addr+u32i*16+5)), *((MS_U8*)(MS_VIRT)(u32Addr+u32i*16+6)), *((MS_U8*)(MS_VIRT)(u32Addr+u32i*16+7)),
114 *((MS_U8*)(MS_VIRT)(u32Addr+u32i*16+8)), *((MS_U8*)(MS_VIRT)(u32Addr+u32i*16+9)), *((MS_U8*)(MS_VIRT)(u32Addr+u32i*16+10)), *((MS_U8*)(MS_VIRT)(u32Addr+u32i*16+11)),
115 *((MS_U8*)(MS_VIRT)(u32Addr+u32i*16+12)), *((MS_U8*)(MS_VIRT)(u32Addr+u32i*16+13)), *((MS_U8*)(MS_VIRT)(u32Addr+u32i*16+14)), *((MS_U8*)(MS_VIRT)(u32Addr+u32i*16+15))
116 );
117 }
118 console_printf("===========================================================\n");
119 }
120
121
drv_gpd_set_scaling(MS_U32 enable,MS_U32 mode)122 void drv_gpd_set_scaling(MS_U32 enable, MS_U32 mode)
123 {
124
125 #if defined(GPD_SCALING_SUPPORT)
126 GPD_SET_MS_U32REG(reg_scale_en, enable);
127 GPD_SET_MS_U32REG(reg_scale_md, mode);
128 #endif
129
130 }
131
drv_gpd_get_scaling_mode(void)132 MS_U32 drv_gpd_get_scaling_mode(void)
133 {
134 #if defined(GPD_SCALING_SUPPORT)
135 return GPD_GET_MS_U32REG(reg_scale_en) | GPD_GET_MS_U32REG(reg_scale_md) << 1;
136 #endif
137 return 0;
138 }
139
140 #if (defined(__arm__))
drv_eng_always_active(MS_U32 value)141 void drv_eng_always_active(MS_U32 value)
142 {
143 GPD_SET_MS_U32REG(reg_eng_always_active, value);
144
145 }
146 #endif
147
148
drv_reg_iofifo_state(void)149 MS_U32 drv_reg_iofifo_state(void)
150 {
151
152 return GPD_GET_MS_U32REG(reg_iofifo_state);
153 }
154
drv_gpd_eco_enable(MS_U32 enable)155 void drv_gpd_eco_enable(MS_U32 enable)
156 {
157
158 GPD_SET_MS_U32REG(reg_spare1, enable);
159
160 }
161
162 static MS_VIRT u32ZbufVA;
163 static MS_VIRT u32CbufVA;
164
165
drv_gpd_set_zbuf_bas(MS_PHY base)166 void drv_gpd_set_zbuf_bas(MS_PHY base)
167 {
168 if (FALSE == g_gpd_cacheable)
169 {
170 u32ZbufVA = MsOS_PA2KSEG1(base<<3);
171 }
172 else
173 {
174 u32ZbufVA = MsOS_PA2KSEG0(base<<3);
175 }
176 GPD_SET_MS_U32REG(reg_zbuf_bas, base & (~DRAMBASE));
177 }
178
drv_gpd_set_cbuf_bas(MS_PHY base)179 void drv_gpd_set_cbuf_bas(MS_PHY base)
180 {
181 if (FALSE == g_gpd_cacheable)
182 {
183 u32CbufVA = MsOS_PA2KSEG1(base<<3);
184 }
185 else
186 {
187 u32CbufVA = MsOS_PA2KSEG0(base<<3);
188 }
189 GPD_SET_MS_U32REG(reg_cbuf_bas, base & (~DRAMBASE));
190
191 }
192
193
set_nop_cmd(MS_U32 num)194 void set_nop_cmd(MS_U32 num)
195 {
196 MS_U32 i;
197 for(i = 0; i < num; i++)
198 drv_gpd_set_iwidth_height(g_iwidth, g_iheight);
199 }
200
drv_gpd_png_state(void)201 MS_U32 drv_gpd_png_state(void)
202 {
203 return GPD_GET_MS_U32REG(reg_png_state);
204 }
205
drv_gpd_bitpos(void)206 MS_U32 drv_gpd_bitpos(void)
207 {
208 return GPD_GET_MS_U32REG(reg_bitpos);
209 }
210
drv_gpd_ififo_radr(void)211 MS_U32 drv_gpd_ififo_radr(void)
212 {
213 return GPD_GET_MS_U32REG(reg_ififo_radr);
214 }
215
drv_gpd_ififo_empty(void)216 MS_U32 drv_gpd_ififo_empty(void)
217 {
218 return GPD_GET_MS_U32REG(reg_ififo_empty);
219 }
220
drv_gpd_ififo_full(void)221 MS_U32 drv_gpd_ififo_full(void)
222 {
223 return GPD_GET_MS_U32REG(reg_ififo_full);
224 }
225
drv_gpd_ofifo_done(void)226 MS_U32 drv_gpd_ofifo_done(void)
227 {
228 //return GPD_GET_MS_U32REG(reg_ofifo_done);
229 return 0;
230 }
231
drv_gpd_bsadr_full(void)232 MS_U32 drv_gpd_bsadr_full(void)
233 {
234 return GPD_GET_MS_U32REG(reg_bsadr_full);
235 }
236
drv_gpd_png_blk_done(void)237 MS_U32 drv_gpd_png_blk_done(void)
238 {
239 return GPD_GET_MS_U32REG(reg_png_blk_done);
240 }
241
drv_gpd_png_eob(void)242 MS_U32 drv_gpd_png_eob(void)
243 {
244 return GPD_GET_MS_U32REG(reg_png_eob);
245 }
246
247 #if 0
248 void png_gif_en(void)
249 {
250 MS_U32 data;
251
252 data=REDREG32(REG_GPD_8014);
253 data|=(1<<7);
254 WRTREG32(REG_GPD_8014,data);
255 }
256
257 MS_U16 read_bits(MS_U32 n)
258 {
259 while((REDREG32(REG_GPD_8014)&IFIFO_EMPTY))
260 {
261 GifQprintf("RIFIFO_EMPTY\n");
262 }
263 return read_bits_reg(n);
264 }
265
266 MS_U16 show_bits(MS_U32 n)
267 {
268 while((REDREG32(REG_GPD_8014)&IFIFO_EMPTY))
269 {
270 GifQprintf("SIFIFO_EMPTY\n");
271 }
272 return show_bits_reg(n);
273 }
274 #else
275
drv_gpd_png_en(void)276 void drv_gpd_png_en(void)
277 {
278 GPD_SET_MS_U32REG(reg_png_en, 1);
279 //drv_eng_always_active(0x0);
280 }
281
drv_gpd_gif_en(void)282 void drv_gpd_gif_en(void)
283 {
284 GPD_SET_MS_U32REG(reg_png_en, 1);
285 #if (defined(__arm__))
286 drv_eng_always_active(0xf);
287 #endif
288 }
289
read_bits(MS_U32 n)290 MS_U16 read_bits(MS_U32 n)
291 {
292 while (GPD_GET_MS_U32REG(reg_ififo_empty))
293 {
294 console_printf("RIFIFO_EMPTY\n");
295 }
296 return read_bits_reg(n);
297 }
298
show_bits(MS_U32 n)299 MS_U16 show_bits(MS_U32 n)
300 {
301 while (GPD_GET_MS_U32REG(reg_ififo_empty))
302 {
303 console_printf("SIFIFO_EMPTY\n");
304 }
305 return show_bits_reg(n);
306 }
307 #endif
308
309 extern MS_U32 num, blk_typ;
drv_gpd_dbg_dump(void)310 void drv_gpd_dbg_dump(void)
311 {
312 MS_U32 data;
313
314 data = drv_gpd_png_state();
315 UNUSED(data);
316 console_printf("PNG state = %tx\n", (ptrdiff_t)data);
317 console_printf("Block stop = %tx\n", (ptrdiff_t)num);
318 console_printf("Block Type = %tx\n",(ptrdiff_t) blk_typ);
319 }
320
321 #if 0
322 void drv_gpd_Init(void)
323 {
324 memset((void*)&GPDreg,0,sizeof(_GPDreg));
325 MDrv_CQ_SWReset();
326
327 set_single_cmd(0x831c,GPD_RST);
328 MDrv_CQ_Fire();
329 }
330
331 void drv_gpd_set_bstart_end(MS_U32 bstart, MS_U32 bend)
332 {
333 /*Set Bstart & Bend*/
334 MS_U32 dwPtr;
335 MDrv_CQ_SWReset();
336 #ifdef DUMPQ
337 GPDreg.h8340 = (((bstart&(~DRAMBASE))&(7))+8); //Boffset
338 set_single_cmd(0x8340,GPDreg.h8340);
339
340 GPDreg.h8334 = ((bstart&(~DRAMBASE))&(~7));
341 GPDreg.h8338 = ((bend&(~DRAMBASE))&(~7));
342 #else
343 GPDreg.h8334 = bstart;
344 GPDreg.h8338 = bend;
345 #endif
346
347 set_single_cmd(0x8334,GPDreg.h8334);
348 set_single_cmd(0x8338,GPDreg.h8338);
349 set_single_cmd(0x8340,0);
350 set_nop_cmd(2);
351 set_single_cmd(0x831c,GPD_BSADDR_GO);
352
353 MDrv_CQ_Fire();
354 }
355
356 void drv_gpd_set_ocolor(MS_U32 ocolor_typ)
357 {
358 MDrv_CQ_SWReset();
359 GPDreg.h8358 &= ~(0x03<<GPD_OCOLOR_SHF);
360 GPDreg.h8358 |= (ocolor_typ<<GPD_OCOLOR_SHF);
361 set_single_cmd(0x8358,GPDreg.h8358);
362 }
363
364 void drv_gpd_write_cmap(MS_U32 num, MS_U32 * ptr)
365 {
366 MS_U32 i,vdata;
367
368 while(num > 0)
369 {
370 vdata = ((DEFAULT_ALPHA<<24)|(((MS_U8 *)(*ptr))[0]<<16)
371 |(((MS_U8 *)(*ptr))[1]<<8)
372 |((MS_U8 *)(*ptr))[2]);
373 set_single_cmd(0x8320,vdata);
374 num--;
375 (*ptr)+=3;
376 }
377 }
378 #else
379
drv_gpd_Init(void)380 void drv_gpd_Init(void)
381 {
382 g_iwidth = 0;
383 g_iheight = 0;
384 hal_gpd_SetMIUProtectMask(gRIU_REG_BASE, TRUE);
385 console_printf("before reset.....bitpos=%td\n", (ptrdiff_t)drv_gpd_bitpos());
386 GPD_SET_MS_U32REG(reg_gpd_rst, 1);
387 GPD_SET_MS_U32REG(reg_gpd_rst, 1);
388 GPD_SET_MS_U32REG(reg_gpd_rst, 1);
389 GPD_SET_MS_U32REG(reg_gpd_rst, 0);
390
391 #if ENABLE_GPD_PATCH
392 GPD_SET_MS_U32REG(reg_gpd_rst, 1);
393 GPD_SET_MS_U32REG(reg_gpd_rst, 1);
394 GPD_SET_MS_U32REG(reg_gpd_rst, 1);
395 GPD_SET_MS_U32REG(reg_gpd_rst, 0);
396
397 GPD_SET_MS_U32REG(reg_gpd_rst, 1);
398 GPD_SET_MS_U32REG(reg_gpd_rst, 1);
399 GPD_SET_MS_U32REG(reg_gpd_rst, 1);
400 GPD_SET_MS_U32REG(reg_gpd_rst, 0);
401 #endif
402
403 console_printf("after reset.....bitpos=%td\n", (ptrdiff_t)drv_gpd_bitpos());
404 hal_gpd_SetMIUProtectMask(gRIU_REG_BASE, FALSE);
405
406
407 #if ENABLE_GPD_PATCH
408 // disable clock gating
409 GPD_SET_MS_U32REG(reg_mreq_always_active, 1);
410 GPD_SET_MS_U32REG(reg_eng_always_active, 0x3f);
411 // disable zcache/ccache
412 GPD_SET_MS_U32REG(reg_cache_hit_cmp, 0x0);
413
414 console_printf("set reg_mreq_always_active = 1\n");
415 console_printf("set reg_eng_always_active = 0x3f\n");
416 console_printf("set reg_cache_hit_cmp = 0\n");
417 #endif
418
419 }
420
drv_gpd_set_bstart_end(MS_PHY bstart,MS_PHY bend)421 void drv_gpd_set_bstart_end(MS_PHY bstart, MS_PHY bend)
422 {
423
424 GPD_SET_MS_U32REG(reg_gpd_bstart, bstart & (~DRAMBASE));
425 GPD_SET_MS_U32REG(reg_gpd_bend, bend & (~DRAMBASE));
426 GPD_SET_MS_U32REG(reg_gpd_boffset, 0);
427
428
429 #ifdef DRVGPD_FLIP_GO
430 {
431 MS_U32 val = GPD_GET_MS_U32REG(reg_gpd_bsaddr_go) ^ 1;
432 GPD_SET_MS_U32REG(reg_gpd_bsaddr_go, val);
433 }
434 #else
435 GPD_SET_MS_U32REG(reg_gpd_bsaddr_go, 1);
436 #endif
437 }
438
drv_gpd_set_ocolor(MS_U32 ocolor_typ)439 void drv_gpd_set_ocolor(MS_U32 ocolor_typ)
440 {
441 GPD_SET_MS_U32REG(reg_gpd_ocolor, ocolor_typ);
442 }
443
444
drv_gpd_write_cmap(MS_U32 num,MS_U8 * ptr,MS_U32 trans_idx)445 void drv_gpd_write_cmap(MS_U32 num, MS_U8 *ptr,MS_U32 trans_idx)
446 {
447 MS_U32 i, vdata;
448 MS_U8 r, g, b, a;
449
450 GPD_SET_MS_U32REG(reg_gif_local_tbl, 0);
451 for (i = 0; i < num; i++)
452 {
453 if (ptr)
454 {
455 r = *ptr++;
456 g = *ptr++;
457 b = *ptr++;
458 }
459 else
460 {
461 r = read_bits(8);
462 g = read_bits(8);
463 b = read_bits(8);
464 }
465
466 if (i == trans_idx)
467 a = 0;
468 else
469 a = 0xFF;
470
471 vdata = (a << 24) | (r << 16) | (g << 8) | b;
472 GPD_SET_MS_U32REG(reg_gpd_cmem_wd, vdata);
473 }
474 }
475
476
477
478 #endif
479
480 #if 0
481 void drv_gpd_set_pitch(MS_U32 pitch)
482 {
483 GPDreg.h832c &=~(0xFFFF<<GPD_PITCH_SHF);
484 GPDreg.h832c |=(pitch<<GPD_PITCH_SHF);
485 set_single_cmd(0x832c,GPDreg.h832c);
486 }
487
488 void drv_gpd_set_gif_swidth_sheight(MS_U32 width ,MS_U32 height)
489 {
490 GPDreg.h8348 &=~(0xFFFF<<GPD_ROI_WIDTH_SHF);
491 GPDreg.h8348 |=(width<<GPD_ROI_WIDTH_SHF);
492 GPDreg.h834c &=~0x0000FFFF;
493 GPDreg.h834c |=height;
494 set_single_cmd(0x8348,GPDreg.h8348);
495 set_single_cmd(0x834c,GPDreg.h834c);
496 }
497
498 void drv_gpd_set_iwidth_height(MS_U32 width, MS_U32 height)
499 {
500 GPDreg.h8330 = ((height<<GPD_IHEIGHT_SHF)|width);
501 set_single_cmd(0x8330,GPDreg.h8330);
502 pwidth=width;
503 pheight=height;
504 }
505
506 void drv_gpd_set_istart(MS_U32 vdata)
507 {
508 GPDreg.h833c = vdata;
509 set_single_cmd(0x833c,GPDreg.h833c);
510 MDrv_CQ_Fire();
511 }
512
513 void drv_gpd_set_ROI(MS_U32 enable,MS_U32 hstart, MS_U32 vstart, MS_U32 width, MS_U32 height)
514 {
515 GPDreg.h8344 = hstart;
516 GPDreg.h8348 = vstart|(width<<16);
517 GPDreg.h834c &= ~(0xFFFF|(1<<16));
518
519 if(enable)
520 GPDreg.h834c |= height|(enable<<16);
521
522 set_single_cmd(0x8344,GPDreg.h8344);
523 set_single_cmd(0x8348,GPDreg.h8348);
524 set_single_cmd(0x834c,GPDreg.h834c);
525 }
526
527 void drv_gpd_set_interlace(MS_U8 state)
528 {
529 MDrv_CQ_SWReset();
530
531 if (state == TRUE)
532 GPDreg.h83b8 |= GPD_INTERLACE;
533 else
534 GPDreg.h83b8 &= ~GPD_INTERLACE;
535 set_single_cmd(0x83b8,GPDreg.h83b8);
536 MDrv_CQ_Fire();
537 }
538
539 void drv_gpd_set_gif_local_map_size(MS_U32 bitperpixel)
540 {
541 MDrv_CQ_SWReset();
542
543 if (!bitperpixel)
544 {
545 GPDreg.h8328 &= ~GIF_LOCAL_TBL;
546 }
547 else
548 {
549 GPDreg.h8328 |= GIF_LOCAL_TBL;
550 GPDreg.h8328 &= ~(0x07<<GIF_LTAB_SIZ_SHF);
551 GPDreg.h8328 |= (bitperpixel<<GIF_LTAB_SIZ_SHF);
552 }
553 set_single_cmd(0x8328,GPDreg.h8328);
554 MDrv_CQ_Fire();
555 }
556 #else
557
drv_gpd_set_pitch(MS_U32 pitch)558 void drv_gpd_set_pitch(MS_U32 pitch)
559 {
560 GPD_SET_MS_U32REG(reg_gpd_pitch, pitch);
561 }
562
drv_gpd_set_gif_swidth_sheight(MS_U32 width,MS_U32 height)563 void drv_gpd_set_gif_swidth_sheight(MS_U32 width ,MS_U32 height)
564 {
565 GPD_SET_MS_U32REG(reg_gpd_roi_width, width);
566 GPD_SET_MS_U32REG(reg_gpd_roi_height, height);
567 }
568
drv_gpd_set_iwidth_height(MS_U32 iwidth,MS_U32 iheight)569 void drv_gpd_set_iwidth_height(MS_U32 iwidth, MS_U32 iheight)
570 {
571 g_iwidth = iwidth;
572 g_iheight = iheight;
573 GPD_SET_MS_U32REG(reg_gpd_iwidth, iwidth);
574 GPD_SET_MS_U32REG(reg_gpd_iheight, iheight);
575 }
576
drv_gpd_set_istart(MS_U32 istart)577 void drv_gpd_set_istart(MS_U32 istart)
578 {
579
580 //GPD_SET_MS_U32REG(reg_gpd_istart, istart & (~DRAMBASE));
581 GPD_SET_MS_U32REG(reg_gpd_istart, istart & (~DRAMBASE));
582
583
584 }
585
drv_gpd_set_ROI(MS_U32 enable,MS_U32 hstart,MS_U32 vstart,MS_U32 width,MS_U32 height)586 void drv_gpd_set_ROI(MS_U32 enable, MS_U32 hstart, MS_U32 vstart, MS_U32 width, MS_U32 height)
587 {
588 GPD_SET_MS_U32REG(reg_gpd_roi_hstart, hstart);
589 GPD_SET_MS_U32REG(reg_gpd_roi_vstart, vstart);
590 GPD_SET_MS_U32REG(reg_gpd_roi_width, width);
591 GPD_SET_MS_U32REG(reg_gpd_roi_height, height);
592
593 if (enable)
594 GPD_SET_MS_U32REG(reg_gpd_roi_en, 1);
595 else
596 GPD_SET_MS_U32REG(reg_gpd_roi_en, 0);
597 }
598
drv_gpd_set_interlace(MS_U8 interlace)599 void drv_gpd_set_interlace(MS_U8 interlace)
600 {
601 if (interlace)
602 GPD_SET_MS_U32REG(reg_gpd_interlace, 1);
603 else
604 GPD_SET_MS_U32REG(reg_gpd_interlace, 0);
605 }
606
drv_gpd_set_gif_local_map_size(MS_U32 bpp)607 void drv_gpd_set_gif_local_map_size(MS_U32 bpp)
608 {
609 if (!bpp)
610 {
611 GPD_SET_MS_U32REG(reg_gif_local_tbl, 0);
612 }
613 else
614 {
615 GPD_SET_MS_U32REG(reg_gif_ltbl_size, bpp);
616 GPD_SET_MS_U32REG(reg_gif_local_tbl, 1);
617 }
618 }
619 #endif
620
621 #if 0
622 void drv_gpd_set_gif_go(void)
623 {
624 MDrv_CQ_SWReset();
625 set_single_cmd(0x831c,GIF_GO);
626 MDrv_CQ_Fire();
627 }
628
629 MS_U32 drv_gpd_gif_done(void)
630 {
631 return (REDREG32(REG_GPD_8014)&GIF_DONE);
632 }
633
634 void drv_gpd_set_trans_rg(MS_U16 r,MS_U16 g)
635 {
636 GPDreg.h8350=(r+(g<<PNG_TRANS_G_SHF));
637 set_single_cmd(0x8350,GPDreg.h8350);
638 }
639
640 void drv_gpd_set_palette(MS_U8 *palette,MS_U16 palette_num,MS_U8 *trans,MS_U16 num_trans)
641 {
642 MS_U32 i;
643 MS_U8 palette_alpha;
644 MS_U8 R,G,B;
645 MS_U32 palette_data;
646
647 for(i=0;i<palette_num;i++)
648 {
649 if(i<num_trans)
650 palette_alpha=*(trans+i);
651 else
652 palette_alpha=DEFAULT_ALPHA;
653
654 R=*(palette+i*3);
655 G=*(palette+i*3+1);
656 B=*(palette+i*3+2);
657 GPDreg.h8320=palette_data=(R<<24)+(G<<16)+(B<<8)+palette_alpha;
658
659 set_single_cmd(0x8320,GPDreg.h8320);
660 }
661
662 for(i=palette_num;i<256;i++)
663 set_single_cmd(0x8320,0);
664 }
665
666 void drv_gpd_set_pgend(MS_U8 pgend)
667 {
668 GPDreg.h83c0 &=~(0x3<<GPD_PGEND_SHF);
669 GPDreg.h83c0 |=(pgend<<GPD_PGEND_SHF);
670
671 set_single_cmd(0x83c0,GPDreg.h83c0);
672 }
673 #else
674
drv_gpd_set_gif_go(void)675 void drv_gpd_set_gif_go(void)
676 {
677 #ifdef DRVGPD_FLIP_GO
678 {
679 MS_U32 val = GPD_GET_MS_U32REG(reg_gif_go) ^ 1;
680 GPD_SET_MS_U32REG(reg_gif_go, val);
681 }
682 #else
683 GPD_SET_MS_U32REG(reg_gif_go, 1);
684 #endif
685 }
686
drv_gpd_gif_done(void)687 MS_U32 drv_gpd_gif_done(void)
688 {
689 return GPD_GET_MS_U32REG(reg_gif_done);
690 }
691
drv_gpd_set_trans(MS_U16 r,MS_U16 g,MS_U16 b,MS_U8 enable)692 void drv_gpd_set_trans(MS_U16 r, MS_U16 g, MS_U16 b, MS_U8 enable)
693 {
694 GPD_SET_MS_U32REG(reg_png_trans_r, r);
695 GPD_SET_MS_U32REG(reg_png_trans_g, g);
696 GPD_SET_MS_U32REG(reg_png_trans_b, b);
697 GPD_SET_MS_U32REG(reg_png_trans_en, enable);
698 }
699
drv_gpd_set_palette(MS_U8 * palette,MS_U16 palette_num,MS_U8 * trans,MS_U16 num_trans)700 void drv_gpd_set_palette(MS_U8 *palette, MS_U16 palette_num, MS_U8 *trans, MS_U16 num_trans)
701 {
702 MS_U32 i;
703 MS_U8 palette_alpha;
704 MS_U8 R,G,B;
705 MS_U32 palette_data;
706 //MS_U32 tmp;
707
708 for (i = 0; i < palette_num; i++)
709 {
710 if (i < num_trans)
711 palette_alpha = *(trans + i);
712 else
713 palette_alpha = DEFAULT_ALPHA;
714
715 R = *(palette + i * 3);
716 G = *(palette + i * 3 + 1);
717 B = *(palette + i * 3 + 2);
718 palette_data = (R << 24) + (G << 16) + (B << 8) + palette_alpha;
719
720 GPD_SET_MS_U32REG(reg_gpd_cmem_wd, palette_data);
721
722
723 }
724
725 for (i = palette_num; i < 256; i++)
726 GPD_SET_MS_U32REG(reg_gpd_cmem_wd, 0);
727 }
728
drv_gpd_set_pgend(MS_U8 pgend)729 void drv_gpd_set_pgend(MS_U8 pgend)
730 {
731 GPD_SET_MS_U32REG(reg_gpd_pgend, pgend);
732 }
733
drv_gpd_set_hipri(MS_U16 hipri)734 void drv_gpd_set_hipri(MS_U16 hipri)
735 {
736 GPD_SET_MS_U32REG(reg_hipri, hipri);
737 }
738
739 #endif
740
741 #if 0
742 void drv_gpd_set_frun_cnt(MS_U32 frun_cnt)
743 {
744 GPDreg.h83c4=frun_cnt;
745 set_single_cmd(0x83c4,GPDreg.h83c4);
746 }
747
748 void drv_gpd_set_iccp_dtsize(MS_U8 iccp,MS_U8 dtsize)
749 {
750 GPDreg.h8328 |=(iccp);
751
752 GPDreg.h8328 &=~((0x3f<<PNG_DTBL_SIZ_SHF));
753 GPDreg.h8328 |=(dtsize<<PNG_DTBL_SIZ_SHF);
754
755 set_single_cmd(0x8328,GPDreg.h8328);
756 }
757
758 void drv_gpd_set_type(MS_U32 data)
759 {
760 GPDreg.h83b8=data;
761
762 set_single_cmd(0x83b8,GPDreg.h83b8);
763 }
764
765 void drv_gpd_set_default_alpha(MS_U32 vdata)
766 {
767 GPDreg.h834c &= ~(0xFF<<GPD_DFALT_ALPHA_SHF);
768 GPDreg.h834c |= (vdata<<GPD_DFALT_ALPHA_SHF);
769
770 set_single_cmd(0x834c,GPDreg.h834c);
771 }
772
773 void drv_gpd_set_sca_dfa(MS_U8 sca,MS_U8 dfa)
774 {
775 GPDreg.h834c &= ~(0x1f<<PNG_SCA_SHF);
776 GPDreg.h834c |= (sca<<PNG_SCA_SHF);
777
778 GPDreg.h834c &= ~(0xff<<GPD_DFALT_ALPHA_SHF);
779 GPDreg.h834c |= (dfa<<GPD_DFALT_ALPHA_SHF);
780
781 set_single_cmd(0x834c,GPDreg.h834c);
782 }
783
784 void drv_gpd_set_ltsize(MS_U16 ltsize)
785 {
786 GPDreg.h8358 &= ~(0x1ff<<PNG_LTBL_SIZ_SHF);
787 GPDreg.h8358 |= (ltsize<<PNG_LTBL_SIZ_SHF);
788
789 set_single_cmd(0x8358,GPDreg.h8358);
790 }
791 #else
792
drv_gpd_set_frun_cnt(MS_U32 frun_cnt)793 void drv_gpd_set_frun_cnt(MS_U32 frun_cnt)
794 {
795 GPD_SET_MS_U32REG(reg_frun_cnt, frun_cnt);
796 }
797
drv_gpd_set_iccp_dtsize(MS_U8 iccp,MS_U8 dtsize)798 void drv_gpd_set_iccp_dtsize(MS_U8 iccp, MS_U8 dtsize)
799 {
800 GPD_SET_MS_U32REG(reg_gpd_only_decom_en, iccp);
801 GPD_SET_MS_U32REG(reg_png_dtbl_size, dtsize);
802 }
803
drv_gpd_set_type(MS_U8 color_type,MS_U8 interlace,MS_U8 color_depth)804 void drv_gpd_set_type(MS_U8 color_type, MS_U8 interlace, MS_U8 color_depth)
805 {
806 GPD_SET_MS_U32REG(reg_png_color_type, color_type);
807 GPD_SET_MS_U32REG(reg_gpd_interlace, interlace);
808 GPD_SET_MS_U32REG(reg_png_color_depth, color_depth);
809 }
810
drv_gpd_set_default_alpha(MS_U8 alpha)811 void drv_gpd_set_default_alpha(MS_U8 alpha)
812 {
813 GPD_SET_MS_U32REG(reg_gpd_default_alpha, alpha);
814 }
815
drv_gpd_set_sca_dfa(MS_U8 sca,MS_U8 alpha)816 void drv_gpd_set_sca_dfa(MS_U8 sca, MS_U8 alpha)
817 {
818 GPD_SET_MS_U32REG(reg_png_sca, sca);
819 GPD_SET_MS_U32REG(reg_gpd_default_alpha, alpha);
820 }
821
drv_gpd_set_ltsize(MS_U16 ltsize)822 void drv_gpd_set_ltsize(MS_U16 ltsize)
823 {
824 GPD_SET_MS_U32REG(reg_png_ltbl_size, ltsize);
825 }
826 #endif
827
828 #if 0
829 void drv_gpd_set_sc01_width(MS_U32 data)
830 {
831 GPDreg.h8398=data;
832
833 set_single_cmd(0x8398,GPDreg.h8398);
834 }
835
836 void drv_gpd_set_sc23_width(MS_U32 data)
837 {
838 GPDreg.h839c=data;
839
840 set_single_cmd(0x839c,GPDreg.h839c);
841 }
842
843 void drv_gpd_set_sc45_width(MS_U32 data)
844 {
845 GPDreg.h83a0=data;
846
847 set_single_cmd(0x83a0,GPDreg.h83a0);
848 }
849
850 void drv_gpd_set_sc60_wh(MS_U32 data)
851 {
852 GPDreg.h83a4=data;
853
854 set_single_cmd(0x83a4,GPDreg.h83a4);
855 }
856
857 void drv_gpd_set_sc12_height(MS_U32 data)
858 {
859 GPDreg.h83a8=data;
860
861 set_single_cmd(0x83a8,GPDreg.h83a8);
862 }
863
864 void drv_gpd_set_sc34_height(MS_U32 data)
865 {
866 GPDreg.h83ac=data;
867
868 set_single_cmd(0x83ac,GPDreg.h83ac);
869 }
870
871 void drv_gpd_set_sc56_height(MS_U32 data)
872 {
873 GPDreg.h83b0=data;
874
875 set_single_cmd(0x83b0,GPDreg.h83b0);
876 }
877 #else
878
drv_gpd_set_scline_width_progressive(MS_U32 width,MS_U8 bpp)879 void drv_gpd_set_scline_width_progressive(MS_U32 width, MS_U8 bpp)
880 {
881 GPD_SET_MS_U32REG(reg_png_scline0_width, ((width * bpp + 7) >> 3) - 1);
882 }
883
drv_gpd_set_scline_height_progressive(MS_U32 height)884 void drv_gpd_set_scline_height_progressive(MS_U32 height)
885 {
886 GPD_SET_MS_U32REG(reg_png_scline0_height, height - 1);
887 }
888
drv_gpd_set_scline_width_interlace(MS_U32 width,MS_U8 bpp)889 void drv_gpd_set_scline_width_interlace(MS_U32 width, MS_U8 bpp)
890 {
891 GPD_SET_MS_U32REG(reg_png_scline0_width, ((((width + 7) >> 3) * bpp + 7) >> 3) - 1);
892 GPD_SET_MS_U32REG(reg_png_scline1_width, ((((width - 4 + 7) >> 3) * bpp + 7) >> 3) - 1);
893 GPD_SET_MS_U32REG(reg_png_scline2_width, ((((width + 3) >> 2) * bpp + 7) >> 3) - 1);
894 GPD_SET_MS_U32REG(reg_png_scline3_width, ((((width - 2 + 3) >> 2) * bpp + 7) >> 3) - 1);
895 GPD_SET_MS_U32REG(reg_png_scline4_width, ((((width + 1) >> 1) * bpp + 7) >> 3) - 1);
896 GPD_SET_MS_U32REG(reg_png_scline5_width, ((((width - 1 + 1) >> 1) * bpp + 7) >> 3) - 1);
897 GPD_SET_MS_U32REG(reg_png_scline6_width, ((( width ) * bpp + 7) >> 3) - 1);
898 }
899
drv_gpd_set_scline_height_interlace(MS_U32 height)900 void drv_gpd_set_scline_height_interlace(MS_U32 height)
901 {
902 GPD_SET_MS_U32REG(reg_png_scline0_height, ((height + 7) >> 3) - 1);
903 GPD_SET_MS_U32REG(reg_png_scline1_height, ((height + 7) >> 3) - 1);
904 GPD_SET_MS_U32REG(reg_png_scline2_height, ((height - 4 + 7) >> 3) - 1);
905 GPD_SET_MS_U32REG(reg_png_scline3_height, ((height + 3) >> 2) - 1);
906 GPD_SET_MS_U32REG(reg_png_scline4_height, ((height - 2 + 3) >> 2) - 1);
907 GPD_SET_MS_U32REG(reg_png_scline5_height, ((height + 1) >> 1) - 1);
908 GPD_SET_MS_U32REG(reg_png_scline6_height, ((height - 1 + 1) >> 1) - 1);
909 }
910 #endif
911
912 #if 0
913 void drv_gpd_set_png_go(void)
914 {
915 MDrv_CQ_SWReset();
916 set_nop_cmd(2);
917 set_single_cmd(0x831c,PNG_GO);
918 MDrv_CQ_Fire();
919 }
920
921 MS_U32 val = 1;
922
923 void drv_gpd_set_blk_go(void)
924 {
925 MS_U32 dbg=0xff;
926
927 MDrv_CQ_SWReset();
928
929 set_nop_cmd(5);
930 set_single_cmd(0x831c,PNG_BLK_GO);
931
932 if(val)
933 GPDreg.h8328 |=(GIF_LOCAL_TBL);
934 else
935 GPDreg.h8328 &=~(GIF_LOCAL_TBL);
936
937 set_single_cmd(0x8328,GPDreg.h8328);
938
939 MDrv_CQ_Fire();
940
941 while(dbg!=val)
942 dbg=((gpd_read_debug_port(0)&_BIT28)>>28);
943
944 val=!val;
945 }
946
947 void drv_gpd_set_png_done(void)
948 {
949 MDrv_CQ_SWReset();
950
951 GPDreg.h83b8 |= (PNG_DONE);
952
953 set_single_cmd(0x83b8,GPDreg.h83b8);
954 MDrv_CQ_Fire();
955 }
956
957 void drv_gpd_set_cmp_type(MS_U8 cmp)
958 {
959 MDrv_CQ_SWReset();
960
961 GPDreg.h83b8 &=~(0x3<<PNG_COMPRESS_TYPE_SHF);
962 GPDreg.h83b8 |= (cmp<<PNG_COMPRESS_TYPE_SHF);
963
964 set_single_cmd(0x83b8,GPDreg.h83b8);
965 MDrv_CQ_Fire();
966 }
967 #else
968
drv_gpd_set_png_go(void)969 void drv_gpd_set_png_go(void)
970 {
971 #ifdef DRVGPD_FLIP_GO
972 {
973 MS_U32 val = GPD_GET_MS_U32REG(reg_png_go) ^ 1;
974 GPD_SET_MS_U32REG(reg_png_go, val);
975 }
976 #else
977 GPD_SET_MS_U32REG(reg_png_go, 1);
978 #endif
979 }
980
drv_gpd_set_blk_go(void)981 void drv_gpd_set_blk_go(void)
982 {
983 #ifdef DRVGPD_FLIP_GO
984 {
985
986 MS_U32 val = GPD_GET_MS_U32REG(reg_png_blk_go) ^ 1;
987 GPD_SET_MS_U32REG(reg_png_blk_go, val);
988 }
989 #else
990 GPD_SET_MS_U32REG(reg_png_blk_go, 1);
991 #endif
992 /*
993 {
994 static MS_U32 val = 1;
995 MS_U32 dbg = 0xff;
996
997 if(val)
998 GPDreg.h8328 |=(GIF_LOCAL_TBL);
999 else
1000 GPDreg.h8328 &=~(GIF_LOCAL_TBL);
1001
1002 set_single_cmd(0x8328,GPDreg.h8328);
1003
1004 MDrv_CQ_Fire();
1005
1006 while(dbg!=val)
1007 dbg=((gpd_read_debug_port(0)&_BIT28)>>28);
1008
1009 val=!val;
1010 }
1011 */
1012 }
1013
drv_gpd_set_png_done(MS_U32 value)1014 void drv_gpd_set_png_done(MS_U32 value)
1015 {
1016 GPD_SET_MS_U32REG(reg_png_done, value);
1017 }
1018
drv_gpd_set_cmp_type(MS_U8 type)1019 void drv_gpd_set_cmp_type(MS_U8 type)
1020 {
1021 GPD_SET_MS_U32REG(reg_png_compress_type, type);
1022 }
1023 #endif
1024
1025 #if 0
1026 void drv_gpd_set_lbase_g1(MS_U32 data) //lbase 2~4
1027 {
1028 MDrv_CQ_SWReset();
1029
1030 GPDreg.h837c=data;
1031
1032 set_single_cmd(0x837c,GPDreg.h837c);
1033 }
1034
1035 void drv_gpd_set_lbase_g2(MS_U32 data) //5~7
1036 {
1037 GPDreg.h8380=data;
1038
1039 set_single_cmd(0x8380,GPDreg.h8380);
1040 }
1041
1042 void drv_gpd_set_lbase_g3(MS_U32 data) //8~10
1043 {
1044 GPDreg.h8384=data;
1045
1046 set_single_cmd(0x8384,GPDreg.h8384);
1047 }
1048
1049 void drv_gpd_set_lbase_g4(MS_U32 data) //11~13
1050 {
1051 GPDreg.h8388=data;
1052
1053 set_single_cmd(0x8388,GPDreg.h8388);
1054 }
1055
1056 void drv_gpd_set_lbase_g5(MS_U32 data) //lbase 14~15
1057 {
1058 GPDreg.h838c=data;
1059
1060 set_single_cmd(0x838c,GPDreg.h838c);
1061 }
1062
1063 void drv_gpd_set_dbase_g1(MS_U32 data) //dbase 2~3
1064 {
1065 GPDreg.h838c &= ~(0x3ff<<PNG_DBASE2_SHF);
1066 GPDreg.h838c |= (data);
1067
1068 set_single_cmd(0x838c,GPDreg.h838c);
1069 }
1070
1071 void drv_gpd_set_dbase_g2(MS_U32 data) //dbase 4~9
1072 {
1073 GPDreg.h8390=data;
1074
1075 set_single_cmd(0x8390,GPDreg.h8390);
1076 }
1077
1078 void drv_gpd_set_dbase_g3(MS_U32 data) //dbase 10~15
1079 {
1080 GPDreg.h8394=data;
1081
1082 set_single_cmd(0x8394,GPDreg.h8394);
1083 }
1084
1085 void drv_gpd_set_lmincode_valid(MS_U16 lvalid)
1086 {
1087 GPDreg.h83b4=lvalid;
1088
1089 set_single_cmd(0x83b4,GPDreg.h83b4);
1090 }
1091
1092 void drv_gpd_set_dmincode_valid(MS_U16 dvalid)
1093 {
1094 GPDreg.h83b4 &=~(0x7fff<<PNG2_MICODE_VALID_SHF);
1095 GPDreg.h83b4 |=((dvalid&0x7fff)<<PNG2_MICODE_VALID_SHF);
1096
1097 set_single_cmd(0x83b4,GPDreg.h83b4);
1098 }
1099
1100 void drv_gpd_set_lmincode_g1(MS_U32 data) //1~7
1101 {
1102 GPDreg.h8354=data;
1103
1104 set_single_cmd(0x8354,GPDreg.h8354);
1105 }
1106
1107 void drv_gpd_set_lmincode_g2(MS_U32 data) //8~10
1108 {
1109 GPDreg.h835c=data;
1110
1111 set_single_cmd(0x835c,GPDreg.h835c);
1112 }
1113
1114 void drv_gpd_set_lmincode_g3(MS_U32 data) //11~12
1115 {
1116 GPDreg.h8360=data;
1117
1118 set_single_cmd(0x8360,GPDreg.h8360);
1119 }
1120
1121 void drv_gpd_set_lmincode_g4(MS_U32 data) //13~14
1122 {
1123 GPDreg.h8364=data;
1124
1125 set_single_cmd(0x8364,GPDreg.h8364);
1126 }
1127
1128 void drv_gpd_set_lmincode_g5(MS_U32 data) //lmin 15
1129 {
1130 GPDreg.h8368=data;
1131
1132 set_single_cmd(0x8368,GPDreg.h8368);
1133 }
1134
1135 void drv_gpd_set_dmincode_g1(MS_U32 data) //1~5
1136 {
1137 GPDreg.h8368 &=~(0x7fff<<PNG2_MINCODE1_SHF);
1138 GPDreg.h8368|=(data);
1139
1140 set_single_cmd(0x8368,GPDreg.h8368);
1141 }
1142
1143 void drv_gpd_set_dmincode_g2(MS_U32 data) //6~9
1144 {
1145 GPDreg.h836c=data;
1146
1147 set_single_cmd(0x836c,GPDreg.h836c);
1148 }
1149
1150 void drv_gpd_set_dmincode_g3(MS_U32 data) //10~11
1151 {
1152 GPDreg.h8370=data;
1153
1154 set_single_cmd(0x8370,GPDreg.h8370);
1155 }
1156
1157 void drv_gpd_set_dmincode_g4(MS_U32 data) //12~13
1158 {
1159 GPDreg.h8374=data;
1160
1161 set_single_cmd(0x8374,GPDreg.h8374);
1162 }
1163
1164 void drv_gpd_set_dmincode_g5(MS_U32 data) //14~15
1165 {
1166 GPDreg.h8378=data;
1167
1168 set_single_cmd(0x8378,GPDreg.h8378);
1169 MDrv_CQ_Fire();
1170 }
1171 #else
1172
drv_gpd_set_lbase(MS_U16 * lbase)1173 void drv_gpd_set_lbase(MS_U16 *lbase)
1174 {
1175 GPD_SET_MS_U32REG(reg_png_lbase2, lbase[2]);
1176 GPD_SET_MS_U32REG(reg_png_lbase3, lbase[3]);
1177 GPD_SET_MS_U32REG(reg_png_lbase4, lbase[4]);
1178 GPD_SET_MS_U32REG(reg_png_lbase5, lbase[5]);
1179 GPD_SET_MS_U32REG(reg_png_lbase6, lbase[6]);
1180 GPD_SET_MS_U32REG(reg_png_lbase7, lbase[7]);
1181 GPD_SET_MS_U32REG(reg_png_lbase8, lbase[8]);
1182 GPD_SET_MS_U32REG(reg_png_lbase9, lbase[9]);
1183 GPD_SET_MS_U32REG(reg_png_lbase10, lbase[10]);
1184 GPD_SET_MS_U32REG(reg_png_lbase11, lbase[11]);
1185 GPD_SET_MS_U32REG(reg_png_lbase12, lbase[12]);
1186 GPD_SET_MS_U32REG(reg_png_lbase13, lbase[13]);
1187 GPD_SET_MS_U32REG(reg_png_lbase14, lbase[14]);
1188 GPD_SET_MS_U32REG(reg_png_lbase15, lbase[15]);
1189 }
1190
drv_gpd_set_dbase(MS_U16 * dbase)1191 void drv_gpd_set_dbase(MS_U16 *dbase)
1192 {
1193 GPD_SET_MS_U32REG(reg_png_dbase2, dbase[2]);
1194 GPD_SET_MS_U32REG(reg_png_dbase3, dbase[3]);
1195 GPD_SET_MS_U32REG(reg_png_dbase4, dbase[4]);
1196 GPD_SET_MS_U32REG(reg_png_dbase5, dbase[5]);
1197 GPD_SET_MS_U32REG(reg_png_dbase6, dbase[6]);
1198 GPD_SET_MS_U32REG(reg_png_dbase7, dbase[7]);
1199 GPD_SET_MS_U32REG(reg_png_dbase8, dbase[8]);
1200 GPD_SET_MS_U32REG(reg_png_dbase9, dbase[9]);
1201 GPD_SET_MS_U32REG(reg_png_dbase10, dbase[10]);
1202 GPD_SET_MS_U32REG(reg_png_dbase11, dbase[11]);
1203 GPD_SET_MS_U32REG(reg_png_dbase12, dbase[12]);
1204 GPD_SET_MS_U32REG(reg_png_dbase13, dbase[13]);
1205 GPD_SET_MS_U32REG(reg_png_dbase14, dbase[14]);
1206 GPD_SET_MS_U32REG(reg_png_dbase15, dbase[15]);
1207 }
1208
drv_gpd_set_lmincode_valid(MS_U16 lmin_valid)1209 void drv_gpd_set_lmincode_valid(MS_U16 lmin_valid)
1210 {
1211 GPD_SET_MS_U32REG(reg_png_mincode_valid, lmin_valid);
1212 }
1213
drv_gpd_set_dmincode_valid(MS_U16 dmin_valid)1214 void drv_gpd_set_dmincode_valid(MS_U16 dmin_valid)
1215 {
1216 GPD_SET_MS_U32REG(reg_png2_mincode_valid, dmin_valid);
1217 }
1218
drv_gpd_set_lmincode(MS_U16 * lmin)1219 void drv_gpd_set_lmincode(MS_U16 *lmin)
1220 {
1221 GPD_SET_MS_U32REG(reg_png_mincode1, lmin[1]);
1222 GPD_SET_MS_U32REG(reg_png_mincode2, lmin[2]);
1223 GPD_SET_MS_U32REG(reg_png_mincode3, lmin[3]);
1224 GPD_SET_MS_U32REG(reg_png_mincode4, lmin[4]);
1225 GPD_SET_MS_U32REG(reg_png_mincode5, lmin[5]);
1226 GPD_SET_MS_U32REG(reg_png_mincode6, lmin[6]);
1227 GPD_SET_MS_U32REG(reg_png_mincode7, lmin[7]);
1228 GPD_SET_MS_U32REG(reg_png_mincode8, lmin[8]);
1229 GPD_SET_MS_U32REG(reg_png_mincode9, lmin[9]);
1230 GPD_SET_MS_U32REG(reg_png_mincode10, lmin[10]);
1231 GPD_SET_MS_U32REG(reg_png_mincode11, lmin[11]);
1232 GPD_SET_MS_U32REG(reg_png_mincode12, lmin[12]);
1233 GPD_SET_MS_U32REG(reg_png_mincode13, lmin[13]);
1234 GPD_SET_MS_U32REG(reg_png_mincode14, lmin[14]);
1235 GPD_SET_MS_U32REG(reg_png_mincode15, lmin[15]);
1236 }
1237
drv_gpd_set_dmincode(MS_U16 * dmin)1238 void drv_gpd_set_dmincode(MS_U16 *dmin)
1239 {
1240 GPD_SET_MS_U32REG(reg_png2_mincode1, dmin[1]);
1241 GPD_SET_MS_U32REG(reg_png2_mincode2, dmin[2]);
1242 GPD_SET_MS_U32REG(reg_png2_mincode3, dmin[3]);
1243 GPD_SET_MS_U32REG(reg_png2_mincode4, dmin[4]);
1244 GPD_SET_MS_U32REG(reg_png2_mincode5, dmin[5]);
1245 GPD_SET_MS_U32REG(reg_png2_mincode6, dmin[6]);
1246 GPD_SET_MS_U32REG(reg_png2_mincode7, dmin[7]);
1247 GPD_SET_MS_U32REG(reg_png2_mincode8, dmin[8]);
1248 GPD_SET_MS_U32REG(reg_png2_mincode9, dmin[9]);
1249 GPD_SET_MS_U32REG(reg_png2_mincode10, dmin[10]);
1250 GPD_SET_MS_U32REG(reg_png2_mincode11, dmin[11]);
1251 GPD_SET_MS_U32REG(reg_png2_mincode12, dmin[12]);
1252 GPD_SET_MS_U32REG(reg_png2_mincode13, dmin[13]);
1253 GPD_SET_MS_U32REG(reg_png2_mincode14, dmin[14]);
1254 GPD_SET_MS_U32REG(reg_png2_mincode15, dmin[15]);
1255 }
1256 #endif
1257
1258 #if 0
1259 void drv_gpd_set_fixed_ldata(void)
1260 {
1261 MS_U32 i;
1262
1263 for (i=256;i<280;i+=2)
1264 {
1265 GPDreg.h8324=i+((i+1)<<9);
1266 set_single_cmd(0x8324,GPDreg.h8324);
1267 }
1268
1269 for (i=0;i<144;i+=2)
1270 {
1271 GPDreg.h8324=i+((i+1)<<9);
1272 set_single_cmd(0x8324,GPDreg.h8324);
1273 }
1274
1275 for (i=280;i<288;i+=2)
1276 {
1277 GPDreg.h8324=i+((i+1)<<9);
1278 set_single_cmd(0x8324,GPDreg.h8324);
1279 }
1280
1281 for (i=144;i<256;i+=2)
1282 {
1283 GPDreg.h8324=i+((i+1)<<9);
1284 set_single_cmd(0x8324,GPDreg.h8324);
1285 }
1286 }
1287
1288 void drv_gpd_set_dynamic_ldata(MS_U16 num,MS_U16 *ldata)
1289 {
1290 MS_U32 i;
1291
1292 for(i=0;i<num;i+=2)
1293 {
1294 GPDreg.h8324=ldata[i]+(ldata[i+1]<<9);
1295 set_single_cmd(0x8324,GPDreg.h8324);
1296 }
1297 }
1298
1299 void drv_gpd_set_dynamic_ddata(MS_U16 num,MS_U16 *ddata)
1300 {
1301 MS_U32 i;
1302
1303 for (i = 0; i < num; i += 2)
1304 {
1305 GPDreg.h8318 = ddata[i] + (ddata[i+1] << 5);
1306 set_single_cmd(0x8318, GPDreg.h8318);
1307 }
1308 }
1309 #else
1310
drv_gpd_set_fixed_ldata(void)1311 void drv_gpd_set_fixed_ldata(void)
1312 {
1313 MS_U32 i;
1314
1315 for (i = 256; i < 280; i += 2)
1316 GPD_SET_MS_U32REG(reg_png_ltbl_wd, i+((i+1)<<9));
1317
1318 for (i = 0; i < 144; i += 2)
1319 GPD_SET_MS_U32REG(reg_png_ltbl_wd, i+((i+1)<<9));
1320
1321 for (i = 280; i < 288; i += 2)
1322 GPD_SET_MS_U32REG(reg_png_ltbl_wd, i+((i+1)<<9));
1323
1324 for (i = 144; i < 256; i += 2)
1325 GPD_SET_MS_U32REG(reg_png_ltbl_wd, i+((i+1)<<9));
1326 }
1327
drv_gpd_set_dynamic_ldata(MS_U16 num,MS_U16 * ldata)1328 void drv_gpd_set_dynamic_ldata(MS_U16 num, MS_U16 *ldata)
1329 {
1330 MS_U16 i;
1331
1332 for(i = 0; i < num; i += 2)
1333 GPD_SET_MS_U32REG(reg_png_ltbl_wd, ldata[i] + (ldata[i+1] << 9));
1334 }
1335
drv_gpd_set_dynamic_ddata(MS_U16 num,MS_U16 * ddata)1336 void drv_gpd_set_dynamic_ddata(MS_U16 num, MS_U16 *ddata)
1337 {
1338 MS_U16 i;
1339
1340 for(i = 0; i < num; i += 2)
1341 GPD_SET_MS_U32REG(reg_png_dtbl_wd, ddata[i] + (ddata[i+1] << 5));
1342 }
1343 #endif
1344
1345 #if 0
1346 MS_U32 drv_gpd_check_engine(void)
1347 {
1348 if(REDREG32(REG_GPD_8014)&GPD_TIME_OUT )
1349 return -1;
1350
1351 if((!(REDREG32(REG_GPD_8014)&GPD_BLK_DONE)) && (REDREG32(REG_GPD_801c)&OFIFO_DONE))
1352 return -2;
1353
1354 return 0;
1355 }
1356 #else
1357
drv_gpd_check_engine(void)1358 MS_U32 drv_gpd_check_engine(void)
1359 {
1360 if (GPD_GET_MS_U32REG(reg_gpd_time_out))
1361 {
1362 console_printf("[Error] reg_gpd_time_out\n");
1363 return -1;
1364 }
1365
1366 if(!GPD_GET_MS_U32REG(reg_png_blk_done) && drv_gpd_ofifo_done())
1367 {
1368 console_printf("[Error] reg_png_blk_done != 1\n");
1369 return -2;
1370 }
1371
1372 return 0;
1373 }
1374 #endif
1375
1376
drv_gpd_set_access_region(MS_U32 start,MS_U32 end)1377 void drv_gpd_set_access_region(MS_U32 start, MS_U32 end)
1378 {
1379
1380 #ifdef GPD_PROTECT_ADDR_PATCH
1381 console_printf("MIU protect: [%lx, %lx]\n", start, end);
1382 GPD_SET_MS_U32REG(reg_lb_addr, start);
1383 GPD_SET_MS_U32REG(reg_ub_addr, end);
1384 #elif ENABLE_GPD_PATCH
1385 console_printf("MIU protect: [%lx, %lx]\n", start, end);
1386 GPD_SET_MS_U32REG(reg_lb_addr, start);
1387 GPD_SET_MS_U32REG(reg_ub_addr, end);
1388 #endif
1389
1390 }
1391
drv_gpd_get_clkbase()1392 MS_U32 drv_gpd_get_clkbase()
1393 {
1394 return hal_gpd_get_clkbase();
1395
1396 }
1397
drv_gpd_get_clkoffset()1398 MS_U32 drv_gpd_get_clkoffset()
1399 {
1400 return hal_gpd_get_clkoffset();
1401
1402 }
1403
drv_gpd_init_outside_reg(MS_VIRT BankBaseAddr)1404 void drv_gpd_init_outside_reg(MS_VIRT BankBaseAddr)
1405 {
1406 gRIU_REG_BASE = BankBaseAddr;
1407 hal_gpd_init_outside_reg(BankBaseAddr);
1408 }
1409
drv_gpd_power_on(void)1410 void drv_gpd_power_on(void)
1411 {
1412 hal_gpd_power_on(gRIU_REG_BASE);
1413 }
1414
drv_gpd_power_off(void)1415 void drv_gpd_power_off(void)
1416 {
1417 hal_gpd_power_off(gRIU_REG_BASE);
1418 }
1419
drv_gpd_init_chip_specific_reg(void)1420 void drv_gpd_init_chip_specific_reg(void)
1421 {
1422 hal_gpd_init_chip_specific_reg();
1423 }
1424
is_stb()1425 MS_U32 is_stb()
1426 {
1427 #ifdef STB
1428
1429 return 1;
1430
1431 #else
1432
1433 return 0;
1434
1435 #endif
1436
1437 }
1438
MDrv_GPD_MIU_Select(MS_U32 u32Addr)1439 MS_U8 MDrv_GPD_MIU_Select(MS_U32 u32Addr)
1440 {
1441 if(u32Addr >=HAL_MIU1_BASE)
1442 {
1443 console_printf("GPD on MIU1!!!!!!!!!!!!\n");
1444 // MIU1
1445 return TRUE;
1446 }
1447 else
1448 {
1449 console_printf("GPD on MIU0!!!!!!!!!!!!\n");
1450 // MIU0
1451 return FALSE;
1452 }
1453 }
1454
1455
MDrv_GPD_Reg_Base(MS_U32 * u32RIUBase,MS_U32 * u32XIUBase)1456 void MDrv_GPD_Reg_Base(MS_U32* u32RIUBase, MS_U32* u32XIUBase)
1457 {
1458 hal_gpd_reg_base(u32RIUBase, u32XIUBase);
1459 }
1460
MDrv_GPD_MIU_Client(MS_U8 * u8Offset,MS_U16 * u16BitMask)1461 void MDrv_GPD_MIU_Client(MS_U8* u8Offset, MS_U16* u16BitMask)
1462 {
1463 hal_gpd_miu_client(u8Offset, u16BitMask);
1464 }
1465
1466 static GPD_IsrFuncCb _pGPDIsrCb = NULL;
1467 static MS_U8 bIsrEnable = FALSE;
_GPD_ISRHandler(MS_U32 IsrNum)1468 static void _GPD_ISRHandler(MS_U32 IsrNum)
1469 {
1470 console_printf("_GPD_ISRHandler: IsrNum = %td\n", (ptrdiff_t)IsrNum);
1471 if(_pGPDIsrCb)
1472 {
1473 _pGPDIsrCb();
1474 }
1475 }
1476
MDrv_GPD_EnableISR(GPD_IsrFuncCb IsrCb)1477 MS_U8 MDrv_GPD_EnableISR(GPD_IsrFuncCb IsrCb)
1478 {
1479 if(TRUE == bIsrEnable)
1480 {
1481 console_printf("GPD ISR has been enabled!!\n");
1482 return FALSE;
1483 }
1484
1485 if(TRUE == OSAL_GPD_ISR_Attach((OSAL_GPD_IsrFuncCb)_GPD_ISRHandler))
1486 {
1487 console_printf("Attach GPD ISR Success!!\n");
1488 if(TRUE == OSAL_GPD_ISR_Enable())
1489 {
1490 console_printf("MDrv_GPD_EnableISR : Success!!\n");
1491 bIsrEnable = TRUE;
1492 if(IsrCb)
1493 {
1494 _pGPDIsrCb = IsrCb;
1495 }
1496 return TRUE;
1497 }
1498 }
1499 GPD_DRV_ERROR("MDrv_GPD_EnableISR Failed!!\n");
1500 return FALSE;
1501 }
1502
1503 /********************************************************************/
MDrv_GPD_DisableISR(void)1504 MS_U8 MDrv_GPD_DisableISR(void)
1505 {
1506 if(FALSE == bIsrEnable)
1507 {
1508 console_printf("GPD ISR has been disabled!!\n");
1509 return FALSE;
1510 }
1511
1512 if(TRUE == OSAL_GPD_ISR_Disable())
1513 {
1514 console_printf("Disable GPD ISR Success!!\n");
1515 if(TRUE == OSAL_GPD_ISR_Detach())
1516 {
1517 console_printf("MDrv_GPD_DisableISR : Success!!\n");
1518 bIsrEnable = FALSE;
1519 _pGPDIsrCb = NULL;
1520 return TRUE;
1521 }
1522 }
1523 return FALSE;
1524 }
1525
MDrv_GPD_SetISRMask(void)1526 void MDrv_GPD_SetISRMask(void)
1527 {
1528 console_printf("1......\n");
1529 // GPD_SET_MS_U32REG(reg_int_mask, 0x1e);
1530 GPD_SET_MS_U32REG(reg_int_mask, 0x1c);
1531
1532 // GPD_SET_MS_U32REG(reg_int_sw_force, 0x1f);
1533 console_printf("2......\n");
1534 }
1535
1536
MDrv_GPD_PrintGPDBuf(void)1537 void MDrv_GPD_PrintGPDBuf(void)
1538 {
1539 console_printf("Dump Z buffer=============================start\n");
1540 _GPD_PrintMem(u32ZbufVA, 2*1024);
1541 console_printf("Dump Z buffer=============================end\n");
1542
1543 console_printf("Dump C buffer=============================start\n");
1544 _GPD_PrintMem(u32CbufVA, 32*1024);
1545 console_printf("Dump C buffer=============================end\n");
1546
1547 }
1548
1549
1550
drv_gpd_set_cacheable(MS_U32 u32Cacheable)1551 void drv_gpd_set_cacheable(MS_U32 u32Cacheable)
1552 {
1553 g_gpd_cacheable = u32Cacheable;
1554 }
1555
drv_gpd_get_cacheable(void)1556 MS_U32 drv_gpd_get_cacheable(void)
1557 {
1558 return g_gpd_cacheable;
1559 }
1560
drv_gpd_get_RIU_BASE(void)1561 MS_VIRT drv_gpd_get_RIU_BASE(void)
1562 {
1563 return gRIU_REG_BASE;
1564 }
1565
1566
drv_gpd_set_access_bound(MS_U32 w_start,MS_U32 w_end,MS_U32 i_start,MS_U32 i_end)1567 void drv_gpd_set_access_bound(MS_U32 w_start, MS_U32 w_end, MS_U32 i_start, MS_U32 i_end)
1568 {
1569 #ifdef GPD_MIU_WRITE_PROTECT_SUPPORT
1570 MS_U8 u8MiuSel = 0;
1571 MS_U32 u32Start = (MS_U32)MIN(w_start, i_start);
1572 _phy_to_miu_offset(u8MiuSel, u32Start, u32Start);
1573 MS_U32 u32End = (MS_U32)MAX(w_end, i_end);
1574 _phy_to_miu_offset(u8MiuSel, u32End, u32End);
1575 console_printf("[MIU protect]: [%lx, %lx]\n", u32Start, u32End);
1576 GPD_SET_MS_U32REG(reg_lb_addr, u32Start>>3);
1577 GPD_SET_MS_U32REG(reg_ub_addr, u32End>>3);
1578 #else
1579 UNUSED(w_start);
1580 UNUSED(w_end);
1581 UNUSED(i_start);
1582 UNUSED(i_end);
1583 #endif
1584 }
1585
1586