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Searched defs:domain (Results 1 – 22 of 22) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/drivers/apusys/devapc/
H A Dapusys_dapc_v1.h117 #define SLAVE_FORBID_EXCEPT_D0_SEC_RW(domain) \ argument
124 #define SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT(domain) \ argument
131 #define SLAVE_FORBID_EXCEPT_D5_NO_PROTECT(domain) \ argument
138 #define SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT(domain) \ argument
145 #define SLAVE_FORBID_EXCEPT_D7_NO_PROTECT(domain) \ argument
152 #define SLAVE_FORBID_EXCEPT_D5_D7_NO_PROTECT(domain) \ argument
159 #define SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT(domain) \ argument
166 #define SLAVE_FORBID_EXCEPT_D0_D11_NO_PROTECT_D3_D5_D8_SEC_RW(domain) \ argument
173 #define SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D3_D5_SEC_RW(domain) \ argument
180 #define SLAVE_FORBID_EXCEPT_D5_SEC_RW(domain) \ argument
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/rk3399_ARM-atf/plat/mediatek/drivers/emi_mpu/mt8188/
H A Demi_mpu_priv.h21 #define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + (domain * 4)) argument
23 #define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + (domain * 4)) argument
34 #define SUB_EMI_MPU_CTRL_D(domain) (SUB_EMI_MPU_CTRL_D0 + (domain * 4)) argument
36 #define SUB_EMI_RG_MASK_D(domain) (SUB_EMI_RG_MASK_D0 + (domain * 4)) argument
/rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8196/
H A Dapusys_ammu.c31 uint8_t domain, uint8_t acp_en, uint8_t aw_clr, in apummu_set_segment_offset2()
129 uint8_t domain, uint8_t ns) in apummu_add_map()
159 uint8_t *domain, uint8_t *ns) in apummu_get_dns()
192 uint8_t domain, ns, seg; in apummu_add_apmcu_map() local
224 uint8_t domain, ns; in apummu_add_rv_boot_map() local
H A Dapusys_security_ctrl_perm_plat.c37 uint8_t *domain, uint8_t *ns) in sec_get_dns()
H A Dapusys_ammu.h203 #define APUMMU_VSID_SEGMENT_08_DOMAIN(domain) \ argument
225 #define APUMMU_BUILD_SEGMENT_OFFSET2(resv, domain, acp_en, aw_clr, \ argument
/rk3399_ARM-atf/plat/imx/imx8ulp/upower/
H A Dupower_api.c488 int upwr_init(soc_domain_t domain, struct MU_t *muptr, in upwr_init()
795 int upwr_xcp_sw_alarm(soc_domain_t domain, in upwr_xcp_sw_alarm()
836 int upwr_xcp_set_ddr_retention(soc_domain_t domain, in upwr_xcp_set_ddr_retention()
877 int upwr_xcp_set_mipi_dsi_ena(soc_domain_t domain, in upwr_xcp_set_mipi_dsi_ena()
917 int upwr_xcp_get_mipi_dsi_ena(soc_domain_t domain, const upwr_callb callb) in upwr_xcp_get_mipi_dsi_ena()
955 int upwr_xcp_set_osc_mode(soc_domain_t domain, in upwr_xcp_set_osc_mode()
997 int upwr_xcp_set_rtd_use_ddr(soc_domain_t domain, in upwr_xcp_set_rtd_use_ddr()
1038 int upwr_xcp_set_rtd_apd_llwu(soc_domain_t domain, in upwr_xcp_set_rtd_apd_llwu()
1855 int upwr_pwm_dom_power_on(soc_domain_t domain, in upwr_pwm_dom_power_on()
1910 int upwr_pwm_boot_start(soc_domain_t domain, const upwr_callb bootcallb) in upwr_pwm_boot_start()
[all …]
H A Dupower_defs.h49 uint32_t domain : UPWR_PWDOMAIN_BITS; /* power domain */ member
354 uint32_t domain : 8U; member
380 uint32_t domain : 8U; member
H A Dupower_soc_defs.h122 uint32_t domain : 16U; member
895 static inline unsigned int upwr_sizeof_pmode_cfg(uint32_t domain) in upwr_sizeof_pmode_cfg()
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/apusys/
H A Dapupwr_clkctl.c115 int32_t apupwr_smc_acc_set_parent(uint32_t freq, uint32_t domain) in apupwr_smc_acc_set_parent()
200 int32_t apupwr_smc_pll_set_rate(uint32_t freq, bool div2, uint32_t domain) in apupwr_smc_pll_set_rate()
H A Dapupll.c90 static int32_t vd2pllidx(enum dvfs_voltage_domain domain) in vd2pllidx()
507 int32_t anpu_pll_set_rate(enum dvfs_voltage_domain domain, in anpu_pll_set_rate()
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/emi_mpu/
H A Demi_mpu.h23 #define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + (domain * 4)) argument
25 #define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + (domain * 4)) argument
38 #define SUB_EMI_MPU_CTRL_D(domain) (SUB_EMI_MPU_CTRL_D0 + (domain * 4)) argument
40 #define SUB_EMI_RG_MASK_D(domain) (SUB_EMI_RG_MASK_D0 + (domain * 4)) argument
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/emi_mpu/
H A Demi_mpu.h23 #define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + (domain * 4)) argument
25 #define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + (domain * 4)) argument
38 #define SUB_EMI_MPU_CTRL_D(domain) (SUB_EMI_MPU_CTRL_D0 + (domain * 4)) argument
40 #define SUB_EMI_RG_MASK_D(domain) (SUB_EMI_RG_MASK_D0 + (domain * 4)) argument
/rk3399_ARM-atf/drivers/arm/gicv5/
H A Dgicv5_main.c42 static inline bool iwb_domain_supported(uint32_t idr0, uint8_t domain) in iwb_domain_supported()
101 static void irs_configure_wire(uintptr_t base_addr, uint32_t wire, uint8_t domain) in irs_configure_wire()
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/emi_mpu/
H A Demi_mpu.h51 #define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + domain * 4) argument
53 #define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + domain * 4) argument
/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/devapc/
H A Ddevapc.c32 static void set_master_domain(uint32_t master_index, enum MASK_DOM domain) in set_master_domain()
/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv3_2/
H A Dmt_cpu_pm.c337 static unsigned int cpupm_get_pstate(enum mt_cpupm_pwr_domain domain, in cpupm_get_pstate()
/rk3399_ARM-atf/include/drivers/arm/
H A Dgicv5.h178 uint8_t domain:2; member
/rk3399_ARM-atf/plat/mediatek/lib/pm/armv8_2/
H A Dpwr_ctrl.c80 static unsigned int get_mediatek_pstate(unsigned int domain, unsigned int psci_state, in get_mediatek_pstate()
/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv5_4/
H A Dmt_cpu_pm.c698 static unsigned int cpupm_get_pstate(enum mt_cpupm_pwr_domain domain, in cpupm_get_pstate()
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/secure/
H A Dfirewall.c72 uint32_t domain[FW_SGRF_MST_DOMAIN_CON_CNT]; member
/rk3399_ARM-atf/plat/mediatek/drivers/thermal/inc/
H A Dthermal_lvts.h178 struct power_domain *domain; member
/rk3399_ARM-atf/drivers/ti/ti_sci/
H A Dti_sci_protocol.h138 uint8_t domain; member