Searched defs:ccm_regs (Results 1 – 3 of 3) sorted by relevance
209 struct ccm_regs { struct210 u32 ccmr; /* Control */211 u32 pdr0; /* Post divider 0 */212 u32 pdr1; /* Post divider 1 */213 u32 pdr2; /* Post divider 2 */214 u32 pdr3; /* Post divider 3 */215 u32 pdr4; /* Post divider 4 */216 u32 rcsr; /* CCM Status */217 u32 mpctl; /* Core PLL Control */218 u32 ppctl; /* Peripheral PLL Control */[all …]
24 struct ccm_regs { struct25 u32 mpctl; /* Core PLL Control */26 u32 upctl; /* USB PLL Control */27 u32 cctl; /* Clock Control */28 u32 cgr0; /* Clock Gating Control 0 */29 u32 cgr1; /* Clock Gating Control 1 */30 u32 cgr2; /* Clock Gating Control 2 */31 u32 pcdr[4]; /* PER Clock Dividers */32 u32 rcsr; /* CCM Status */33 u32 crdr; /* CCM Reset and Debug */[all …]
1111 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in enable_pcie_clock() local