1 /*
2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <version.h>
9 #include <boot_rkimg.h>
10 #include <debug_uart.h>
11 #include <dm.h>
12 #include <envf.h>
13 #include <key.h>
14 #include <led.h>
15 #include <misc.h>
16 #include <mtd_blk.h>
17 #include <ram.h>
18 #include <spl.h>
19 #include <spl_ab.h>
20 #include <optee_include/OpteeClientInterface.h>
21 #include <power/fuel_gauge.h>
22 #include <asm/arch/bootrom.h>
23 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS
24 #include <asm/arch/rk_atags.h>
25 #endif
26 #include <asm/arch/pcie_ep_boot.h>
27 #include <asm/arch/sdram.h>
28 #include <asm/arch/boot_mode.h>
29 #include <asm/arch-rockchip/sys_proto.h>
30 #include <asm/io.h>
31 #include <asm/arch/param.h>
32 #include <asm/arch/rk_hwid.h>
33 #include <asm/arch/rk_meta.h>
34
35 DECLARE_GLOBAL_DATA_PTR;
36
board_return_to_bootrom(void)37 void board_return_to_bootrom(void)
38 {
39 back_to_bootrom(BROM_BOOT_NEXTSTAGE);
40 }
41
42 __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
43 };
44
spl_rk_board_prepare_for_jump(struct spl_image_info * spl_image)45 __weak void spl_rk_board_prepare_for_jump(struct spl_image_info *spl_image)
46 {
47 }
48
board_spl_was_booted_from(void)49 const char *board_spl_was_booted_from(void)
50 {
51 u32 bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
52 const char *bootdevice_ofpath = NULL;
53
54 if ((bootdevice_brom_id & BROM_DOWNLOAD_MASK) == BROM_DOWNLOAD_MASK)
55 bootdevice_brom_id = BROM_BOOTSOURCE_USB;
56
57 bootdevice_brom_id = bootdevice_brom_id & BROM_BOOTSOURCE_MASK;
58 if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
59 bootdevice_ofpath = boot_devices[bootdevice_brom_id];
60
61 if (bootdevice_ofpath)
62 debug("%s: brom_bootdevice_id %x maps to '%s'\n",
63 __func__, bootdevice_brom_id, bootdevice_ofpath);
64 else
65 debug("%s: failed to resolve brom_bootdevice_id %x\n",
66 __func__, bootdevice_brom_id);
67
68 return bootdevice_ofpath;
69 }
70
spl_boot_device(void)71 u32 spl_boot_device(void)
72 {
73 u32 boot_device = BOOT_DEVICE_MMC1;
74
75 #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
76 defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
77 defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
78 return BOOT_DEVICE_SPI;
79 #endif
80 if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
81 return BOOT_DEVICE_BOOTROM;
82
83 return boot_device;
84 }
85
spl_boot_mode(const u32 boot_device)86 u32 spl_boot_mode(const u32 boot_device)
87 {
88 return MMCSD_MODE_RAW;
89 }
90
rockchip_stimer_init(void)91 __weak void rockchip_stimer_init(void)
92 {
93 /* If Timer already enabled, don't re-init it */
94 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
95 if ( reg & 0x1 )
96 return;
97 #ifdef COUNTER_FREQUENCY
98 #ifndef CONFIG_ARM64
99 asm volatile("mcr p15, 0, %0, c14, c0, 0"
100 : : "r"(COUNTER_FREQUENCY));
101 #endif
102 #endif
103 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
104 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
105 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
106 writel(1, CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
107 }
108
arch_cpu_init(void)109 __weak int arch_cpu_init(void)
110 {
111 return 0;
112 }
113
rk_board_init_f(void)114 __weak int rk_board_init_f(void)
115 {
116 return 0;
117 }
118
119 #ifndef CONFIG_SPL_LIBGENERIC_SUPPORT
udelay(unsigned long usec)120 void udelay(unsigned long usec)
121 {
122 __udelay(usec);
123 }
124
hang(void)125 void hang(void)
126 {
127 bootstage_error(BOOTSTAGE_ID_NEED_RESET);
128 for (;;)
129 ;
130 }
131
132 /**
133 * memset - Fill a region of memory with the given value
134 * @s: Pointer to the start of the area.
135 * @c: The byte to fill the area with
136 * @count: The size of the area.
137 *
138 * Do not use memset() to access IO space, use memset_io() instead.
139 */
memset(void * s,int c,size_t count)140 void *memset(void *s, int c, size_t count)
141 {
142 unsigned long *sl = (unsigned long *)s;
143 char *s8;
144
145 #if !CONFIG_IS_ENABLED(TINY_MEMSET)
146 unsigned long cl = 0;
147 int i;
148
149 /* do it one word at a time (32 bits or 64 bits) while possible */
150 if (((ulong)s & (sizeof(*sl) - 1)) == 0) {
151 for (i = 0; i < sizeof(*sl); i++) {
152 cl <<= 8;
153 cl |= c & 0xff;
154 }
155 while (count >= sizeof(*sl)) {
156 *sl++ = cl;
157 count -= sizeof(*sl);
158 }
159 }
160 #endif /* fill 8 bits at a time */
161 s8 = (char *)sl;
162 while (count--)
163 *s8++ = c;
164
165 return s;
166 }
167 #endif
168
169 #ifdef CONFIG_SPL_DM_RESET
brom_download(void)170 static void brom_download(void)
171 {
172 if (gd->console_evt == 0x02) {
173 printf("ctrl+b: Bootrom download!\n");
174 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG);
175 do_reset(NULL, 0, 0, NULL);
176 }
177 }
178 #endif
179
spl_hotkey_init(void)180 static void spl_hotkey_init(void)
181 {
182 /* If disable console, skip getting uart reg */
183 if (!gd || gd->flags & GD_FLG_DISABLE_CONSOLE)
184 return;
185 if (!gd->have_console)
186 return;
187
188 /* serial uclass only exists when enable CONFIG_SPL_FRAMEWORK */
189 #ifdef CONFIG_SPL_FRAMEWORK
190 if (serial_tstc()) {
191 gd->console_evt = serial_getc();
192 #else
193 if (debug_uart_tstc()) {
194 gd->console_evt = debug_uart_getc();
195 #endif
196 if (gd->console_evt <= 0x1a) /* 'z' */
197 printf("SPL Hotkey: ctrl+%c\n",
198 gd->console_evt + 'a' - 1);
199 }
200
201 return;
202 }
203
204 void board_init_f(ulong dummy)
205 {
206 #ifdef CONFIG_SPL_FRAMEWORK
207 int ret;
208 #if !defined(CONFIG_SUPPORT_TPL)
209 struct udevice *dev;
210 #endif
211 #endif
212 gd->flags = dummy;
213 rockchip_stimer_init();
214 #define EARLY_UART
215 #if defined(EARLY_UART) && defined(CONFIG_DEBUG_UART)
216 /*
217 * Debug UART can be used from here if required:
218 *
219 * debug_uart_init();
220 * printch('a');
221 * printhex8(0x1234);
222 * printascii("string");
223 */
224 if (!gd->serial.using_pre_serial &&
225 !(gd->flags & GD_FLG_DISABLE_CONSOLE))
226 debug_uart_init();
227 printascii("U-Boot SPL board init");
228 #endif
229 gd->sys_start_tick = get_ticks();
230 #ifdef CONFIG_SPL_PCIE_EP_SUPPORT
231 rockchip_pcie_ep_init();
232 #endif
233 #ifdef CONFIG_SPL_FRAMEWORK
234 ret = spl_early_init();
235 if (ret) {
236 printf("spl_early_init() failed: %d\n", ret);
237 hang();
238 }
239 #if !defined(CONFIG_SUPPORT_TPL)
240 debug("\nspl:init dram\n");
241 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
242 if (ret) {
243 printf("DRAM init failed: %d\n", ret);
244 return;
245 }
246 #endif
247 preloader_console_init();
248 #else
249 /* Some SoCs like rk3036 does not use any frame work */
250 sdram_init();
251 #endif
252 /* Get hotkey and store in gd */
253 spl_hotkey_init();
254 #ifdef CONFIG_SPL_DM_RESET
255 brom_download();
256 #endif
257 arch_cpu_init();
258 rk_board_init_f();
259 #if defined(CONFIG_SPL_RAM_DEVICE) && defined(CONFIG_SPL_PCIE_EP_SUPPORT)
260 rockchip_pcie_ep_get_firmware();
261 #endif
262 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
263 back_to_bootrom(BROM_BOOT_NEXTSTAGE);
264 #endif
265
266 }
267
268 #ifdef CONFIG_SPL_LOAD_FIT
269 int board_fit_config_name_match(const char *name)
270 {
271 /* Just empty function now - can't decide what to choose */
272 debug("%s: %s\n", __func__, name);
273
274 return 0;
275 }
276 #endif
277
278 int board_init_f_boot_flags(void)
279 {
280 int boot_flags = 0;
281
282 #ifdef CONFIG_ARM64
283 asm volatile("mrs %0, cntfrq_el0" : "=r" (gd->arch.timer_rate_hz));
284 #else
285 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (gd->arch.timer_rate_hz));
286 #endif
287
288 #if CONFIG_IS_ENABLED(FPGA_ROCKCHIP)
289 arch_fpga_init();
290 #endif
291 #ifdef CONFIG_PSTORE
292 param_parse_pstore();
293 #endif
294 /* pre-loader serial */
295 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \
296 defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS)
297 struct tag *t;
298
299 t = atags_get_tag(ATAG_SERIAL);
300 if (t) {
301 gd->serial.using_pre_serial = 1;
302 gd->serial.enable = t->u.serial.enable;
303 gd->serial.baudrate = t->u.serial.baudrate;
304 gd->serial.addr = t->u.serial.addr;
305 gd->serial.id = t->u.serial.id;
306 gd->baudrate = t->u.serial.baudrate;
307 if (!t->u.serial.enable)
308 boot_flags |= GD_FLG_DISABLE_CONSOLE;
309 debug("preloader: enable=%d, addr=0x%x, baudrate=%d, id=%d\n",
310 t->u.serial.enable, (u32)t->u.serial.addr,
311 t->u.serial.baudrate, t->u.serial.id);
312 } else
313 #endif
314 {
315 gd->baudrate = CONFIG_BAUDRATE;
316 gd->serial.baudrate = CONFIG_BAUDRATE;
317 gd->serial.addr = CONFIG_DEBUG_UART_BASE;
318 }
319
320 /* The highest priority to turn off (override) console */
321 #if defined(CONFIG_DISABLE_CONSOLE)
322 boot_flags |= GD_FLG_DISABLE_CONSOLE;
323 #endif
324
325 return boot_flags;
326 }
327
328 #ifdef CONFIG_SPL_BOARD_INIT
329 __weak int rk_spl_board_init(void)
330 {
331 return 0;
332 }
333
334 static int setup_led(void)
335 {
336 #ifdef CONFIG_SPL_LED
337 struct udevice *dev;
338 char *led_name;
339 int ret;
340
341 led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
342 if (!led_name)
343 return 0;
344 ret = led_get_by_label(led_name, &dev);
345 if (ret) {
346 debug("%s: get=%d\n", __func__, ret);
347 return ret;
348 }
349 ret = led_set_state(dev, LEDST_ON);
350 if (ret)
351 return ret;
352 #endif
353
354 return 0;
355 }
356
357 void spl_board_init(void)
358 {
359 int ret;
360
361 ret = setup_led();
362
363 if (ret) {
364 debug("LED ret=%d\n", ret);
365 hang();
366 }
367
368 rk_spl_board_init();
369 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
370 back_to_bootrom(BROM_BOOT_NEXTSTAGE);
371 #endif
372 return;
373 }
374 #endif
375
376 #ifdef CONFIG_SPL_KERNEL_BOOT
377 static int spl_rockchip_dnl_key_pressed(void)
378 {
379 #if defined(CONFIG_SPL_INPUT)
380 return key_read(KEY_VOLUMEUP);
381 #else
382 return 0;
383 #endif
384 }
385
386 #ifdef CONFIG_SPL_DM_FUEL_GAUGE
387 bool spl_is_low_power(void)
388 {
389 struct udevice *dev;
390 int ret, voltage;
391
392 ret = uclass_get_device(UCLASS_FG, 0, &dev);
393 if (ret) {
394 debug("Get charge display failed, ret=%d\n", ret);
395 return false;
396 }
397
398 voltage = fuel_gauge_get_voltage(dev);
399 if (voltage >= CONFIG_SPL_POWER_LOW_VOLTAGE_THRESHOLD)
400 return false;
401
402 return true;
403 }
404 #endif
405
406 void spl_next_stage(struct spl_image_info *spl)
407 {
408 const char *reason[] = { "Recovery key", "Ctrl+c", "LowPwr", "Other" };
409 uint32_t reg_boot_mode;
410 int i = 0;
411
412 if (spl_rockchip_dnl_key_pressed()) {
413 i = 0;
414 spl->next_stage = SPL_NEXT_STAGE_UBOOT;
415 goto out;
416 }
417
418 if (gd->console_evt == 0x03) {
419 i = 1;
420 spl->next_stage = SPL_NEXT_STAGE_UBOOT;
421 goto out;
422 }
423
424 #ifdef CONFIG_SPL_DM_FUEL_GAUGE
425 if (spl_is_low_power()) {
426 i = 2;
427 spl->next_stage = SPL_NEXT_STAGE_UBOOT;
428 goto out;
429 }
430 #endif
431
432 reg_boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG);
433 switch (reg_boot_mode) {
434 case BOOT_LOADER:
435 case BOOT_FASTBOOT:
436 case BOOT_CHARGING:
437 case BOOT_UMS:
438 case BOOT_DFU:
439 i = 3;
440 spl->next_stage = SPL_NEXT_STAGE_UBOOT;
441 break;
442 default:
443 spl->next_stage = SPL_NEXT_STAGE_KERNEL;
444 }
445
446 out:
447 if (spl->next_stage == SPL_NEXT_STAGE_UBOOT)
448 printf("Enter uboot reason: %s\n", reason[i]);
449
450 return;
451 }
452
453 const char *spl_kernel_partition(struct spl_image_info *spl,
454 struct spl_load_info *info)
455 {
456 struct bootloader_message *bmsg = NULL;
457 u32 boot_mode;
458 int ret, cnt;
459 u32 sector = 0;
460
461 #ifdef CONFIG_SPL_LIBDISK_SUPPORT
462 disk_partition_t part_info;
463
464 ret = part_get_info_by_name(info->dev, PART_MISC, &part_info);
465 if (ret >= 0)
466 sector = part_info.start;
467 #else
468 sector = CONFIG_SPL_MISC_SECTOR;
469 #endif
470 if (sector) {
471 cnt = DIV_ROUND_UP(sizeof(*bmsg), info->bl_len);
472 bmsg = memalign(ARCH_DMA_MINALIGN, cnt * info->bl_len);
473 ret = info->read(info, sector + BCB_MESSAGE_BLK_OFFSET,
474 cnt, bmsg);
475 if (ret == cnt && !strcmp(bmsg->command, "boot-recovery")) {
476 free(bmsg);
477 return PART_RECOVERY;
478 } else {
479 free(bmsg);
480 }
481 }
482
483 boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG);
484
485 return (boot_mode == BOOT_RECOVERY) ? PART_RECOVERY : PART_BOOT;
486 }
487
488 __weak void spl_fdt_fixup_memory(struct spl_image_info *spl_image)
489 {
490 void *blob = spl_image->fdt_addr;
491 struct tag *t;
492 u64 start[CONFIG_NR_DRAM_BANKS];
493 u64 size[CONFIG_NR_DRAM_BANKS];
494 int i, count, err;
495
496 err = fdt_check_header(blob);
497 if (err < 0) {
498 printf("Invalid dtb\n");
499 return;
500 }
501
502 /* Fixup memory node based on ddr_mem atags */
503 t = atags_get_tag(ATAG_DDR_MEM);
504 if (t && t->u.ddr_mem.count) {
505 count = t->u.ddr_mem.count;
506 for (i = 0; i < count; i++) {
507 start[i] = t->u.ddr_mem.bank[i];
508 size[i] = t->u.ddr_mem.bank[i + count];
509 #ifdef SPL_RESV_MEM_SIZE
510 if ((start[i] == CONFIG_SYS_SDRAM_BASE) &&
511 (start[i] + size[i] > CONFIG_SYS_SDRAM_BASE + SPL_RESV_MEM_SIZE))
512 start[i] += SPL_RESV_MEM_SIZE;
513 #endif
514 if (size[i] == 0)
515 continue;
516 debug("Adding bank: 0x%08llx - 0x%08llx (size: 0x%08llx)\n",
517 start[i], start[i] + size[i], size[i]);
518 }
519
520 fdt_increase_size(blob, 512);
521
522 err = fdt_fixup_memory_banks(blob, start, size, count);
523 if (err < 0) {
524 printf("Fixup kernel dtb memory node failed: %s\n", fdt_strerror(err));
525 return;
526 }
527 }
528
529 return;
530 }
531
532 #if defined(CONFIG_SPL_ROCKCHIP_HWID_DTB)
533 int spl_find_hwid_dtb(const char *fdt_name)
534 {
535 hwid_init_data();
536
537 return hwid_dtb_is_available(fdt_name);
538 }
539 #endif
540
541 int spl_fdt_chosen_bootargs(struct spl_load_info *info, void *fdt)
542 {
543 __maybe_unused struct blk_desc *desc = info->dev;
544
545 #ifdef CONFIG_SPL_AB
546 char slot_suffix[3] = {0};
547
548 if (!spl_get_current_slot(desc, "misc", slot_suffix))
549 spl_ab_bootargs_append_slot(fdt, slot_suffix);
550 #endif
551
552 #ifdef CONFIG_SPL_ENVF
553 char *part_type[] = { "mtdparts", "blkdevparts" };
554 char *env = NULL;
555 char *part_list;
556 int id = 0, ret = 0;
557
558 env = envf_get(desc, part_type[id]);
559 if (!env)
560 env = envf_get(desc, part_type[++id]);
561 if (env) {
562 if (!strstr(env, part_type[id])) {
563 part_list = calloc(1, strlen(env) + strlen(part_type[id]) + 2);
564 if (part_list) {
565 strcat(part_list, part_type[id]);
566 strcat(part_list, "=");
567 strcat(part_list, env);
568 }
569 } else {
570 part_list = env;
571 }
572 ret = fdt_bootargs_append(fdt, part_list);
573 if (ret) {
574 printf("Append parts info to bootargs fail");
575 return ret;
576 }
577 debug("## parts: %s\n\n", part_list);
578
579 env = envf_get(desc, "sys_bootargs");
580 env = env + strlen("sys_bootargs=");
581 if (env) {
582 ret = fdt_bootargs_append(fdt, env);
583 if (ret) {
584 printf("Append sys_bootargs to bootargs fail");
585 return ret;
586 }
587 debug("## sys_bootargs: %s\n\n", env);
588 }
589 }
590 #endif
591 #ifdef CONFIG_MTD_BLK
592 if (!env && desc->if_type == IF_TYPE_MTD) {
593 char *mtd_par_info = mtd_part_parse(desc);
594
595 ret = fdt_bootargs_append(fdt, mtd_par_info);
596 if (ret) {
597 printf("Append mtdparts info to bootargs fail");
598 return ret;
599 }
600 debug("## mtdparts: %s\n\n", mtd_par_info);
601 }
602 #endif
603 #ifdef CONFIG_ROCKCHIP_META
604 rk_meta_bootargs_append(fdt);
605 #endif
606
607 return 0;
608 }
609 #endif
610
611 void spl_perform_fixups(struct spl_image_info *spl_image)
612 {
613 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS
614 atags_set_bootdev_by_spl_bootdevice(spl_image->boot_device);
615 #ifdef BUILD_SPL_TAG
616 atags_set_shared_fwver(FW_SPL, "spl-"BUILD_SPL_TAG);
617 #endif
618 #endif
619 #if defined(CONFIG_SPL_KERNEL_BOOT)
620 if (spl_image->next_stage == SPL_NEXT_STAGE_KERNEL)
621 spl_fdt_fixup_memory(spl_image);
622 #endif
623 return;
624 }
625
626 void spl_hang_reset(void)
627 {
628 printf("# Reset the board to bootrom #\n");
629 #if defined(CONFIG_SPL_SYSRESET) && defined(CONFIG_SPL_DRIVERS_MISC_SUPPORT)
630 /* reset is available after dm setup */
631 if (gd->flags & GD_FLG_SPL_EARLY_INIT) {
632 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG);
633 do_reset(NULL, 0, 0, NULL);
634 }
635 #endif
636 }
637
638 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT
639 int fit_read_otp_rollback_index(uint32_t fit_index, uint32_t *otp_index)
640 {
641 int ret = 0;
642
643 *otp_index = 0;
644 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP)
645 struct udevice *dev;
646 u32 index, i, otp_version;
647 u32 bit_count;
648
649 dev = misc_otp_get_device(OTP_S);
650 if (!dev)
651 return -ENODEV;
652
653 otp_version = 0;
654 for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) {
655 if (misc_otp_read(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4,
656 &index,
657 4)) {
658 printf("Can't read rollback index\n");
659 return -EIO;
660 }
661
662 bit_count = fls(index);
663 otp_version += bit_count;
664 }
665 *otp_index = otp_version;
666 #endif
667
668 return ret;
669 }
670
671 static int fit_write_otp_rollback_index(u32 fit_index)
672 {
673 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP)
674 struct udevice *dev;
675 u32 index, i, otp_index;
676
677 if (!fit_index)
678 return 0;
679
680 if (fit_index > OTP_UBOOT_ROLLBACK_WORDS * 32)
681 return -EINVAL;
682
683 dev = misc_otp_get_device(OTP_S);
684 if (!dev)
685 return -ENODEV;
686
687 if (fit_read_otp_rollback_index(fit_index, &otp_index))
688 return -EIO;
689
690 if (otp_index < fit_index) {
691 /* Write new SW version to otp */
692 for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) {
693 /*
694 * If fit_index is equal to 0, then execute 0xffffffff >> 32.
695 * But the operand can only be 0 - 31. The "0xffffffff >> 32" is
696 * actually be "0xffffffff >> 0".
697 */
698 if (!fit_index)
699 break;
700 /* convert to base-1 representation */
701 index = 0xffffffff >> (OTP_ALL_ONES_NUM_BITS -
702 min(fit_index, (u32)OTP_ALL_ONES_NUM_BITS));
703 fit_index -= min(fit_index,
704 (u32)OTP_ALL_ONES_NUM_BITS);
705 if (index) {
706 if (misc_otp_write(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4,
707 &index,
708 4)) {
709 printf("Can't write rollback index\n");
710 return -EIO;
711 }
712 }
713 }
714 }
715 #endif
716
717 return 0;
718 }
719 #endif
720
721 int spl_board_prepare_for_jump(struct spl_image_info *spl_image)
722 {
723 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT
724 int ret;
725
726 ret = fit_write_otp_rollback_index(gd->rollback_index);
727 if (ret) {
728 panic("Failed to write fit rollback index %d, ret=%d",
729 gd->rollback_index, ret);
730 }
731 #endif
732
733 #ifdef CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS
734 misc_decompress_cleanup();
735 #endif
736 spl_rk_board_prepare_for_jump(spl_image);
737
738 return 0;
739 }
740