1 /*
2 * Copyright (c) 2018-2023, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <inttypes.h>
8 #include <stdint.h>
9 #include <string.h>
10
11 #include <libfdt.h>
12
13 #include <platform_def.h>
14
15 #include <arch_helpers.h>
16 #include <bl1/bl1.h>
17 #include <common/bl_common.h>
18 #include <common/debug.h>
19 #include <common/desc_image_load.h>
20 #include <common/image_decompress.h>
21 #include <drivers/console.h>
22 #include <drivers/io/io_driver.h>
23 #include <drivers/io/io_storage.h>
24 #include <lib/mmio.h>
25 #include <lib/xlat_tables/xlat_tables_defs.h>
26 #include <plat/common/platform.h>
27 #if RCAR_GEN3_BL33_GZIP == 1
28 #include <tf_gunzip.h>
29 #endif
30
31 #include "avs_driver.h"
32 #include "boot_init_dram.h"
33 #include "cpg_registers.h"
34 #include "board.h"
35 #include "emmc_def.h"
36 #include "emmc_hal.h"
37 #include "emmc_std.h"
38
39 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
40 #include "iic_dvfs.h"
41 #endif
42
43 #include "io_common.h"
44 #include "io_rcar.h"
45 #include "qos_init.h"
46 #include "rcar_def.h"
47 #include "rcar_private.h"
48 #include "rcar_version.h"
49 #include "rom_api.h"
50
51 /*
52 * Following symbols are only used during plat_arch_setup()
53 */
54 static const uint64_t BL2_RO_BASE = BL_CODE_BASE;
55 static const uint64_t BL2_RO_LIMIT = BL_CODE_END;
56
57 #if USE_COHERENT_MEM
58 static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE;
59 static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END;
60 #endif
61
62 extern void plat_rcar_gic_driver_init(void);
63 extern void plat_rcar_gic_init(void);
64 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info);
65 extern void bl2_system_cpg_init(void);
66 extern void bl2_secure_setting(void);
67 extern void bl2_ram_security_setting_finish(void);
68 extern void bl2_cpg_init(void);
69 extern void rcar_io_emmc_setup(void);
70 extern void rcar_io_setup(void);
71 extern void rcar_swdt_release(void);
72 extern void rcar_swdt_init(void);
73 extern void rcar_rpc_init(void);
74 extern void rcar_pfc_init(void);
75 extern void rcar_dma_init(void);
76
77 static void bl2_init_generic_timer(void);
78
79 /* R-Car Gen3 product check */
80 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
81 #define TARGET_PRODUCT PRR_PRODUCT_H3
82 #define TARGET_NAME "R-Car H3"
83 #elif RCAR_LSI == RCAR_M3
84 #define TARGET_PRODUCT PRR_PRODUCT_M3
85 #define TARGET_NAME "R-Car M3"
86 #elif RCAR_LSI == RCAR_M3N
87 #define TARGET_PRODUCT PRR_PRODUCT_M3N
88 #define TARGET_NAME "R-Car M3N"
89 #elif RCAR_LSI == RCAR_V3M
90 #define TARGET_PRODUCT PRR_PRODUCT_V3M
91 #define TARGET_NAME "R-Car V3M"
92 #elif RCAR_LSI == RCAR_E3
93 #define TARGET_PRODUCT PRR_PRODUCT_E3
94 #define TARGET_NAME "R-Car E3"
95 #elif RCAR_LSI == RCAR_D3
96 #define TARGET_PRODUCT PRR_PRODUCT_D3
97 #define TARGET_NAME "R-Car D3"
98 #elif RCAR_LSI == RCAR_AUTO
99 #define TARGET_NAME "R-Car H3/M3/M3N/V3M"
100 #endif
101
102 #if (RCAR_LSI == RCAR_E3)
103 #define GPIO_INDT (GPIO_INDT6)
104 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<13U)
105 #else
106 #define GPIO_INDT (GPIO_INDT1)
107 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<8U)
108 #endif
109
110 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100)
111 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE),
112 assert_bl31_params_do_not_fit_in_shared_memory);
113
114 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
115
116 /* FDT with DRAM configuration */
117 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)];
118 static void *fdt = (void *)fdt_blob;
119
unsigned_num_print(unsigned long long int unum,unsigned int radix,char * string)120 static void unsigned_num_print(unsigned long long int unum, unsigned int radix,
121 char *string)
122 {
123 /* Just need enough space to store 64 bit decimal integer */
124 char num_buf[20];
125 int i = 0;
126 unsigned int rem;
127
128 do {
129 rem = unum % radix;
130 if (rem < 0xa)
131 num_buf[i] = '0' + rem;
132 else
133 num_buf[i] = 'a' + (rem - 0xa);
134 i++;
135 unum /= radix;
136 } while (unum > 0U);
137
138 while (--i >= 0)
139 *string++ = num_buf[i];
140 *string = 0;
141 }
142
143 #if (RCAR_LOSSY_ENABLE == 1)
144 typedef struct bl2_lossy_info {
145 uint32_t magic;
146 uint32_t a0;
147 uint32_t b0;
148 } bl2_lossy_info_t;
149
bl2_lossy_gen_fdt(uint32_t no,uint64_t start_addr,uint64_t end_addr,uint32_t format,uint32_t enable,int fcnlnode)150 static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr,
151 uint64_t end_addr, uint32_t format,
152 uint32_t enable, int fcnlnode)
153 {
154 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr);
155 char nodename[40] = { 0 };
156 int ret, node;
157
158 /* Ignore undefined addresses */
159 if (start_addr == 0 && end_addr == 0)
160 return;
161
162 snprintf(nodename, sizeof(nodename), "lossy-decompression@");
163 unsigned_num_print(start_addr, 16, nodename + strlen(nodename));
164
165 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename);
166 if (ret < 0) {
167 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret);
168 panic();
169 }
170
171 ret = fdt_setprop_string(fdt, node, "compatible",
172 "renesas,lossy-decompression");
173 if (ret < 0) {
174 NOTICE("BL2: Cannot add FCNL compat string (ret=%i)\n", ret);
175 panic();
176 }
177
178 ret = fdt_appendprop_string(fdt, node, "compatible",
179 "shared-dma-pool");
180 if (ret < 0) {
181 NOTICE("BL2: Cannot append FCNL compat string (ret=%i)\n", ret);
182 panic();
183 }
184
185 ret = fdt_setprop_u64(fdt, node, "reg", start_addr);
186 if (ret < 0) {
187 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret);
188 panic();
189 }
190
191 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize));
192 if (ret < 0) {
193 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret);
194 panic();
195 }
196
197 ret = fdt_setprop(fdt, node, "no-map", NULL, 0);
198 if (ret < 0) {
199 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret);
200 panic();
201 }
202
203 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format);
204 if (ret < 0) {
205 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret);
206 panic();
207 }
208 }
209
bl2_lossy_setting(uint32_t no,uint64_t start_addr,uint64_t end_addr,uint32_t format,uint32_t enable,int fcnlnode)210 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr,
211 uint64_t end_addr, uint32_t format,
212 uint32_t enable, int fcnlnode)
213 {
214 bl2_lossy_info_t info;
215 uint32_t reg;
216
217 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode);
218
219 reg = format | (start_addr >> 20);
220 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg);
221 mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, end_addr >> 20);
222 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable);
223
224 info.magic = 0x12345678U;
225 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no);
226 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no);
227
228 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic);
229 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4, info.a0);
230 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8, info.b0);
231
232 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no,
233 mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no),
234 mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no));
235 }
236
bl2_create_reserved_memory(void)237 static int bl2_create_reserved_memory(void)
238 {
239 int ret;
240
241 int fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory");
242 if (fcnlnode < 0) {
243 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n",
244 fcnlnode);
245 panic();
246 }
247
248 ret = fdt_setprop(fdt, fcnlnode, "ranges", NULL, 0);
249 if (ret < 0) {
250 NOTICE("BL2: Cannot add FCNL ranges prop (ret=%i)\n", ret);
251 panic();
252 }
253
254 ret = fdt_setprop_u32(fdt, fcnlnode, "#address-cells", 2);
255 if (ret < 0) {
256 NOTICE("BL2: Cannot add FCNL #address-cells prop (ret=%i)\n", ret);
257 panic();
258 }
259
260 ret = fdt_setprop_u32(fdt, fcnlnode, "#size-cells", 2);
261 if (ret < 0) {
262 NOTICE("BL2: Cannot add FCNL #size-cells prop (ret=%i)\n", ret);
263 panic();
264 }
265
266 return fcnlnode;
267 }
268
bl2_create_fcnl_reserved_memory(void)269 static void bl2_create_fcnl_reserved_memory(void)
270 {
271 int fcnlnode;
272
273 NOTICE("BL2: Lossy Decomp areas\n");
274
275 fcnlnode = bl2_create_reserved_memory();
276
277 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0,
278 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode);
279 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1,
280 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode);
281 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2,
282 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode);
283 }
284 #else
bl2_create_fcnl_reserved_memory(void)285 static void bl2_create_fcnl_reserved_memory(void) {}
286 #endif
287
bl2_plat_flush_bl31_params(void)288 void bl2_plat_flush_bl31_params(void)
289 {
290 uint32_t product_cut, product, cut;
291 uint32_t boot_dev, boot_cpu;
292 uint32_t lcs, reg, val;
293
294 reg = mmio_read_32(RCAR_MODEMR);
295 boot_dev = reg & MODEMR_BOOT_DEV_MASK;
296
297 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
298 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8)
299 emmc_terminate();
300
301 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7)
302 bl2_secure_setting();
303
304 reg = mmio_read_32(RCAR_PRR);
305 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
306 product = reg & PRR_PRODUCT_MASK;
307 cut = reg & PRR_CUT_MASK;
308
309 if (product == PRR_PRODUCT_M3 && PRR_PRODUCT_30 > cut)
310 goto tlb;
311
312 if (product == PRR_PRODUCT_H3 && PRR_PRODUCT_20 > cut)
313 goto tlb;
314
315 /* Disable MFIS write protection */
316 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1);
317
318 tlb:
319 reg = mmio_read_32(RCAR_MODEMR);
320 boot_cpu = reg & MODEMR_BOOT_CPU_MASK;
321 if (boot_cpu != MODEMR_BOOT_CPU_CA57 &&
322 boot_cpu != MODEMR_BOOT_CPU_CA53)
323 goto mmu;
324
325 if (product_cut == PRR_PRODUCT_H3_CUT20) {
326 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
327 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE);
328 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
329 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE);
330 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE);
331 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE);
332 } else if (product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) ||
333 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11)) {
334 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
335 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
336 } else if ((product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) ||
337 (product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_11))) {
338 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
339 mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE);
340 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
341 }
342
343 if (product_cut == (PRR_PRODUCT_H3_CUT20) ||
344 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) ||
345 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11) ||
346 product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) {
347 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE);
348 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE);
349 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE);
350
351 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE);
352 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE);
353 }
354
355 mmu:
356 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE);
357 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT);
358
359 val = rcar_rom_get_lcs(&lcs);
360 if (val) {
361 ERROR("BL2: Failed to get the LCS. (%d)\n", val);
362 panic();
363 }
364
365 if (lcs == LCS_SE)
366 mmio_clrbits_32(P_ARMREG_SEC_CTRL, P_ARMREG_SEC_CTRL_PROT);
367
368 rcar_swdt_release();
369 bl2_system_cpg_init();
370
371 /* Disable data cache (clean and invalidate) */
372 disable_mmu_el3();
373 #if RCAR_BL2_DCACHE == 1
374 dcsw_op_all(DCCISW);
375 #endif
376 tlbialle3();
377 disable_mmu_icache_el3();
378 plat_invalidate_icache();
379 dsbsy();
380 isb();
381 }
382
is_ddr_backup_mode(void)383 static uint32_t is_ddr_backup_mode(void)
384 {
385 #if RCAR_SYSTEM_SUSPEND
386 static uint32_t reason = RCAR_COLD_BOOT;
387 static uint32_t once;
388
389 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
390 uint8_t data;
391 #endif
392 if (once)
393 return reason;
394
395 once = 1;
396 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0)
397 return reason;
398
399 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
400 if (rcar_iic_dvfs_receive(PMIC, REG_KEEP10, &data)) {
401 ERROR("BL2: REG Keep10 READ ERROR.\n");
402 panic();
403 }
404
405 if (KEEP10_MAGIC != data)
406 reason = RCAR_WARM_BOOT;
407 #else
408 reason = RCAR_WARM_BOOT;
409 #endif
410 return reason;
411 #else
412 return RCAR_COLD_BOOT;
413 #endif
414 }
415
416 #if RCAR_GEN3_BL33_GZIP == 1
bl2_plat_preload_setup(void)417 void bl2_plat_preload_setup(void)
418 {
419 image_decompress_init(BL33_COMP_BASE, BL33_COMP_SIZE, gunzip);
420 }
421 #endif
422
check_secure_load_area(uintptr_t base,uint32_t size,uintptr_t dest,uint32_t len)423 static uint64_t check_secure_load_area(uintptr_t base, uint32_t size,
424 uintptr_t dest, uint32_t len)
425 {
426 uintptr_t free_end, requested_end;
427
428 /*
429 * Handle corner cases first.
430 *
431 * The order of the 2 tests is important, because if there's no space
432 * left (i.e. free_size == 0) but we don't ask for any memory
433 * (i.e. size == 0) then we should report that the memory is free.
434 */
435 if (len == 0U) {
436 WARN("BL2: load data size is zero\n");
437 return 0; /* A zero-byte region is always free */
438 }
439 if (size == 0U) {
440 goto err;
441 }
442
443 /*
444 * Check that the end addresses don't overflow.
445 * If they do, consider that this memory region is not free, as this
446 * is an invalid scenario.
447 */
448 if (check_uptr_overflow(base, size - 1U)) {
449 goto err;
450 }
451 free_end = base + (size - 1U);
452
453 if (check_uptr_overflow(dest, len - 1U)) {
454 goto err;
455 }
456 requested_end = dest + (len - 1U);
457
458 /*
459 * Finally, check that the requested memory region lies within the free
460 * region.
461 */
462 if ((dest < base) || (requested_end > free_end)) {
463 goto err;
464 }
465
466 return 0;
467
468 err:
469 ERROR("BL2: load data is outside the loadable area.\n");
470 ERROR("BL2: dst=0x%lx, len=%d(0x%x)\n", dest, len, len);
471 return 1;
472 }
473
rcar_get_dest_addr_from_cert(uint32_t certid,uintptr_t * dest,uint32_t * len)474 static uint64_t rcar_get_dest_addr_from_cert(uint32_t certid, uintptr_t *dest,
475 uint32_t *len)
476 {
477 uint32_t cert;
478 int ret;
479
480 ret = rcar_get_certificate(certid, &cert);
481 if (ret) {
482 ERROR("%s : cert file load error", __func__);
483 return 1;
484 }
485
486 rcar_read_certificate((uint64_t) cert, len, dest);
487
488 return 0;
489 }
490
bl2_plat_handle_pre_image_load(unsigned int image_id)491 int bl2_plat_handle_pre_image_load(unsigned int image_id)
492 {
493 u_register_t *boot_kind = (void *) BOOT_KIND_BASE;
494 bl_mem_params_node_t *bl_mem_params;
495 uintptr_t dev_handle;
496 uintptr_t image_spec;
497 uintptr_t dest;
498 uint32_t len;
499 uint64_t ui64_ret;
500 int iret;
501
502 bl_mem_params = get_bl_mem_params_node(image_id);
503 if (bl_mem_params == NULL) {
504 ERROR("BL2: Failed to get loading parameter.\n");
505 return 1;
506 }
507
508 switch (image_id) {
509 case BL31_IMAGE_ID:
510 if (is_ddr_backup_mode() == RCAR_COLD_BOOT) {
511 iret = plat_get_image_source(image_id, &dev_handle,
512 &image_spec);
513 if (iret != 0) {
514 return 1;
515 }
516
517 ui64_ret = rcar_get_dest_addr_from_cert(
518 SOC_FW_CONTENT_CERT_ID, &dest, &len);
519 if (ui64_ret != 0U) {
520 return 1;
521 }
522
523 ui64_ret = check_secure_load_area(
524 BL31_BASE, BL31_LIMIT - BL31_BASE,
525 dest, len);
526 if (ui64_ret != 0U) {
527 return 1;
528 }
529
530 *boot_kind = RCAR_COLD_BOOT;
531 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind));
532
533 bl_mem_params->image_info.image_base = dest;
534 bl_mem_params->image_info.image_size = len;
535 } else {
536 *boot_kind = RCAR_WARM_BOOT;
537 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind));
538
539 console_flush();
540 bl2_plat_flush_bl31_params();
541
542 /* will not return */
543 bl2_enter_bl31(&bl_mem_params->ep_info);
544 }
545
546 return 0;
547 #ifndef SPD_NONE
548 case BL32_IMAGE_ID:
549 ui64_ret = rcar_get_dest_addr_from_cert(
550 TRUSTED_OS_FW_CONTENT_CERT_ID, &dest, &len);
551 if (ui64_ret != 0U) {
552 return 1;
553 }
554
555 ui64_ret = check_secure_load_area(
556 BL32_BASE, BL32_LIMIT - BL32_BASE, dest, len);
557 if (ui64_ret != 0U) {
558 return 1;
559 }
560
561 bl_mem_params->image_info.image_base = dest;
562 bl_mem_params->image_info.image_size = len;
563
564 return 0;
565 #endif
566 case BL33_IMAGE_ID:
567 /* case of image_id == BL33_IMAGE_ID */
568 ui64_ret = rcar_get_dest_addr_from_cert(
569 NON_TRUSTED_FW_CONTENT_CERT_ID,
570 &dest, &len);
571
572 if (ui64_ret != 0U) {
573 return 1;
574 }
575
576 bl_mem_params->image_info.image_base = dest;
577 bl_mem_params->image_info.image_size = len;
578
579 #if RCAR_GEN3_BL33_GZIP == 1
580 image_decompress_prepare(&bl_mem_params->image_info);
581 #endif
582
583 return 0;
584 default:
585 return 1;
586 }
587
588 return 0;
589 }
590
bl2_plat_handle_post_image_load(unsigned int image_id)591 int bl2_plat_handle_post_image_load(unsigned int image_id)
592 {
593 static bl2_to_bl31_params_mem_t *params;
594 bl_mem_params_node_t *bl_mem_params;
595
596 if (!params) {
597 params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE;
598 memset((void *)PARAMS_BASE, 0, sizeof(*params));
599 }
600
601 bl_mem_params = get_bl_mem_params_node(image_id);
602 if (!bl_mem_params) {
603 ERROR("BL2: Failed to get loading parameter.\n");
604 return 1;
605 }
606
607 switch (image_id) {
608 case BL31_IMAGE_ID:
609 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base;
610 return 0;
611 case BL32_IMAGE_ID:
612 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base;
613 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info,
614 sizeof(entry_point_info_t));
615 return 0;
616 case BL33_IMAGE_ID:
617 #if RCAR_GEN3_BL33_GZIP == 1
618 int ret;
619 if ((mmio_read_32(BL33_COMP_BASE) & 0xffff) == 0x8b1f) {
620 /* decompress gzip-compressed image */
621 ret = image_decompress(&bl_mem_params->image_info);
622 if (ret != 0) {
623 return ret;
624 }
625 } else {
626 /* plain image, copy it in place */
627 memcpy((void *)BL33_BASE, (void *)BL33_COMP_BASE,
628 bl_mem_params->image_info.image_size);
629 }
630 #endif
631 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base;
632 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info,
633 sizeof(entry_point_info_t));
634 return 0;
635 default:
636 return 1;
637 }
638
639 return 0;
640 }
641
bl2_plat_sec_mem_layout(void)642 struct meminfo *bl2_plat_sec_mem_layout(void)
643 {
644 return &bl2_tzram_layout;
645 }
646
bl2_populate_compatible_string(void * dt)647 static void bl2_populate_compatible_string(void *dt)
648 {
649 uint32_t board_type;
650 uint32_t board_rev;
651 uint32_t reg;
652 int ret;
653
654 fdt_setprop_u32(dt, 0, "#address-cells", 2);
655 fdt_setprop_u32(dt, 0, "#size-cells", 2);
656
657 /* Populate compatible string */
658 rcar_get_board_type(&board_type, &board_rev);
659 switch (board_type) {
660 case BOARD_SALVATOR_X:
661 ret = fdt_setprop_string(dt, 0, "compatible",
662 "renesas,salvator-x");
663 break;
664 case BOARD_SALVATOR_XS:
665 ret = fdt_setprop_string(dt, 0, "compatible",
666 "renesas,salvator-xs");
667 break;
668 case BOARD_STARTER_KIT:
669 ret = fdt_setprop_string(dt, 0, "compatible",
670 "renesas,m3ulcb");
671 break;
672 case BOARD_STARTER_KIT_PRE:
673 ret = fdt_setprop_string(dt, 0, "compatible",
674 "renesas,h3ulcb");
675 break;
676 case BOARD_EAGLE:
677 ret = fdt_setprop_string(dt, 0, "compatible",
678 "renesas,eagle");
679 break;
680 case BOARD_EBISU:
681 case BOARD_EBISU_4D:
682 ret = fdt_setprop_string(dt, 0, "compatible",
683 "renesas,ebisu");
684 break;
685 case BOARD_DRAAK:
686 ret = fdt_setprop_string(dt, 0, "compatible",
687 "renesas,draak");
688 break;
689 default:
690 NOTICE("BL2: Cannot set compatible string, board unsupported\n");
691 panic();
692 }
693
694 if (ret < 0) {
695 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret);
696 panic();
697 }
698
699 reg = mmio_read_32(RCAR_PRR);
700 switch (reg & PRR_PRODUCT_MASK) {
701 case PRR_PRODUCT_H3:
702 ret = fdt_appendprop_string(dt, 0, "compatible",
703 "renesas,r8a7795");
704 break;
705 case PRR_PRODUCT_M3:
706 ret = fdt_appendprop_string(dt, 0, "compatible",
707 "renesas,r8a7796");
708 break;
709 case PRR_PRODUCT_M3N:
710 ret = fdt_appendprop_string(dt, 0, "compatible",
711 "renesas,r8a77965");
712 break;
713 case PRR_PRODUCT_V3M:
714 ret = fdt_appendprop_string(dt, 0, "compatible",
715 "renesas,r8a77970");
716 break;
717 case PRR_PRODUCT_E3:
718 ret = fdt_appendprop_string(dt, 0, "compatible",
719 "renesas,r8a77990");
720 break;
721 case PRR_PRODUCT_D3:
722 ret = fdt_appendprop_string(dt, 0, "compatible",
723 "renesas,r8a77995");
724 break;
725 default:
726 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n");
727 panic();
728 }
729
730 if (ret < 0) {
731 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret);
732 panic();
733 }
734 }
735
bl2_add_rpc_node(void)736 static void bl2_add_rpc_node(void)
737 {
738 #if (RCAR_RPC_HYPERFLASH_LOCKED == 0)
739 int ret, node;
740
741 node = ret = fdt_add_subnode(fdt, 0, "soc");
742 if (ret < 0) {
743 goto err;
744 }
745
746 node = ret = fdt_add_subnode(fdt, node, "spi@ee200000");
747 if (ret < 0) {
748 goto err;
749 }
750
751 ret = fdt_setprop_string(fdt, node, "status", "okay");
752 if (ret < 0) {
753 goto err;
754 }
755
756 return;
757 err:
758 NOTICE("BL2: Cannot add RPC node to FDT (ret=%i)\n", ret);
759 panic();
760 #endif
761 }
762
bl2_add_kaslr_seed(void)763 static void bl2_add_kaslr_seed(void)
764 {
765 uint32_t cnt, isr, prr;
766 uint64_t seed;
767 int ret, node;
768
769 /* SCEG is only available on H3/M3-W/M3-N */
770 prr = mmio_read_32(RCAR_PRR);
771 switch (prr & PRR_PRODUCT_MASK) {
772 case PRR_PRODUCT_H3:
773 case PRR_PRODUCT_M3:
774 case PRR_PRODUCT_M3N:
775 break;
776 default:
777 return;
778 }
779
780 mmio_write_32(RCAR_CC63_BASE + CC63_TRNG_SW_RESET_REG_ADDR,
781 CC63_TRNG_SW_RESET_REG_SET);
782
783 do {
784 mmio_write_32(RCAR_CC63_BASE + CC63_TRNG_CLK_ENABLE_REG_ADDR,
785 CC63_TRNG_CLK_ENABLE_REG_SET);
786 mmio_write_32(RCAR_CC63_BASE + CC63_TRNG_SAMPLE_CNT1_REG_ADDR,
787 CC63_TRNG_SAMPLE_CNT1_REG_SAMPLE_COUNT);
788 cnt = mmio_read_32(RCAR_CC63_BASE + CC63_TRNG_SAMPLE_CNT1_REG_ADDR);
789 } while (cnt != CC63_TRNG_SAMPLE_CNT1_REG_SAMPLE_COUNT);
790
791 mmio_write_32(RCAR_CC63_BASE + CC63_TRNG_CONFIG_REG_ADDR,
792 CC63_TRNG_CONFIG_REG_ROSC_MAX_LENGTH);
793 mmio_write_32(RCAR_CC63_BASE + CC63_TRNG_DEBUG_CONTROL_REG_ADDR,
794 CC63_TRNG_DEBUG_CONTROL_REG_80090B);
795 mmio_write_32(RCAR_CC63_BASE + CC63_TRNG_SOURCE_ENABLE_REG_ADDR,
796 CC63_TRNG_SOURCE_ENABLE_REG_SET);
797
798 do {
799 isr = mmio_read_32(RCAR_CC63_BASE + CC63_TRNG_ISR_REG_ADDR);
800 if ((isr & CC63_TRNG_ISR_REG_AUTOCORR_ERR) != 0U) {
801 panic();
802 }
803 } while ((isr & CC63_TRNG_ISR_REG_EHR_VALID) == 0U);
804
805 mmio_write_32(RCAR_CC63_BASE + CC63_TRNG_ICR_REG_ADDR, UINT32_MAX);
806 seed = mmio_read_64(RCAR_CC63_BASE + CC63_TRNG_EHR_DATA_ADDR_0_REG_ADDR);
807 mmio_write_32(RCAR_CC63_BASE + CC63_TRNG_SOURCE_ENABLE_REG_ADDR,
808 CC63_TRNG_SOURCE_ENABLE_REG_CLR);
809
810 node = ret = fdt_add_subnode(fdt, 0, "chosen");
811 if (ret < 0) {
812 goto err;
813 }
814
815 ret = fdt_setprop_u64(fdt, node, "kaslr-seed", seed);
816 if (ret < 0) {
817 goto err;
818 }
819
820 return;
821 err:
822 NOTICE("BL2: Cannot add KASLR seed to FDT (ret=%i)\n", ret);
823 panic();
824 }
825
bl2_add_dram_entry(uint64_t start,uint64_t size)826 static void bl2_add_dram_entry(uint64_t start, uint64_t size)
827 {
828 char nodename[32] = { 0 };
829 uint64_t fdtsize;
830 int ret, node;
831
832 fdtsize = cpu_to_fdt64(size);
833
834 snprintf(nodename, sizeof(nodename), "memory@");
835 unsigned_num_print(start, 16, nodename + strlen(nodename));
836 node = ret = fdt_add_subnode(fdt, 0, nodename);
837 if (ret < 0) {
838 goto err;
839 }
840
841 ret = fdt_setprop_string(fdt, node, "device_type", "memory");
842 if (ret < 0) {
843 goto err;
844 }
845
846 ret = fdt_setprop_u64(fdt, node, "reg", start);
847 if (ret < 0) {
848 goto err;
849 }
850
851 ret = fdt_appendprop(fdt, node, "reg", &fdtsize,
852 sizeof(fdtsize));
853 if (ret < 0) {
854 goto err;
855 }
856
857 return;
858 err:
859 NOTICE("BL2: Cannot add memory node [%" PRIx64 " - %" PRIx64 "] to FDT (ret=%i)\n",
860 start, start + size - 1, ret);
861 panic();
862 }
863
bl2_advertise_dram_entries(uint64_t dram_config[8])864 static void bl2_advertise_dram_entries(uint64_t dram_config[8])
865 {
866 uint64_t start, size, size32;
867 int chan;
868
869 for (chan = 0; chan < 4; chan++) {
870 start = dram_config[2 * chan];
871 size = dram_config[2 * chan + 1];
872 if (!size)
873 continue;
874
875 NOTICE("BL2: CH%d: %" PRIx64 " - %" PRIx64 ", %" PRId64 " %siB\n",
876 chan, start, start + size - 1,
877 (size >> 30) ? : size >> 20,
878 (size >> 30) ? "G" : "M");
879 }
880
881 /*
882 * We add the DT nodes in reverse order here. The fdt_add_subnode()
883 * adds the DT node before the first existing DT node, so we have
884 * to add them in reverse order to get nodes sorted by address in
885 * the resulting DT.
886 */
887 for (chan = 3; chan >= 0; chan--) {
888 start = dram_config[2 * chan];
889 size = dram_config[2 * chan + 1];
890 if (!size)
891 continue;
892
893 /*
894 * Channel 0 is mapped in 32bit space and the first
895 * 128 MiB are reserved and the maximum size is 2GiB.
896 */
897 if (chan == 0) {
898 /* Limit the 32bit entry to 2 GiB - 128 MiB */
899 size32 = size - 0x8000000U;
900 if (size32 >= 0x78000000U) {
901 size32 = 0x78000000U;
902 }
903
904 /* Emit 32bit entry, up to 2 GiB - 128 MiB long. */
905 bl2_add_dram_entry(0x48000000, size32);
906
907 /*
908 * If channel 0 is less than 2 GiB long, the
909 * entire memory fits into the 32bit space entry,
910 * so move on to the next channel.
911 */
912 if (size <= 0x80000000U) {
913 continue;
914 }
915
916 /*
917 * If channel 0 is more than 2 GiB long, emit
918 * another entry which covers the rest of the
919 * memory in channel 0, in the 64bit space.
920 *
921 * Start of this new entry is at 2 GiB offset
922 * from the beginning of the 64bit channel 0
923 * address, size is 2 GiB shorter than total
924 * size of the channel.
925 */
926 start += 0x80000000U;
927 size -= 0x80000000U;
928 }
929
930 bl2_add_dram_entry(start, size);
931 }
932 }
933
bl2_advertise_dram_size(uint32_t product)934 static void bl2_advertise_dram_size(uint32_t product)
935 {
936 uint64_t dram_config[8] = {
937 [0] = 0x400000000ULL,
938 [2] = 0x500000000ULL,
939 [4] = 0x600000000ULL,
940 [6] = 0x700000000ULL,
941 };
942 uint32_t cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
943
944 switch (product) {
945 case PRR_PRODUCT_H3:
946 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0)
947 /* 4GB(1GBx4) */
948 dram_config[1] = 0x40000000ULL;
949 dram_config[3] = 0x40000000ULL;
950 dram_config[5] = 0x40000000ULL;
951 dram_config[7] = 0x40000000ULL;
952 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \
953 (RCAR_DRAM_CHANNEL == 5) && \
954 (RCAR_DRAM_SPLIT == 2)
955 /* 4GB(2GBx2 2ch split) */
956 dram_config[1] = 0x80000000ULL;
957 dram_config[3] = 0x80000000ULL;
958 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15)
959 /* 8GB(2GBx4: default) */
960 dram_config[1] = 0x80000000ULL;
961 dram_config[3] = 0x80000000ULL;
962 dram_config[5] = 0x80000000ULL;
963 dram_config[7] = 0x80000000ULL;
964 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */
965 break;
966
967 case PRR_PRODUCT_M3:
968 if (cut < PRR_PRODUCT_30) {
969 #if (RCAR_GEN3_ULCB == 1)
970 /* 2GB(1GBx2 2ch split) */
971 dram_config[1] = 0x40000000ULL;
972 dram_config[5] = 0x40000000ULL;
973 #else
974 /* 4GB(2GBx2 2ch split) */
975 dram_config[1] = 0x80000000ULL;
976 dram_config[5] = 0x80000000ULL;
977 #endif
978 } else {
979 /* 8GB(2GBx4 2ch split) */
980 dram_config[1] = 0x100000000ULL;
981 dram_config[5] = 0x100000000ULL;
982 }
983 break;
984
985 case PRR_PRODUCT_M3N:
986 #if (RCAR_DRAM_LPDDR4_MEMCONF == 2)
987 /* 4GB(4GBx1) */
988 dram_config[1] = 0x100000000ULL;
989 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1)
990 /* 2GB(1GBx2) */
991 dram_config[1] = 0x80000000ULL;
992 #endif
993 break;
994
995 case PRR_PRODUCT_V3M:
996 /* 1GB(512MBx2) */
997 dram_config[1] = 0x40000000ULL;
998 break;
999
1000 case PRR_PRODUCT_E3:
1001 #if (RCAR_DRAM_DDR3L_MEMCONF == 0)
1002 /* 1GB(512MBx2) */
1003 dram_config[1] = 0x40000000ULL;
1004 #elif (RCAR_DRAM_DDR3L_MEMCONF == 1)
1005 /* 2GB(512MBx4) */
1006 dram_config[1] = 0x80000000ULL;
1007 #elif (RCAR_DRAM_DDR3L_MEMCONF == 2)
1008 /* 4GB(1GBx4) */
1009 dram_config[1] = 0x100000000ULL;
1010 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */
1011 break;
1012
1013 case PRR_PRODUCT_D3:
1014 /* 512MB */
1015 dram_config[1] = 0x20000000ULL;
1016 break;
1017 }
1018
1019 bl2_advertise_dram_entries(dram_config);
1020 }
1021
bl2_el3_early_platform_setup(u_register_t arg1,u_register_t arg2,u_register_t arg3,u_register_t arg4)1022 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
1023 u_register_t arg3, u_register_t arg4)
1024 {
1025 uint32_t reg, midr, lcs, boot_dev, boot_cpu, sscg, type, rev;
1026 uint32_t product, product_cut, major, minor;
1027 int32_t ret;
1028 const char *str;
1029 const char *unknown = "unknown";
1030 const char *cpu_ca57 = "CA57";
1031 const char *cpu_ca53 = "CA53";
1032 const char *product_m3n = "M3N";
1033 const char *product_h3 = "H3";
1034 const char *product_m3 = "M3";
1035 const char *product_e3 = "E3";
1036 const char *product_d3 = "D3";
1037 const char *product_v3m = "V3M";
1038 const char *lcs_secure = "SE";
1039 const char *lcs_cm = "CM";
1040 const char *lcs_dm = "DM";
1041 const char *lcs_sd = "SD";
1042 const char *lcs_fa = "FA";
1043 const char *sscg_off = "PLL1 nonSSCG Clock select";
1044 const char *sscg_on = "PLL1 SSCG Clock select";
1045 const char *boot_hyper80 = "HyperFlash(80MHz)";
1046 const char *boot_qspi40 = "QSPI Flash(40MHz)";
1047 const char *boot_qspi80 = "QSPI Flash(80MHz)";
1048 const char *boot_emmc25x1 = "eMMC(25MHz x1)";
1049 const char *boot_emmc50x8 = "eMMC(50MHz x8)";
1050 #if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
1051 const char *boot_hyper160 = "HyperFlash(150MHz)";
1052 #else
1053 const char *boot_hyper160 = "HyperFlash(160MHz)";
1054 #endif
1055
1056 bl2_init_generic_timer();
1057
1058 reg = mmio_read_32(RCAR_MODEMR);
1059 boot_dev = reg & MODEMR_BOOT_DEV_MASK;
1060 boot_cpu = reg & MODEMR_BOOT_CPU_MASK;
1061
1062 bl2_cpg_init();
1063
1064 if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
1065 boot_cpu == MODEMR_BOOT_CPU_CA53) {
1066 rcar_pfc_init();
1067 rcar_console_boot_init();
1068 }
1069
1070 plat_rcar_gic_driver_init();
1071 plat_rcar_gic_init();
1072 rcar_swdt_init();
1073
1074 /* FIQ interrupts are taken to EL3 */
1075 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT);
1076
1077 write_daifclr(DAIF_FIQ_BIT);
1078
1079 reg = read_midr();
1080 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT);
1081 switch (midr) {
1082 case MIDR_CA57:
1083 str = cpu_ca57;
1084 break;
1085 case MIDR_CA53:
1086 str = cpu_ca53;
1087 break;
1088 default:
1089 str = unknown;
1090 break;
1091 }
1092
1093 NOTICE("BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n", str,
1094 version_of_renesas);
1095
1096 reg = mmio_read_32(RCAR_PRR);
1097 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
1098 product = reg & PRR_PRODUCT_MASK;
1099
1100 switch (product) {
1101 case PRR_PRODUCT_H3:
1102 str = product_h3;
1103 break;
1104 case PRR_PRODUCT_M3:
1105 str = product_m3;
1106 break;
1107 case PRR_PRODUCT_M3N:
1108 str = product_m3n;
1109 break;
1110 case PRR_PRODUCT_V3M:
1111 str = product_v3m;
1112 break;
1113 case PRR_PRODUCT_E3:
1114 str = product_e3;
1115 break;
1116 case PRR_PRODUCT_D3:
1117 str = product_d3;
1118 break;
1119 default:
1120 str = unknown;
1121 break;
1122 }
1123
1124 if ((PRR_PRODUCT_M3 == product) &&
1125 (PRR_PRODUCT_20 == (reg & RCAR_MAJOR_MASK))) {
1126 if (RCAR_M3_CUT_VER11 == (reg & PRR_CUT_MASK)) {
1127 /* M3 Ver.1.1 or Ver.1.2 */
1128 NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n",
1129 str);
1130 } else {
1131 NOTICE("BL2: PRR is R-Car %s Ver.1.%d\n",
1132 str,
1133 (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET);
1134 }
1135 } else if (product == PRR_PRODUCT_D3) {
1136 if (RCAR_D3_CUT_VER10 == (reg & PRR_CUT_MASK)) {
1137 NOTICE("BL2: PRR is R-Car %s Ver.1.0\n", str);
1138 } else if (RCAR_D3_CUT_VER11 == (reg & PRR_CUT_MASK)) {
1139 NOTICE("BL2: PRR is R-Car %s Ver.1.1\n", str);
1140 } else {
1141 NOTICE("BL2: PRR is R-Car %s Ver.X.X\n", str);
1142 }
1143 } else {
1144 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT;
1145 major = major + RCAR_MAJOR_OFFSET;
1146 minor = reg & RCAR_MINOR_MASK;
1147 NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor);
1148 }
1149
1150 if (PRR_PRODUCT_E3 == product || PRR_PRODUCT_D3 == product) {
1151 reg = mmio_read_32(RCAR_MODEMR);
1152 sscg = reg & RCAR_SSCG_MASK;
1153 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off;
1154 NOTICE("BL2: %s\n", str);
1155 }
1156
1157 rcar_get_board_type(&type, &rev);
1158
1159 switch (type) {
1160 case BOARD_SALVATOR_X:
1161 case BOARD_KRIEK:
1162 case BOARD_STARTER_KIT:
1163 case BOARD_SALVATOR_XS:
1164 case BOARD_EBISU:
1165 case BOARD_STARTER_KIT_PRE:
1166 case BOARD_EBISU_4D:
1167 case BOARD_DRAAK:
1168 case BOARD_EAGLE:
1169 break;
1170 default:
1171 type = BOARD_UNKNOWN;
1172 break;
1173 }
1174
1175 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN)
1176 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type));
1177 else {
1178 NOTICE("BL2: Board is %s Rev.%d.%d\n",
1179 GET_BOARD_NAME(type),
1180 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev));
1181 }
1182
1183 #if RCAR_LSI != RCAR_AUTO
1184 if (product != TARGET_PRODUCT) {
1185 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME);
1186 ERROR("BL2: Please write the correct IPL to flash memory.\n");
1187 panic();
1188 }
1189 #endif
1190 rcar_avs_init();
1191 rcar_avs_setting();
1192
1193 switch (boot_dev) {
1194 case MODEMR_BOOT_DEV_HYPERFLASH160:
1195 str = boot_hyper160;
1196 break;
1197 case MODEMR_BOOT_DEV_HYPERFLASH80:
1198 str = boot_hyper80;
1199 break;
1200 case MODEMR_BOOT_DEV_QSPI_FLASH40:
1201 str = boot_qspi40;
1202 break;
1203 case MODEMR_BOOT_DEV_QSPI_FLASH80:
1204 str = boot_qspi80;
1205 break;
1206 case MODEMR_BOOT_DEV_EMMC_25X1:
1207 #if RCAR_LSI == RCAR_D3
1208 ERROR("BL2: Failed to Initialize. eMMC is not supported.\n");
1209 panic();
1210 #endif
1211 str = boot_emmc25x1;
1212 break;
1213 case MODEMR_BOOT_DEV_EMMC_50X8:
1214 str = boot_emmc50x8;
1215 break;
1216 default:
1217 str = unknown;
1218 break;
1219 }
1220 NOTICE("BL2: Boot device is %s\n", str);
1221
1222 rcar_avs_setting();
1223 reg = rcar_rom_get_lcs(&lcs);
1224 if (reg) {
1225 str = unknown;
1226 goto lcm_state;
1227 }
1228
1229 switch (lcs) {
1230 case LCS_CM:
1231 str = lcs_cm;
1232 break;
1233 case LCS_DM:
1234 str = lcs_dm;
1235 break;
1236 case LCS_SD:
1237 str = lcs_sd;
1238 break;
1239 case LCS_SE:
1240 str = lcs_secure;
1241 break;
1242 case LCS_FA:
1243 str = lcs_fa;
1244 break;
1245 default:
1246 str = unknown;
1247 break;
1248 }
1249
1250 lcm_state:
1251 NOTICE("BL2: LCM state is %s\n", str);
1252
1253 rcar_avs_end();
1254 is_ddr_backup_mode();
1255
1256 bl2_tzram_layout.total_base = BL31_BASE;
1257 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE;
1258
1259 if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
1260 boot_cpu == MODEMR_BOOT_CPU_CA53) {
1261 ret = rcar_dram_init();
1262 if (ret) {
1263 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret);
1264 panic();
1265 }
1266 rcar_qos_init();
1267 }
1268
1269 /* Set up FDT */
1270 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob));
1271 if (ret) {
1272 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret);
1273 panic();
1274 }
1275
1276 /* Add platform compatible string */
1277 bl2_populate_compatible_string(fdt);
1278
1279 /* Enable RPC if unlocked */
1280 bl2_add_rpc_node();
1281
1282 /* Print DRAM layout */
1283 bl2_advertise_dram_size(product);
1284
1285 /* Add KASLR seed */
1286 bl2_add_kaslr_seed();
1287
1288 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
1289 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) {
1290 if (rcar_emmc_init() != EMMC_SUCCESS) {
1291 NOTICE("BL2: Failed to eMMC driver initialize.\n");
1292 panic();
1293 }
1294 rcar_emmc_memcard_power(EMMC_POWER_ON);
1295 if (rcar_emmc_mount() != EMMC_SUCCESS) {
1296 NOTICE("BL2: Failed to eMMC mount operation.\n");
1297 panic();
1298 }
1299 } else {
1300 rcar_rpc_init();
1301 rcar_dma_init();
1302 }
1303
1304 reg = mmio_read_32(RST_WDTRSTCR);
1305 reg &= ~WDTRSTCR_RWDT_RSTMSK;
1306 reg |= WDTRSTCR_PASSWORD;
1307 mmio_write_32(RST_WDTRSTCR, reg);
1308
1309 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD);
1310 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD);
1311
1312 reg = mmio_read_32(RCAR_PRR);
1313 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57)
1314 mmio_write_32(CPG_CA57DBGRCR,
1315 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR));
1316
1317 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53)
1318 mmio_write_32(CPG_CA53DBGRCR,
1319 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR));
1320
1321 if (product_cut == PRR_PRODUCT_H3_CUT10) {
1322 reg = mmio_read_32(CPG_PLL2CR);
1323 reg &= ~((uint32_t) 1 << 5);
1324 mmio_write_32(CPG_PLL2CR, reg);
1325
1326 reg = mmio_read_32(CPG_PLL4CR);
1327 reg &= ~((uint32_t) 1 << 5);
1328 mmio_write_32(CPG_PLL4CR, reg);
1329
1330 reg = mmio_read_32(CPG_PLL0CR);
1331 reg &= ~((uint32_t) 1 << 12);
1332 mmio_write_32(CPG_PLL0CR, reg);
1333 }
1334
1335 bl2_create_fcnl_reserved_memory();
1336
1337 fdt_pack(fdt);
1338 NOTICE("BL2: FDT at %p\n", fdt);
1339
1340 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
1341 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8)
1342 rcar_io_emmc_setup();
1343 else
1344 rcar_io_setup();
1345 }
1346
bl2_el3_plat_arch_setup(void)1347 void bl2_el3_plat_arch_setup(void)
1348 {
1349 rcar_configure_mmu_el3(BL2_BASE,
1350 BL2_END - BL2_BASE,
1351 BL2_RO_BASE, BL2_RO_LIMIT
1352 #if USE_COHERENT_MEM
1353 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT
1354 #endif
1355 );
1356 }
1357
bl2_el3_plat_prepare_exit(void)1358 void bl2_el3_plat_prepare_exit(void)
1359 {
1360 bl2_ram_security_setting_finish();
1361 }
1362
bl2_platform_setup(void)1363 void bl2_platform_setup(void)
1364 {
1365
1366 }
1367
bl2_init_generic_timer(void)1368 static void bl2_init_generic_timer(void)
1369 {
1370 /* FIXME: V3M 16.666 MHz ? */
1371 #if RCAR_LSI == RCAR_D3
1372 uint32_t reg_cntfid = EXTAL_DRAAK;
1373 #elif RCAR_LSI == RCAR_E3
1374 uint32_t reg_cntfid = EXTAL_EBISU;
1375 #else /* RCAR_LSI == RCAR_E3 */
1376 uint32_t reg;
1377 uint32_t reg_cntfid;
1378 uint32_t modemr;
1379 uint32_t modemr_pll;
1380 uint32_t board_type;
1381 uint32_t board_rev;
1382 uint32_t pll_table[] = {
1383 EXTAL_MD14_MD13_TYPE_0, /* MD14/MD13 : 0b00 */
1384 EXTAL_MD14_MD13_TYPE_1, /* MD14/MD13 : 0b01 */
1385 EXTAL_MD14_MD13_TYPE_2, /* MD14/MD13 : 0b10 */
1386 EXTAL_MD14_MD13_TYPE_3 /* MD14/MD13 : 0b11 */
1387 };
1388
1389 modemr = mmio_read_32(RCAR_MODEMR);
1390 modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK);
1391
1392 /* Set frequency data in CNTFID0 */
1393 reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT];
1394 reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
1395 switch (modemr_pll) {
1396 case MD14_MD13_TYPE_0:
1397 rcar_get_board_type(&board_type, &board_rev);
1398 if (BOARD_SALVATOR_XS == board_type) {
1399 reg_cntfid = EXTAL_SALVATOR_XS;
1400 }
1401 break;
1402 case MD14_MD13_TYPE_3:
1403 if (PRR_PRODUCT_H3_CUT10 == reg) {
1404 reg_cntfid = reg_cntfid >> 1U;
1405 }
1406 break;
1407 default:
1408 /* none */
1409 break;
1410 }
1411 #endif /* RCAR_LSI == RCAR_E3 */
1412 /* Update memory mapped and register based frequency */
1413 write_cntfrq_el0((u_register_t )reg_cntfid);
1414 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid);
1415 /* Enable counter */
1416 mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF,
1417 (uint32_t)CNTCR_EN);
1418 }
1419