1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2016-2017 Micron Technology, Inc.
4 *
5 * Authors:
6 * Peter Pan <peterpandong@micron.com>
7 */
8 #ifndef __LINUX_MTD_SPINAND_H
9 #define __LINUX_MTD_SPINAND_H
10
11 #ifndef __UBOOT__
12 #include <linux/mutex.h>
13 #include <linux/bitops.h>
14 #include <linux/device.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/nand.h>
17 #include <linux/spi/spi.h>
18 #include <linux/spi/spi-mem.h>
19 #else
20 #include <common.h>
21 #include <spi.h>
22 #include <spi-mem.h>
23 #include <linux/mtd/nand.h>
24 #endif
25
26 /**
27 * Standard SPI NAND flash operations
28 */
29
30 #define SPINAND_RESET_OP \
31 SPI_MEM_OP(SPI_MEM_OP_CMD(0xff, 1), \
32 SPI_MEM_OP_NO_ADDR, \
33 SPI_MEM_OP_NO_DUMMY, \
34 SPI_MEM_OP_NO_DATA)
35
36 #define SPINAND_WR_EN_DIS_OP(enable) \
37 SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1), \
38 SPI_MEM_OP_NO_ADDR, \
39 SPI_MEM_OP_NO_DUMMY, \
40 SPI_MEM_OP_NO_DATA)
41
42 #define SPINAND_READID_OP(naddr, ndummy, buf, len) \
43 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \
44 SPI_MEM_OP_ADDR(naddr, 0, 1), \
45 SPI_MEM_OP_DUMMY(ndummy, 1), \
46 SPI_MEM_OP_DATA_IN(len, buf, 1))
47
48 #define SPINAND_SET_FEATURE_OP(reg, valptr) \
49 SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1), \
50 SPI_MEM_OP_ADDR(1, reg, 1), \
51 SPI_MEM_OP_NO_DUMMY, \
52 SPI_MEM_OP_DATA_OUT(1, valptr, 1))
53
54 #define SPINAND_GET_FEATURE_OP(reg, valptr) \
55 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0f, 1), \
56 SPI_MEM_OP_ADDR(1, reg, 1), \
57 SPI_MEM_OP_NO_DUMMY, \
58 SPI_MEM_OP_DATA_IN(1, valptr, 1))
59
60 #define SPINAND_BLK_ERASE_OP(addr) \
61 SPI_MEM_OP(SPI_MEM_OP_CMD(0xd8, 1), \
62 SPI_MEM_OP_ADDR(3, addr, 1), \
63 SPI_MEM_OP_NO_DUMMY, \
64 SPI_MEM_OP_NO_DATA)
65
66 #define SPINAND_PAGE_READ_OP(addr) \
67 SPI_MEM_OP(SPI_MEM_OP_CMD(0x13, 1), \
68 SPI_MEM_OP_ADDR(3, addr, 1), \
69 SPI_MEM_OP_NO_DUMMY, \
70 SPI_MEM_OP_NO_DATA)
71
72 #define SPINAND_PAGE_READ_FROM_CACHE_OP(fast, addr, ndummy, buf, len) \
73 SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1), \
74 SPI_MEM_OP_ADDR(2, addr, 1), \
75 SPI_MEM_OP_DUMMY(ndummy, 1), \
76 SPI_MEM_OP_DATA_IN(len, buf, 1))
77
78 #define SPINAND_PAGE_READ_FROM_CACHE_OP_3A(fast, addr, ndummy, buf, len) \
79 SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1), \
80 SPI_MEM_OP_ADDR(3, addr, 1), \
81 SPI_MEM_OP_DUMMY(ndummy, 1), \
82 SPI_MEM_OP_DATA_IN(len, buf, 1))
83
84 #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(addr, ndummy, buf, len) \
85 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
86 SPI_MEM_OP_ADDR(2, addr, 1), \
87 SPI_MEM_OP_DUMMY(ndummy, 1), \
88 SPI_MEM_OP_DATA_IN(len, buf, 2))
89
90 #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(addr, ndummy, buf, len) \
91 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
92 SPI_MEM_OP_ADDR(3, addr, 1), \
93 SPI_MEM_OP_DUMMY(ndummy, 1), \
94 SPI_MEM_OP_DATA_IN(len, buf, 2))
95
96 #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(addr, ndummy, buf, len) \
97 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
98 SPI_MEM_OP_ADDR(2, addr, 1), \
99 SPI_MEM_OP_DUMMY(ndummy, 1), \
100 SPI_MEM_OP_DATA_IN(len, buf, 4))
101
102 #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(addr, ndummy, buf, len) \
103 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
104 SPI_MEM_OP_ADDR(3, addr, 1), \
105 SPI_MEM_OP_DUMMY(ndummy, 1), \
106 SPI_MEM_OP_DATA_IN(len, buf, 4))
107
108 #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(addr, ndummy, buf, len) \
109 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \
110 SPI_MEM_OP_ADDR(2, addr, 2), \
111 SPI_MEM_OP_DUMMY(ndummy, 2), \
112 SPI_MEM_OP_DATA_IN(len, buf, 2))
113
114 #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP_3A(addr, ndummy, buf, len) \
115 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \
116 SPI_MEM_OP_ADDR(3, addr, 2), \
117 SPI_MEM_OP_DUMMY(ndummy, 2), \
118 SPI_MEM_OP_DATA_IN(len, buf, 2))
119
120 #define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(addr, ndummy, buf, len) \
121 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \
122 SPI_MEM_OP_ADDR(2, addr, 4), \
123 SPI_MEM_OP_DUMMY(ndummy, 4), \
124 SPI_MEM_OP_DATA_IN(len, buf, 4))
125
126 #define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP_3A(addr, ndummy, buf, len) \
127 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \
128 SPI_MEM_OP_ADDR(3, addr, 4), \
129 SPI_MEM_OP_DUMMY(ndummy, 4), \
130 SPI_MEM_OP_DATA_IN(len, buf, 4))
131
132 #define SPINAND_PROG_EXEC_OP(addr) \
133 SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), \
134 SPI_MEM_OP_ADDR(3, addr, 1), \
135 SPI_MEM_OP_NO_DUMMY, \
136 SPI_MEM_OP_NO_DATA)
137
138 #define SPINAND_PROG_LOAD(reset, addr, buf, len) \
139 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x02 : 0x84, 1), \
140 SPI_MEM_OP_ADDR(2, addr, 1), \
141 SPI_MEM_OP_NO_DUMMY, \
142 SPI_MEM_OP_DATA_OUT(len, buf, 1))
143
144 #define SPINAND_PROG_LOAD_X4(reset, addr, buf, len) \
145 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x32 : 0x34, 1), \
146 SPI_MEM_OP_ADDR(2, addr, 1), \
147 SPI_MEM_OP_NO_DUMMY, \
148 SPI_MEM_OP_DATA_OUT(len, buf, 4))
149
150 /**
151 * Standard SPI NAND flash commands
152 */
153 #define SPINAND_CMD_PROG_LOAD_X4 0x32
154 #define SPINAND_CMD_PROG_LOAD_RDM_DATA_X4 0x34
155
156 /* feature register */
157 #define REG_BLOCK_LOCK 0xa0
158 #define BL_ALL_UNLOCKED 0x00
159 #define HWP_EN 0x02 /* Skyhigh feature, Hardware write protection */
160
161 /* configuration register */
162 #define REG_CFG 0xb0
163 #define CFG_OTP_ENABLE BIT(6)
164 #define CFG_ECC_ENABLE BIT(4)
165 #define CFG_BUF_ENABLE BIT(3)
166 #define CFG_QUAD_ENABLE BIT(0)
167
168 /* status register */
169 #define REG_STATUS 0xc0
170 #define STATUS_BUSY BIT(0)
171 #define STATUS_ERASE_FAILED BIT(2)
172 #define STATUS_PROG_FAILED BIT(3)
173 #define STATUS_ECC_MASK GENMASK(5, 4)
174 #define STATUS_ECC_NO_BITFLIPS (0 << 4)
175 #define STATUS_ECC_HAS_BITFLIPS (1 << 4)
176 #define STATUS_ECC_UNCOR_ERROR (2 << 4)
177
178 struct spinand_op;
179 struct spinand_device;
180
181 #define SPINAND_MAX_ID_LEN 4
182
183 /**
184 * struct spinand_id - SPI NAND id structure
185 * @data: buffer containing the id bytes. Currently 4 bytes large, but can
186 * be extended if required
187 * @len: ID length
188 */
189 struct spinand_id {
190 u8 data[SPINAND_MAX_ID_LEN];
191 int len;
192 };
193
194 enum spinand_readid_method {
195 SPINAND_READID_METHOD_OPCODE,
196 SPINAND_READID_METHOD_OPCODE_ADDR,
197 SPINAND_READID_METHOD_OPCODE_DUMMY,
198 };
199
200 /**
201 * struct spinand_devid - SPI NAND device id structure
202 * @id: device id of current chip
203 * @len: number of bytes in device id
204 * @method: method to read chip id
205 * There are 3 possible variants:
206 * SPINAND_READID_METHOD_OPCODE: chip id is returned immediately
207 * after read_id opcode.
208 * SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after
209 * read_id opcode + 1-byte address.
210 * SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after
211 * read_id opcode + 1 dummy byte.
212 */
213 struct spinand_devid {
214 const u8 *id;
215 const u8 len;
216 const enum spinand_readid_method method;
217 };
218
219 /**
220 * struct manufacurer_ops - SPI NAND manufacturer specific operations
221 * @init: initialize a SPI NAND device
222 * @cleanup: cleanup a SPI NAND device
223 *
224 * Each SPI NAND manufacturer driver should implement this interface so that
225 * NAND chips coming from this vendor can be initialized properly.
226 */
227 struct spinand_manufacturer_ops {
228 int (*init)(struct spinand_device *spinand);
229 void (*cleanup)(struct spinand_device *spinand);
230 };
231
232 /**
233 * struct spinand_manufacturer - SPI NAND manufacturer instance
234 * @id: manufacturer ID
235 * @name: manufacturer name
236 * @devid_len: number of bytes in device ID
237 * @chips: supported SPI NANDs under current manufacturer
238 * @nchips: number of SPI NANDs available in chips array
239 * @ops: manufacturer operations
240 */
241 struct spinand_manufacturer {
242 u8 id;
243 char *name;
244 const struct spinand_info *chips;
245 const size_t nchips;
246 const struct spinand_manufacturer_ops *ops;
247 };
248
249 /* SPI NAND manufacturers */
250 extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
251 extern const struct spinand_manufacturer macronix_spinand_manufacturer;
252 extern const struct spinand_manufacturer micron_spinand_manufacturer;
253 extern const struct spinand_manufacturer toshiba_spinand_manufacturer;
254 extern const struct spinand_manufacturer winbond_spinand_manufacturer;
255 extern const struct spinand_manufacturer dosilicon_spinand_manufacturer;
256 extern const struct spinand_manufacturer esmt_spinand_manufacturer;
257 extern const struct spinand_manufacturer xincun_spinand_manufacturer;
258 extern const struct spinand_manufacturer xtx_spinand_manufacturer;
259 extern const struct spinand_manufacturer hyf_spinand_manufacturer;
260 extern const struct spinand_manufacturer fmsh_spinand_manufacturer;
261 extern const struct spinand_manufacturer foresee_spinand_manufacturer;
262 extern const struct spinand_manufacturer biwin_spinand_manufacturer;
263 extern const struct spinand_manufacturer etron_spinand_manufacturer;
264 extern const struct spinand_manufacturer jsc_spinand_manufacturer;
265 extern const struct spinand_manufacturer silicongo_spinand_manufacturer;
266 extern const struct spinand_manufacturer unim_spinand_manufacturer;
267 extern const struct spinand_manufacturer unim_zl_spinand_manufacturer;
268 extern const struct spinand_manufacturer skyhigh_spinand_manufacturer;
269 extern const struct spinand_manufacturer gsto_spinand_manufacturer;
270 extern const struct spinand_manufacturer zbit_spinand_manufacturer;
271 extern const struct spinand_manufacturer hiksemi_spinand_manufacturer;
272 extern const struct spinand_manufacturer kingston_spinand_manufacturer;
273
274 /**
275 * struct spinand_op_variants - SPI NAND operation variants
276 * @ops: the list of variants for a given operation
277 * @nops: the number of variants
278 *
279 * Some operations like read-from-cache/write-to-cache have several variants
280 * depending on the number of IO lines you use to transfer data or address
281 * cycles. This structure is a way to describe the different variants supported
282 * by a chip and let the core pick the best one based on the SPI mem controller
283 * capabilities.
284 */
285 struct spinand_op_variants {
286 const struct spi_mem_op *ops;
287 unsigned int nops;
288 };
289
290 #define SPINAND_OP_VARIANTS(name, ...) \
291 const struct spinand_op_variants name = { \
292 .ops = (struct spi_mem_op[]) { __VA_ARGS__ }, \
293 .nops = sizeof((struct spi_mem_op[]){ __VA_ARGS__ }) / \
294 sizeof(struct spi_mem_op), \
295 }
296
297 /**
298 * spinand_ecc_info - description of the on-die ECC implemented by a SPI NAND
299 * chip
300 * @get_status: get the ECC status. Should return a positive number encoding
301 * the number of corrected bitflips if correction was possible or
302 * -EBADMSG if there are uncorrectable errors. I can also return
303 * other negative error codes if the error is not caused by
304 * uncorrectable bitflips
305 * @ooblayout: the OOB layout used by the on-die ECC implementation
306 */
307 struct spinand_ecc_info {
308 int (*get_status)(struct spinand_device *spinand, u8 status);
309 const struct mtd_ooblayout_ops *ooblayout;
310 };
311
312 #define SPINAND_HAS_QE_BIT BIT(0)
313
314 /**
315 * struct spinand_info - Structure used to describe SPI NAND chips
316 * @model: model name
317 * @devid: device ID
318 * @flags: OR-ing of the SPINAND_XXX flags
319 * @memorg: memory organization
320 * @eccreq: ECC requirements
321 * @eccinfo: on-die ECC info
322 * @op_variants: operations variants
323 * @op_variants.read_cache: variants of the read-cache operation
324 * @op_variants.write_cache: variants of the write-cache operation
325 * @op_variants.update_cache: variants of the update-cache operation
326 * @select_target: function used to select a target/die. Required only for
327 * multi-die chips
328 *
329 * Each SPI NAND manufacturer driver should have a spinand_info table
330 * describing all the chips supported by the driver.
331 */
332 struct spinand_info {
333 const char *model;
334 struct spinand_devid devid;
335 u32 flags;
336 struct nand_memory_organization memorg;
337 struct nand_ecc_req eccreq;
338 struct spinand_ecc_info eccinfo;
339 struct {
340 const struct spinand_op_variants *read_cache;
341 const struct spinand_op_variants *write_cache;
342 const struct spinand_op_variants *update_cache;
343 } op_variants;
344 int (*select_target)(struct spinand_device *spinand,
345 unsigned int target);
346 };
347
348 #define SPINAND_ID(__method, ...) \
349 { \
350 .id = (const u8[]){ __VA_ARGS__ }, \
351 .len = sizeof((u8[]){ __VA_ARGS__ }), \
352 .method = __method, \
353 }
354
355 #define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \
356 { \
357 .read_cache = __read, \
358 .write_cache = __write, \
359 .update_cache = __update, \
360 }
361
362 #define SPINAND_ECCINFO(__ooblayout, __get_status) \
363 .eccinfo = { \
364 .ooblayout = __ooblayout, \
365 .get_status = __get_status, \
366 }
367
368 #define SPINAND_SELECT_TARGET(__func) \
369 .select_target = __func,
370
371 #define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants, \
372 __flags, ...) \
373 { \
374 .model = __model, \
375 .devid = __id, \
376 .memorg = __memorg, \
377 .eccreq = __eccreq, \
378 .op_variants = __op_variants, \
379 .flags = __flags, \
380 __VA_ARGS__ \
381 }
382
383 /**
384 * struct spinand_device - SPI NAND device instance
385 * @base: NAND device instance
386 * @slave: pointer to the SPI slave object
387 * @lock: lock used to serialize accesses to the NAND
388 * @id: NAND ID as returned by READ_ID
389 * @flags: NAND flags
390 * @op_templates: various SPI mem op templates
391 * @op_templates.read_cache: read cache op template
392 * @op_templates.write_cache: write cache op template
393 * @op_templates.update_cache: update cache op template
394 * @select_target: select a specific target/die. Usually called before sending
395 * a command addressing a page or an eraseblock embedded in
396 * this die. Only required if your chip exposes several dies
397 * @cur_target: currently selected target/die
398 * @eccinfo: on-die ECC information
399 * @cfg_cache: config register cache. One entry per die
400 * @databuf: bounce buffer for data
401 * @oobbuf: bounce buffer for OOB data
402 * @scratchbuf: buffer used for everything but page accesses. This is needed
403 * because the spi-mem interface explicitly requests that buffers
404 * passed in spi_mem_op be DMA-able, so we can't based the bufs on
405 * the stack
406 * @manufacturer: SPI NAND manufacturer information
407 * @priv: manufacturer private data
408 */
409 struct spinand_device {
410 struct nand_device base;
411 #ifndef __UBOOT__
412 struct spi_mem *spimem;
413 struct mutex lock;
414 #else
415 struct spi_slave *slave;
416 #endif
417 struct spinand_id id;
418 u32 flags;
419
420 struct {
421 const struct spi_mem_op *read_cache;
422 const struct spi_mem_op *write_cache;
423 const struct spi_mem_op *update_cache;
424 } op_templates;
425
426 int (*select_target)(struct spinand_device *spinand,
427 unsigned int target);
428 unsigned int cur_target;
429
430 struct spinand_ecc_info eccinfo;
431
432 u8 *cfg_cache;
433 u8 *databuf;
434 u8 *oobbuf;
435 u8 *scratchbuf;
436 const struct spinand_manufacturer *manufacturer;
437 void *priv;
438 bool support_cont_read;
439 };
440
441 /**
442 * mtd_to_spinand() - Get the SPI NAND device attached to an MTD instance
443 * @mtd: MTD instance
444 *
445 * Return: the SPI NAND device attached to @mtd.
446 */
mtd_to_spinand(struct mtd_info * mtd)447 static inline struct spinand_device *mtd_to_spinand(struct mtd_info *mtd)
448 {
449 return container_of(mtd_to_nanddev(mtd), struct spinand_device, base);
450 }
451
452 /**
453 * spinand_to_mtd() - Get the MTD device embedded in a SPI NAND device
454 * @spinand: SPI NAND device
455 *
456 * Return: the MTD device embedded in @spinand.
457 */
spinand_to_mtd(struct spinand_device * spinand)458 static inline struct mtd_info *spinand_to_mtd(struct spinand_device *spinand)
459 {
460 return nanddev_to_mtd(&spinand->base);
461 }
462
463 /**
464 * nand_to_spinand() - Get the SPI NAND device embedding an NAND object
465 * @nand: NAND object
466 *
467 * Return: the SPI NAND device embedding @nand.
468 */
nand_to_spinand(struct nand_device * nand)469 static inline struct spinand_device *nand_to_spinand(struct nand_device *nand)
470 {
471 return container_of(nand, struct spinand_device, base);
472 }
473
474 /**
475 * spinand_to_nand() - Get the NAND device embedded in a SPI NAND object
476 * @spinand: SPI NAND device
477 *
478 * Return: the NAND device embedded in @spinand.
479 */
480 static inline struct nand_device *
spinand_to_nand(struct spinand_device * spinand)481 spinand_to_nand(struct spinand_device *spinand)
482 {
483 return &spinand->base;
484 }
485
486 /**
487 * spinand_set_of_node - Attach a DT node to a SPI NAND device
488 * @spinand: SPI NAND device
489 * @np: DT node
490 *
491 * Attach a DT node to a SPI NAND device.
492 */
spinand_set_of_node(struct spinand_device * spinand,const struct device_node * np)493 static inline void spinand_set_of_node(struct spinand_device *spinand,
494 const struct device_node *np)
495 {
496 nanddev_set_of_node(&spinand->base, np);
497 }
498
499 int spinand_match_and_init(struct spinand_device *spinand,
500 const struct spinand_info *table,
501 unsigned int table_size,
502 enum spinand_readid_method rdid_method);
503
504 int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val);
505 int spinand_select_target(struct spinand_device *spinand, unsigned int target);
506
507 #endif /* __LINUX_MTD_SPINAND_H */
508