1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 4 * 5 */ 6 7 #ifndef __CONFIG_RK3568_COMMON_H 8 #define __CONFIG_RK3568_COMMON_H 9 10 #define CFG_CPUID_OFFSET 0xa 11 12 #include "rockchip-common.h" 13 14 #define CONFIG_SPL_FRAMEWORK 15 #define CONFIG_SPL_TEXT_BASE 0x00000000 16 #define CONFIG_SPL_MAX_SIZE 0x00040000 17 #define CONFIG_SPL_BSS_START_ADDR 0x03fe0000 18 #define CONFIG_SPL_BSS_MAX_SIZE 0x00010000 19 #define CONFIG_SPL_STACK 0x03fe0000 20 #ifdef CONFIG_SPL_LOAD_FIT_ADDRESS 21 #undef CONFIG_SPL_LOAD_FIT_ADDRESS 22 #endif 23 #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x10000000 24 25 #define CONFIG_SYS_MALLOC_LEN (32 << 20) 26 #define CONFIG_SYS_CBSIZE 1024 27 #define CONFIG_SKIP_LOWLEVEL_INIT 28 29 #ifdef CONFIG_SUPPORT_USBPLUG 30 #define CONFIG_SYS_TEXT_BASE 0x00000000 31 #else 32 #define CONFIG_SYS_TEXT_BASE 0x00a00000 33 #endif 34 35 #define CONFIG_SYS_INIT_SP_ADDR 0x00c00000 36 #define CONFIG_SYS_LOAD_ADDR 0x00c00800 37 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 38 #define COUNTER_FREQUENCY 24000000 39 40 #define GICD_BASE 0xfd400000 41 #define GICR_BASE 0xfd460000 42 #define GICC_BASE 0xfd800000 43 44 /* secure otp */ 45 #define OTP_UBOOT_ROLLBACK_OFFSET 0xe0 46 #define OTP_UBOOT_ROLLBACK_WORDS 2 /* 64 bits, 2 words */ 47 #define OTP_ALL_ONES_NUM_BITS 32 48 #define OTP_SECURE_BOOT_ENABLE_ADDR 0x80 49 #define OTP_SECURE_BOOT_ENABLE_SIZE 2 50 #ifdef CONFIG_FIT_ENABLE_RSA4096_SUPPORT 51 #define OTP_SECURE_BOOT_ENABLE_VALUE 0x30ff 52 #endif 53 #define OTP_RSA_HASH_ADDR 0x90 54 #define OTP_RSA_HASH_SIZE 32 55 56 /* MMC/SD IP block */ 57 #define CONFIG_BOUNCE_BUFFER 58 #ifdef CONFIG_AHCI 59 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 60 #define CONFIG_SYS_SCSI_MAX_LUN 1 61 /*#define CONFIG_SCSI_AHCI_PLAT */ 62 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 63 CONFIG_SYS_SCSI_MAX_LUN) 64 #endif 65 /* Nand */ 66 #define CONFIG_SYS_NAND_BASE 0xFE330000 67 #define CONFIG_SYS_MAX_NAND_DEVICE 1 68 #define CONFIG_SYS_NAND_ONFI_DETECTION 69 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 70 #define CONFIG_SYS_NAND_PAGE_COUNT 64 71 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 72 73 #define CONFIG_SYS_SDRAM_BASE 0 74 #define SDRAM_MAX_SIZE 0xf0000000 75 #define CONFIG_PREBOOT 76 77 #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ 78 79 #ifndef CONFIG_SPL_BUILD 80 /* usb mass storage */ 81 #define CONFIG_USB_FUNCTION_MASS_STORAGE 82 #define CONFIG_ROCKUSB_G_DNL_PID 0x350a 83 #define ROCKUSB_FSG_BUFLEN 0x400000 84 85 #define ENV_MEM_LAYOUT_SETTINGS \ 86 "scriptaddr=0x00c00000\0" \ 87 "pxefile_addr_r=0x00e00000\0" \ 88 "fdt_addr_r=0x08300000\0" \ 89 "kernel_addr_r=0x00280000\0" \ 90 "kernel_addr_c=0x04080000\0" \ 91 "ramdisk_addr_r=0x0a200000\0" 92 93 #include <config_distro_bootcmd.h> 94 95 #define CONFIG_EXTRA_ENV_SETTINGS \ 96 ENV_MEM_LAYOUT_SETTINGS \ 97 "partitions=" PARTS_RKIMG \ 98 ROCKCHIP_DEVICE_SETTINGS \ 99 RKIMG_DET_BOOTDEV \ 100 BOOTENV 101 #endif 102 103 /* rockchip ohci host driver */ 104 #define CONFIG_USB_OHCI_NEW 105 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 106 107 #define CONFIG_LIB_HW_RAND 108 109 #endif 110