1 /* 2 * Copyright (c) 2025-2026, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP2_RISAF_H 8 #define STM32MP2_RISAF_H 9 10 #include <stdint.h> 11 12 #include <lib/utils_def.h> 13 14 /* RISAF general registers (base relative) */ 15 #define _RISAF_CR U(0x00) 16 #define _RISAF_SR U(0x04) 17 #define _RISAF_KEYR U(0x30) 18 #define _RISAF_HWCFGR U(0xFF0) 19 20 /* RISAF general register field description */ 21 /* _RISAF_CR register fields */ 22 #define _RISAF_CR_GLOCK BIT_32(0) 23 /* _RISAF_SR register fields */ 24 #define _RISAF_SR_KEYVALID BIT_32(0) 25 #define _RISAF_SR_KEYRDY BIT_32(1) 26 #define _RISAF_SR_ENCDIS BIT_32(2) 27 /* _RISAF_HWCFGR register fields */ 28 #define _RISAF_HWCFGR_CFG1_SHIFT 0 29 #define _RISAF_HWCFGR_CFG1_MASK GENMASK_32(7, 0) 30 #define _RISAF_HWCFGR_CFG2_SHIFT 8 31 #define _RISAF_HWCFGR_CFG2_MASK GENMASK_32(15, 8) 32 #define _RISAF_HWCFGR_CFG3_SHIFT 16 33 #define _RISAF_HWCFGR_CFG3_MASK GENMASK_32(23, 16) 34 #define _RISAF_HWCFGR_CFG4_SHIFT 24 35 #define _RISAF_HWCFGR_CFG4_MASK GENMASK_32(31, 24) 36 37 /* RISAF region registers (base relative) */ 38 #define _RISAF_REG_BASE U(0x40) 39 #define _RISAF_REG_SIZE U(0x40) 40 #define _RISAF_REG(n) (_RISAF_REG_BASE + (((n) - 1) * _RISAF_REG_SIZE)) 41 #define _RISAF_REG_CFGR_OFFSET U(0x0) 42 #define _RISAF_REG_CFGR(n) (_RISAF_REG(n) + _RISAF_REG_CFGR_OFFSET) 43 #define _RISAF_REG_STARTR_OFFSET U(0x4) 44 #define _RISAF_REG_STARTR(n) (_RISAF_REG(n) + _RISAF_REG_STARTR_OFFSET) 45 #define _RISAF_REG_ENDR_OFFSET U(0x8) 46 #define _RISAF_REG_ENDR(n) (_RISAF_REG(n) + _RISAF_REG_ENDR_OFFSET) 47 #define _RISAF_REG_CIDCFGR_OFFSET U(0xC) 48 #define _RISAF_REG_CIDCFGR(n) (_RISAF_REG(n) + _RISAF_REG_CIDCFGR_OFFSET) 49 50 /* RISAF region register field description */ 51 /* _RISAF_REG_CFGR(n) register fields */ 52 #define _RISAF_REG_CFGR_BREN_SHIFT 0 53 #define _RISAF_REG_CFGR_BREN BIT_32(_RISAF_REG_CFGR_BREN_SHIFT) 54 #define _RISAF_REG_CFGR_SEC_SHIFT 8 55 #define _RISAF_REG_CFGR_SEC BIT_32(_RISAF_REG_CFGR_SEC_SHIFT) 56 #if STM32MP21 57 #define _RISAF_REG_CFGR_ENC_SHIFT 14 58 #define _RISAF_REG_CFGR_ENC GENMASK_32(15, _RISAF_REG_CFGR_ENC_SHIFT) 59 #else /* STM32MP21 */ 60 #define _RISAF_REG_CFGR_ENC_SHIFT 15 61 #define _RISAF_REG_CFGR_ENC BIT_32(_RISAF_REG_CFGR_ENC_SHIFT) 62 #endif /* STM32MP21 */ 63 #define _RISAF_REG_CFGR_PRIVC_SHIFT 16 64 #define _RISAF_REG_CFGR_PRIVC_MASK GENMASK_32(23, 16) 65 #define _RISAF_REG_CFGR_ALL_MASK (_RISAF_REG_CFGR_BREN | _RISAF_REG_CFGR_SEC | \ 66 _RISAF_REG_CFGR_ENC | _RISAF_REG_CFGR_PRIVC_MASK) 67 /* _RISAF_REG_CIDCFGR(n) register fields */ 68 #define _RISAF_REG_CIDCFGR_RDENC_SHIFT 0 69 #define _RISAF_REG_CIDCFGR_RDENC_MASK GENMASK_32(7, 0) 70 #define _RISAF_REG_CIDCFGR_WRENC_SHIFT 16 71 #define _RISAF_REG_CIDCFGR_WRENC_MASK GENMASK_32(23, 16) 72 #define _RISAF_REG_CIDCFGR_ALL_MASK (_RISAF_REG_CIDCFGR_RDENC_MASK | \ 73 _RISAF_REG_CIDCFGR_WRENC_MASK) 74 75 #if STM32MP21 76 /* RISAF MCE extension registers */ 77 #define _RISAF_XCR U(0x1C00) 78 #define _RISAF_XSR U(0x1C04) 79 #define _RISAF_MKEYR U(0x1E00) 80 81 /* RISAF MCE extension register field description */ 82 /* _RISAF_XCR register fields */ 83 #define _RISAF_XCR_XLOCK BIT(0) 84 #define _RISAF_XCR_MKLOCK BIT(0) 85 #define _RISAF_XCR_CIPHERSEL_SHIFT 4 86 #define _RISAF_XCR_CIPHERSEL_MASK GENMASK_32(5, _RISAF_XCR_CIPHERSEL_SHIFT) 87 #define _RISAF_XCR_CIPHERSEL_AES128 1 88 #define _RISAF_XCR_CIPHERSEL_AES256 3 89 /* _RISAF_XSR register fields */ 90 #define _RISAF_XSR_MKVALID BIT(0) 91 #endif /* STM32MP21 */ 92 93 /* Device Tree related definitions */ 94 #define DT_RISAF_COMPAT "st,stm32-risaf" 95 #define DT_RISAF_REG_ID_MASK U(0xF) 96 #define DT_RISAF_EN_SHIFT 4 97 #define DT_RISAF_EN_MASK BIT_32(DT_RISAF_EN_SHIFT) 98 #define DT_RISAF_SEC_SHIFT 5 99 #define DT_RISAF_SEC_MASK BIT_32(DT_RISAF_SEC_SHIFT) 100 #define DT_RISAF_ENC_SHIFT 6 101 #define DT_RISAF_ENC_MASK GENMASK_32(7, DT_RISAF_ENC_SHIFT) 102 #define DT_RISAF_PRIV_SHIFT 8 103 #define DT_RISAF_PRIV_MASK GENMASK_32(15, DT_RISAF_PRIV_SHIFT) 104 #define DT_RISAF_READ_SHIFT 16 105 #define DT_RISAF_READ_MASK GENMASK_32(23, DT_RISAF_READ_SHIFT) 106 #define DT_RISAF_WRITE_SHIFT 24 107 #define DT_RISAF_WRITE_MASK GENMASK_32(31, DT_RISAF_WRITE_SHIFT) 108 109 /* RISAF max properties */ 110 #define RISAF_REGION_REG_SIZE (4 * sizeof(uint32_t)) 111 #define RISAF_REGION_PROTREG_SIZE (1 * sizeof(uint32_t)) 112 #define RISAF_TIMEOUT_1MS_IN_US U(1000) 113 114 /* RISAF key sizes in bytes */ 115 #if STM32MP21 116 #define RISAF_MCE_KEY_128BITS_SIZE_IN_BYTES U(16) 117 #define RISAF_MCE_KEY_256BITS_SIZE_IN_BYTES U(32) 118 #endif /* STM32MP21 */ 119 #define RISAF_ENCRYPTION_KEY_SIZE_IN_BYTES U(16) 120 121 struct stm32mp2_risaf_region { 122 int instance; 123 uint32_t cfg; 124 uintptr_t addr; 125 size_t len; 126 }; 127 128 struct stm32mp2_risaf_platdata { 129 uintptr_t *base; 130 unsigned long *clock; 131 uint32_t *granularity; 132 struct stm32mp2_risaf_region *region; 133 int nregions; 134 }; 135 136 int stm32mp2_risaf_write_encryption_key(int instance, uint8_t *key); 137 #if STM32MP21 138 int stm32mp2_risaf_write_mce_key(int instance, uint8_t *key); 139 #endif /* STM32MP21 */ 140 int stm32mp2_risaf_lock(int instance); 141 int stm32mp2_risaf_is_locked(int instance, bool *state); 142 int stm32mp2_risaf_init(void); 143 144 #endif /* STM32MP2_RISAF_H */ 145