1 /* 2 * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLATFORM_DEF_H 10 #define PLATFORM_DEF_H 11 12 #include <arch.h> 13 #include <drivers/arm/gic_common.h> 14 #include <plat_common.h> 15 #include "versal_net_def.h" 16 17 /******************************************************************************* 18 * Generic platform constants 19 ******************************************************************************/ 20 21 /* Size of cacheable stacks */ 22 #define PLATFORM_STACK_SIZE U(0x440) 23 24 #define PLATFORM_CLUSTER_COUNT U(4) 25 #define PLATFORM_CORE_COUNT_PER_CLUSTER U(4) /* 4 CPUs per cluster */ 26 27 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * PLATFORM_CORE_COUNT_PER_CLUSTER) 28 29 #define E_INVALID_CORE_COUNT -1 30 #define E_INVALID_CLUSTER_COUNT -3 31 32 #define PLAT_MAX_PWR_LVL U(2) 33 #define PLAT_MAX_RET_STATE U(1) 34 #define PLAT_MAX_OFF_STATE U(2) 35 36 /******************************************************************************* 37 * BL31 specific defines. 38 ******************************************************************************/ 39 /* 40 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 41 * present). BL31_BASE is calculated using the current BL31 debug size plus a 42 * little space for growth. 43 */ 44 #ifndef VERSAL_NET_ATF_MEM_BASE 45 # define BL31_BASE U(0xBBF00000) 46 # define BL31_LIMIT U(0xBC000000) 47 #else 48 # define BL31_BASE U(VERSAL_NET_ATF_MEM_BASE) 49 # define BL31_LIMIT U(VERSAL_NET_ATF_MEM_BASE + VERSAL_NET_ATF_MEM_SIZE) 50 # ifdef VERSAL_NET_ATF_MEM_PROGBITS_SIZE 51 # define BL31_PROGBITS_LIMIT U(VERSAL_NET_ATF_MEM_BASE + \ 52 VERSAL_NET_ATF_MEM_PROGBITS_SIZE) 53 # endif 54 #endif 55 56 /******************************************************************************* 57 * BL32 specific defines. 58 ******************************************************************************/ 59 #ifndef VERSAL_NET_BL32_MEM_BASE 60 # define BL32_BASE U(0x60000000) 61 # define BL32_LIMIT U(0x80000000) 62 #else 63 # define BL32_BASE U(VERSAL_NET_BL32_MEM_BASE) 64 # define BL32_LIMIT U(VERSAL_NET_BL32_MEM_BASE + VERSAL_NET_BL32_MEM_SIZE) 65 #endif 66 67 /******************************************************************************* 68 * BL33 specific defines. 69 ******************************************************************************/ 70 #ifndef PRELOADED_BL33_BASE 71 # define PLAT_ARM_NS_IMAGE_BASE U(0x8000000) 72 #else 73 # define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE) 74 #endif 75 76 /******************************************************************************* 77 * HIGH and LOW DDR MAX definitions 78 ******************************************************************************/ 79 #define PLAT_DDR_LOWMEM_MAX U(0x80000000) 80 #define PLAT_DDR_HIGHMEM_MAX U(0x100000000) 81 82 /******************************************************************************* 83 * TSP specific defines. 84 ******************************************************************************/ 85 #define TSP_SEC_MEM_BASE BL32_BASE 86 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE) 87 88 /* ID of the secure physical generic timer interrupt used by the TSP */ 89 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 90 91 /******************************************************************************* 92 * Platform specific page table and MMU setup constants 93 ******************************************************************************/ 94 95 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32U) 96 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32U) 97 98 #define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000) 99 100 #define PLAT_OCM_BASE U(0xBBF00000) 101 #define PLAT_OCM_LIMIT U(0xBC000000) 102 103 #define IS_TFA_IN_OCM(x) ((x >= PLAT_OCM_BASE) && (x < PLAT_OCM_LIMIT)) 104 105 #ifndef MAX_MMAP_REGIONS 106 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 107 #define MAX_MMAP_REGIONS 9 108 #else 109 #define MAX_MMAP_REGIONS 8 110 #endif 111 #endif 112 113 #ifndef MAX_XLAT_TABLES 114 #define MAX_XLAT_TABLES U(9) 115 #endif 116 117 #define CACHE_WRITEBACK_SHIFT U(6) 118 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 119 120 #define PLAT_ARM_GICD_BASE U(0xE2000000) 121 #define PLAT_ARM_GICR_BASE U(0xE2060000) 122 123 /* interrupt priorities when SDEI is enabled: 124 * RAS in future is planned to have highest priority (lower value 0x10) 125 * followed by IPI and SDEI exceptions in a step of 0x10. 126 */ 127 128 #if SDEI_SUPPORT 129 #define VERSAL_NET_SDEI_SGI_PRIVATE U(8) 130 #define PLAT_SDEI_CRITICAL_PRI 0x30 131 #define PLAT_SDEI_NORMAL_PRI 0x40 132 #define PLAT_PRI_BITS U(3) 133 #define PLAT_IPI_PRI 0x20 134 135 #define PLAT_EHF_DESC EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_IPI_PRI) 136 137 #define VERSAL_NET_SDEI_SH_EVENT_0 U(200) 138 #define VERSAL_NET_SDEI_PRV_EV U(201) 139 #endif 140 141 /* 142 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 143 * terminology. On a GICv2 system or mode, the lists will be merged and treated 144 * as Group 0 interrupts. 145 */ 146 #define PLAT_VERSAL_NET_IPI_IRQ 89 147 #define PLAT_VERSAL_IPI_IRQ PLAT_VERSAL_NET_IPI_IRQ 148 149 #if SDEI_SUPPORT 150 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 151 INTR_PROP_DESC(VERSAL_NET_IRQ_SEC_PHY_TIMER, PLAT_IPI_PRI, grp, \ 152 GIC_INTR_CFG_LEVEL) 153 154 #define PLAT_ARM_G0_IRQ_PROPS(grp) \ 155 INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, PLAT_IPI_PRI, grp, \ 156 GIC_INTR_CFG_EDGE), \ 157 INTR_PROP_DESC(CPU_PWR_DOWN_REQ_INTR, PLAT_IPI_PRI, grp, \ 158 GIC_INTR_CFG_EDGE), \ 159 INTR_PROP_DESC(VERSAL_NET_SDEI_SGI_PRIVATE, PLAT_SDEI_NORMAL_PRI, grp, \ 160 GIC_INTR_CFG_EDGE) 161 #else 162 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 163 INTR_PROP_DESC(VERSAL_NET_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 164 GIC_INTR_CFG_LEVEL) 165 166 #define PLAT_ARM_G0_IRQ_PROPS(grp) \ 167 INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \ 168 GIC_INTR_CFG_EDGE), \ 169 INTR_PROP_DESC(CPU_PWR_DOWN_REQ_INTR, GIC_HIGHEST_SEC_PRIORITY, grp, \ 170 GIC_INTR_CFG_EDGE) 171 #endif 172 173 #define IRQ_MAX 200U 174 175 #endif /* PLATFORM_DEF_H */ 176