1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2021 Fuzhou Rockchip Electronics Co., Ltd
4 * Author: Algea Cao <algea.cao@rock-chips.com>
5 */
6
7 #include <common.h>
8 #include <malloc.h>
9 #include <syscon.h>
10 #include <asm/arch-rockchip/clock.h>
11 #include <asm/arch/vendor.h>
12 #include <edid.h>
13 #include <dm/device.h>
14 #include <dm/of_access.h>
15 #include <dm/ofnode.h>
16 #include <dm/read.h>
17 #include <linux/hdmi.h>
18 #include <linux/media-bus-format.h>
19 #include <linux/dw_hdmi.h>
20 #include <asm/io.h>
21 #include "rockchip_bridge.h"
22 #include "rockchip_display.h"
23 #include "rockchip_crtc.h"
24 #include "rockchip_connector.h"
25 #include "dw_hdmi_qp.h"
26 #include "rockchip_phy.h"
27
28 enum frl_mask {
29 FRL_3GBPS_3LANE = 1,
30 FRL_6GBPS_3LANE,
31 FRL_6GBPS_4LANE,
32 FRL_8GBPS_4LANE,
33 FRL_10GBPS_4LANE,
34 FRL_12GBPS_4LANE,
35 };
36
37 #define DDC_CI_ADDR 0x37
38 #define DDC_SEGMENT_ADDR 0x30
39
40 #define HDMI_EDID_LEN 512
41 #define HDMI_EDID_BLOCK_LEN 128
42
43 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
44 #define SCDC_MIN_SOURCE_VERSION 0x1
45
46 #define HDMI14_MAX_TMDSCLK 340000000
47
48 struct hdmi_vmode {
49 bool mdataenablepolarity;
50
51 unsigned int mpixelclock;
52 unsigned int mpixelrepetitioninput;
53 unsigned int mpixelrepetitionoutput;
54 unsigned int mtmdsclock;
55 };
56
57 struct hdmi_data_info {
58 unsigned int enc_in_bus_format;
59 unsigned int enc_out_bus_format;
60 unsigned int enc_in_encoding;
61 unsigned int enc_out_encoding;
62 unsigned int quant_range;
63 unsigned int pix_repet_factor;
64 struct hdmi_vmode video_mode;
65 };
66
67 struct dw_hdmi_phy_data {
68 enum dw_hdmi_phy_type type;
69 const char *name;
70 unsigned int gen;
71 bool has_svsret;
72 int (*configure)(struct dw_hdmi *hdmi,
73 const struct dw_hdmi_plat_data *pdata,
74 unsigned long mpixelclock);
75 };
76
77 struct dw_hdmi_i2c {
78 u8 slave_reg;
79 bool is_regaddr;
80 bool is_segment;
81
82 unsigned int scl_high_ns;
83 unsigned int scl_low_ns;
84 };
85
86 struct dw_hdmi_qp {
87 enum dw_hdmi_devtype dev_type;
88 unsigned int version;
89 struct hdmi_data_info hdmi_data;
90 struct hdmi_edid_data edid_data;
91 const struct dw_hdmi_plat_data *plat_data;
92 struct ddc_adapter adap;
93
94 int vic;
95 int id;
96
97 unsigned long bus_format;
98 bool cable_plugin;
99 bool sink_is_hdmi;
100 bool sink_has_audio;
101 void *regs;
102 void *rk_hdmi;
103 struct dw_hdmi_i2c *i2c;
104
105 struct {
106 const struct dw_hdmi_qp_phy_ops *ops;
107 const char *name;
108 void *data;
109 bool enabled;
110 } phy;
111
112 struct drm_display_mode previous_mode;
113
114 unsigned int sample_rate;
115 unsigned int audio_cts;
116 unsigned int audio_n;
117 bool audio_enable;
118 bool scramble_low_rates;
119
120 void (*write)(struct dw_hdmi_qp *hdmi, u32 val, int offset);
121 u8 (*read)(struct dw_hdmi_qp *hdmi, int offset);
122
123 bool hdcp1x_enable;
124 bool output_bus_format_rgb;
125 };
126
hdmi_writel(struct dw_hdmi_qp * hdmi,u32 val,int offset)127 static inline void hdmi_writel(struct dw_hdmi_qp *hdmi, u32 val, int offset)
128 {
129 writel(val, hdmi->regs + offset);
130 }
131
hdmi_readl(struct dw_hdmi_qp * hdmi,int offset)132 static inline u32 hdmi_readl(struct dw_hdmi_qp *hdmi, int offset)
133 {
134 return readl(hdmi->regs + offset);
135 }
136
137 static void
hdmi_modb(struct dw_hdmi_qp * hdmi,u32 data,u32 mask,unsigned int reg)138 hdmi_modb(struct dw_hdmi_qp *hdmi, u32 data, u32 mask, unsigned int reg)
139 {
140 u32 val = hdmi_readl(hdmi, reg) & ~mask;
141
142 val |= data & mask;
143 hdmi_writel(hdmi, val, reg);
144 }
145
hdmi_bus_fmt_is_rgb(unsigned int bus_format)146 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
147 {
148 switch (bus_format) {
149 case MEDIA_BUS_FMT_RGB888_1X24:
150 case MEDIA_BUS_FMT_RGB101010_1X30:
151 case MEDIA_BUS_FMT_RGB121212_1X36:
152 case MEDIA_BUS_FMT_RGB161616_1X48:
153 return true;
154
155 default:
156 return false;
157 }
158 }
159
hdmi_bus_fmt_is_yuv444(unsigned int bus_format)160 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
161 {
162 switch (bus_format) {
163 case MEDIA_BUS_FMT_YUV8_1X24:
164 case MEDIA_BUS_FMT_YUV10_1X30:
165 case MEDIA_BUS_FMT_YUV12_1X36:
166 case MEDIA_BUS_FMT_YUV16_1X48:
167 return true;
168
169 default:
170 return false;
171 }
172 }
173
hdmi_bus_fmt_is_yuv422(unsigned int bus_format)174 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
175 {
176 switch (bus_format) {
177 case MEDIA_BUS_FMT_UYVY8_1X16:
178 case MEDIA_BUS_FMT_UYVY10_1X20:
179 case MEDIA_BUS_FMT_UYVY12_1X24:
180 case MEDIA_BUS_FMT_YUYV8_1X16:
181 case MEDIA_BUS_FMT_YUYV10_1X20:
182 case MEDIA_BUS_FMT_YUYV12_1X24:
183 return true;
184
185 default:
186 return false;
187 }
188 }
189
hdmi_bus_fmt_is_yuv420(unsigned int bus_format)190 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format)
191 {
192 switch (bus_format) {
193 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
194 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
195 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
196 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
197 return true;
198
199 default:
200 return false;
201 }
202 }
203
hdmi_bus_fmt_color_depth(unsigned int bus_format)204 static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
205 {
206 switch (bus_format) {
207 case MEDIA_BUS_FMT_RGB888_1X24:
208 case MEDIA_BUS_FMT_YUV8_1X24:
209 case MEDIA_BUS_FMT_UYVY8_1X16:
210 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
211 return 8;
212
213 case MEDIA_BUS_FMT_RGB101010_1X30:
214 case MEDIA_BUS_FMT_YUV10_1X30:
215 case MEDIA_BUS_FMT_UYVY10_1X20:
216 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
217 return 10;
218
219 case MEDIA_BUS_FMT_RGB121212_1X36:
220 case MEDIA_BUS_FMT_YUV12_1X36:
221 case MEDIA_BUS_FMT_UYVY12_1X24:
222 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
223 return 12;
224
225 case MEDIA_BUS_FMT_RGB161616_1X48:
226 case MEDIA_BUS_FMT_YUV16_1X48:
227 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
228 return 16;
229
230 default:
231 return 0;
232 }
233 }
234
drm_scdc_set_scrambling(struct ddc_adapter * adapter,bool enable)235 static bool drm_scdc_set_scrambling(struct ddc_adapter *adapter, bool enable)
236 {
237 u8 config;
238 int ret;
239
240 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
241 if (ret < 0) {
242 debug("Failed to read TMDS config: %d\n", ret);
243 return false;
244 }
245
246 if (enable)
247 config |= SCDC_SCRAMBLING_ENABLE;
248 else
249 config &= ~SCDC_SCRAMBLING_ENABLE;
250
251 ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config);
252 if (ret < 0) {
253 debug("Failed to enable scrambling: %d\n", ret);
254 return false;
255 }
256
257 return true;
258 }
259
260 static bool
drm_scdc_set_high_tmds_clock_ratio(struct ddc_adapter * adapter,bool set)261 drm_scdc_set_high_tmds_clock_ratio(struct ddc_adapter *adapter, bool set)
262 {
263 u8 config;
264 int ret;
265
266 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
267 if (ret < 0) {
268 debug("Failed to read TMDS config: %d\n", ret);
269 return false;
270 }
271
272 if (set)
273 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
274 else
275 config &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
276
277 ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config);
278 if (ret < 0) {
279 debug("Failed to set TMDS clock ratio: %d\n", ret);
280 return false;
281 }
282
283 /*
284 * The spec says that a source should wait minimum 1ms and maximum
285 * 100ms after writing the TMDS config for clock ratio. Lets allow a
286 * wait of up to 2ms here.
287 */
288 udelay(2000);
289 return true;
290 }
291
dw_hdmi_i2c_init(struct dw_hdmi_qp * hdmi)292 static void dw_hdmi_i2c_init(struct dw_hdmi_qp *hdmi)
293 {
294 /* Software reset */
295 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0);
296
297 hdmi_writel(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0);
298
299 hdmi_modb(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0);
300
301 /* Clear DONE and ERROR interrupts */
302 hdmi_writel(hdmi, I2CM_OP_DONE_CLEAR | I2CM_NACK_RCVD_CLEAR,
303 MAINUNIT_1_INT_CLEAR);
304 }
305
dw_hdmi_i2c_read(struct dw_hdmi_qp * hdmi,unsigned char * buf,unsigned int length)306 static int dw_hdmi_i2c_read(struct dw_hdmi_qp *hdmi,
307 unsigned char *buf, unsigned int length)
308 {
309 struct dw_hdmi_i2c *i2c = hdmi->i2c;
310 int i = 20, retry;
311 u32 intr = 0;
312 bool read_edid = false;
313
314 if (!i2c->is_regaddr) {
315 printf("set read register address to 0\n");
316 i2c->slave_reg = 0x00;
317 i2c->is_regaddr = true;
318 }
319
320 /* edid reads are in 128 bytes. scdc reads are in 1 byte */
321 if (length == HDMI_EDID_BLOCK_LEN)
322 read_edid = true;
323
324 while (length > 0) {
325 retry = 100;
326 hdmi_modb(hdmi, i2c->slave_reg << 12, I2CM_ADDR,
327 I2CM_INTERFACE_CONTROL0);
328
329 if (read_edid) {
330 hdmi_modb(hdmi, I2CM_16BYTES, I2CM_NBYTES_MASK,
331 I2CM_INTERFACE_CONTROL0);
332 i2c->slave_reg += 16;
333 length -= 16;
334 } else {
335 hdmi_modb(hdmi, I2CM_1BYTES, I2CM_NBYTES_MASK,
336 I2CM_INTERFACE_CONTROL0);
337 i2c->slave_reg++;
338 length--;
339 }
340
341 while (retry > 0) {
342 if (!hdmi->phy.ops->read_hpd(hdmi->rk_hdmi)) {
343 debug("hdmi disconnect, stop ddc read\n");
344 return -EPERM;
345 }
346
347 i = 20;
348 if (i2c->is_segment)
349 hdmi_modb(hdmi, I2CM_EXT_READ, I2CM_WR_MASK,
350 I2CM_INTERFACE_CONTROL0);
351 else
352 hdmi_modb(hdmi, I2CM_FM_READ, I2CM_WR_MASK,
353 I2CM_INTERFACE_CONTROL0);
354
355 while (i--) {
356 udelay(1000);
357 intr = hdmi_readl(hdmi, MAINUNIT_1_INT_STATUS);
358 intr &= (I2CM_OP_DONE_IRQ |
359 I2CM_READ_REQUEST_IRQ |
360 I2CM_NACK_RCVD_IRQ);
361 if (intr) {
362 hdmi_writel(hdmi, intr,
363 MAINUNIT_1_INT_CLEAR);
364 break;
365 }
366 }
367
368 if (!i) {
369 printf("i2c read time out!\n");
370 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0);
371 retry -= 10;
372 continue;
373 }
374
375 /* Check for error condition on the bus */
376 if (intr & I2CM_NACK_RCVD_IRQ) {
377 printf("i2c read err!\n");
378 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0);
379 retry--;
380 mdelay(10);
381 continue;
382 }
383
384 /* read success */
385 break;
386 }
387
388 if (retry <= 0) {
389 printf("ddc read failed offset:0x%x\n", i2c->slave_reg);
390 return -EIO;
391 }
392
393 if (read_edid) {
394 u8 reg_offset, val_offset, i;
395 u32 val, reg;
396
397 for (i = 0; i < 16; i++) {
398 reg_offset = i / 4;
399 val_offset = (i % 4) * 8;
400 reg = I2CM_INTERFACE_RDDATA_0_3 + 4 *
401 reg_offset;
402 val = hdmi_readl(hdmi, reg);
403 *buf++ = (val & (0xff << val_offset)) >>
404 val_offset;
405 debug("i2c read done! 0x%02x\n",
406 (val & (0xff << val_offset)) >>
407 val_offset);
408 }
409 } else {
410 *buf++ = hdmi_readl(hdmi, I2CM_INTERFACE_RDDATA_0_3) &
411 0xff;
412 debug("i2c read done! 0x%02x\n",
413 hdmi_readl(hdmi, I2CM_INTERFACE_RDDATA_0_3));
414 }
415
416 hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0);
417 }
418 i2c->is_segment = false;
419
420 return 0;
421 }
422
dw_hdmi_i2c_write(struct dw_hdmi_qp * hdmi,unsigned char * buf,unsigned int length)423 static int dw_hdmi_i2c_write(struct dw_hdmi_qp *hdmi,
424 unsigned char *buf, unsigned int length)
425 {
426 struct dw_hdmi_i2c *i2c = hdmi->i2c;
427 int i = 20, retry;
428 u32 intr = 0;
429
430 if (!i2c->is_regaddr) {
431 /* Use the first write byte as register address */
432 i2c->slave_reg = buf[0];
433 length--;
434 buf++;
435 i2c->is_regaddr = true;
436 }
437
438 while (length--) {
439 retry = 100;
440
441 while (retry > 0) {
442 if (!hdmi->phy.ops->read_hpd(hdmi->rk_hdmi)) {
443 debug("hdmi disconnect, stop ddc read\n");
444 return -EPERM;
445 }
446
447 i = 20;
448 hdmi_writel(hdmi, *buf++, I2CM_INTERFACE_WRDATA_0_3);
449 hdmi_modb(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR,
450 I2CM_INTERFACE_CONTROL0);
451 hdmi_modb(hdmi, I2CM_FM_WRITE, I2CM_WR_MASK,
452 I2CM_INTERFACE_CONTROL0);
453
454 while (i--) {
455 udelay(1000);
456 intr = hdmi_readl(hdmi, MAINUNIT_1_INT_STATUS);
457 intr &= (I2CM_OP_DONE_IRQ |
458 I2CM_READ_REQUEST_IRQ |
459 I2CM_NACK_RCVD_IRQ);
460 if (intr) {
461 hdmi_writel(hdmi, intr,
462 MAINUNIT_1_INT_CLEAR);
463 break;
464 }
465 }
466
467 if (!i) {
468 printf("i2c write time out!\n");
469 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0);
470 retry -= 10;
471 continue;
472 }
473
474 /* Check for error condition on the bus */
475 if (intr & I2CM_NACK_RCVD_IRQ) {
476 printf("i2c write nack!\n");
477 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0);
478 retry--;
479 mdelay(10);
480 continue;
481 }
482 /* write success */
483 break;
484 }
485 hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0);
486 if (retry <= 0) {
487 printf("ddc write failed\n");
488 return -EIO;
489 }
490 }
491
492 return 0;
493 }
494
dw_hdmi_i2c_xfer(struct ddc_adapter * adap,struct i2c_msg * msgs,int num)495 static int dw_hdmi_i2c_xfer(struct ddc_adapter *adap,
496 struct i2c_msg *msgs, int num)
497 {
498 struct dw_hdmi_qp *hdmi = container_of(adap, struct dw_hdmi_qp, adap);
499 struct dw_hdmi_i2c *i2c = hdmi->i2c;
500 u8 addr = msgs[0].addr;
501 int i, ret = 0;
502
503 debug("i2c xfer: num: %d, addr: %#x\n", num, addr);
504
505 for (i = 0; i < num; i++) {
506 if (msgs[i].len == 0) {
507 printf("unsupported transfer %d/%d, no data\n",
508 i + 1, num);
509 return -EOPNOTSUPP;
510 }
511 }
512
513 /* Unmute DONE and ERROR interrupts */
514 hdmi_modb(hdmi, I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N,
515 I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N,
516 MAINUNIT_1_INT_MASK_N);
517
518 /* Set slave device address taken from the first I2C message */
519 if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1)
520 addr = DDC_ADDR;
521
522 hdmi_modb(hdmi, addr << 5, I2CM_SLVADDR, I2CM_INTERFACE_CONTROL0);
523
524 /* Set slave device register address on transfer */
525 i2c->is_regaddr = false;
526
527 /* Set segment pointer for I2C extended read mode operation */
528 i2c->is_segment = false;
529
530 for (i = 0; i < num; i++) {
531 debug("xfer: num: %d/%d, len: %d, flags: %#x\n",
532 i + 1, num, msgs[i].len, msgs[i].flags);
533
534 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
535 i2c->is_segment = true;
536 hdmi_modb(hdmi, DDC_SEGMENT_ADDR, I2CM_SEG_ADDR,
537 I2CM_INTERFACE_CONTROL1);
538 hdmi_modb(hdmi, *msgs[i].buf << 7, I2CM_SEG_PTR,
539 I2CM_INTERFACE_CONTROL1);
540 } else {
541 if (msgs[i].flags & I2C_M_RD)
542 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
543 msgs[i].len);
544 else
545 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
546 msgs[i].len);
547 }
548 if (ret < 0)
549 break;
550 }
551
552 if (!ret)
553 ret = num;
554
555 /* Mute DONE and ERROR interrupts */
556 hdmi_modb(hdmi, 0, I2CM_OP_DONE_MASK_N | I2CM_NACK_RCVD_MASK_N,
557 MAINUNIT_1_INT_MASK_N);
558
559 return ret;
560 }
561
dw_hdmi_detect_phy(struct dw_hdmi_qp * hdmi)562 static int dw_hdmi_detect_phy(struct dw_hdmi_qp *hdmi)
563 {
564 /* Vendor PHYs require support from the glue layer. */
565 if (!hdmi->plat_data->qp_phy_ops || !hdmi->plat_data->phy_name) {
566 dev_err(hdmi->dev,
567 "Vendor HDMI PHY not supported by glue layer\n");
568 return -ENODEV;
569 }
570
571 hdmi->phy.ops = hdmi->plat_data->qp_phy_ops;
572 hdmi->phy.data = hdmi->plat_data->phy_data;
573 hdmi->phy.name = hdmi->plat_data->phy_name;
574
575 return 0;
576 }
577
578 static unsigned int
hdmi_get_tmdsclock(struct dw_hdmi_qp * hdmi,unsigned long mpixelclock)579 hdmi_get_tmdsclock(struct dw_hdmi_qp *hdmi, unsigned long mpixelclock)
580 {
581 unsigned int tmdsclock = mpixelclock;
582 unsigned int depth =
583 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format);
584
585 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
586 switch (depth) {
587 case 16:
588 tmdsclock = mpixelclock * 2;
589 break;
590 case 12:
591 tmdsclock = mpixelclock * 3 / 2;
592 break;
593 case 10:
594 tmdsclock = mpixelclock * 5 / 4;
595 break;
596 default:
597 break;
598 }
599 }
600
601 return tmdsclock;
602 }
603
hdmi_infoframe_set_checksum(u8 * ptr,int size)604 static void hdmi_infoframe_set_checksum(u8 *ptr, int size)
605 {
606 u8 csum = 0;
607 int i;
608
609 ptr[3] = 0;
610 /* compute checksum */
611 for (i = 0; i < size; i++)
612 csum += ptr[i];
613
614 ptr[3] = 256 - csum;
615 }
616
is_hdmi2_sink(struct dw_hdmi_qp * hdmi)617 static bool is_hdmi2_sink(struct dw_hdmi_qp *hdmi)
618 {
619 return hdmi->edid_data.display_info.hdmi.scdc.supported ||
620 hdmi->edid_data.display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
621 }
622
hdmi_config_AVI(struct dw_hdmi_qp * hdmi,struct drm_display_mode * mode)623 static void hdmi_config_AVI(struct dw_hdmi_qp *hdmi, struct drm_display_mode *mode)
624 {
625 struct hdmi_avi_infoframe frame;
626 u32 val, i, j;
627 u8 buff[17];
628 bool is_hdmi2 = false;
629 enum hdmi_quantization_range rgb_quant_range =
630 hdmi->hdmi_data.quant_range;
631
632 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) ||
633 hdmi->edid_data.display_info.hdmi.scdc.supported)
634 is_hdmi2 = true;
635 /* Initialise info frame from DRM mode */
636 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, is_hdmi2);
637
638 /*
639 * Ignore monitor selectable quantization, use quantization set
640 * by the user
641 */
642 drm_hdmi_avi_infoframe_quant_range(&frame, mode, rgb_quant_range,
643 true, is_hdmi2);
644 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
645 frame.colorspace = HDMI_COLORSPACE_YUV444;
646 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
647 frame.colorspace = HDMI_COLORSPACE_YUV422;
648 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
649 frame.colorspace = HDMI_COLORSPACE_YUV420;
650 else
651 frame.colorspace = HDMI_COLORSPACE_RGB;
652
653 /* Set up colorimetry and quant range */
654 if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
655 switch (hdmi->hdmi_data.enc_out_encoding) {
656 case V4L2_YCBCR_ENC_601:
657 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
658 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
659 else
660 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
661 frame.extended_colorimetry =
662 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
663 break;
664 case V4L2_YCBCR_ENC_709:
665 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
666 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
667 else
668 frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
669 frame.extended_colorimetry =
670 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
671 break;
672 case V4L2_YCBCR_ENC_BT2020:
673 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_BT2020)
674 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
675 else
676 frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
677 frame.extended_colorimetry =
678 HDMI_EXTENDED_COLORIMETRY_BT2020;
679 break;
680 default: /* Carries no data */
681 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
682 frame.extended_colorimetry =
683 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
684 break;
685 }
686
687 frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
688 } else {
689 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_BT2020) {
690 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
691 frame.extended_colorimetry =
692 HDMI_EXTENDED_COLORIMETRY_BT2020;
693 } else {
694 frame.colorimetry = HDMI_COLORIMETRY_NONE;
695 frame.extended_colorimetry =
696 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
697 }
698
699 if (is_hdmi2_sink(hdmi) &&
700 frame.quantization_range == HDMI_QUANTIZATION_RANGE_FULL)
701 frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_FULL;
702 else
703 frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
704 }
705
706 frame.scan_mode = HDMI_SCAN_MODE_NONE;
707
708 hdmi_avi_infoframe_pack_only(&frame, buff, 17);
709
710 /* mode which vic >= 128 must use avi version 3 */
711 if (hdmi->vic >= 128) {
712 frame.version = 3;
713 buff[1] = frame.version;
714 buff[4] &= 0x1f;
715 buff[4] |= ((frame.colorspace & 0x7) << 5);
716 buff[7] = hdmi->vic;
717 hdmi_infoframe_set_checksum(buff, 17);
718 }
719
720 /*
721 * The Designware IP uses a different byte format from standard
722 * AVI info frames, though generally the bits are in the correct
723 * bytes.
724 */
725
726 val = (frame.version << 8) | (frame.length << 16);
727 hdmi_writel(hdmi, val, PKT_AVI_CONTENTS0);
728
729 for (i = 0; i < 4; i++) {
730 for (j = 0; j < 4; j++) {
731 if (i * 4 + j >= 14)
732 break;
733 if (!j)
734 val = buff[i * 4 + j + 3];
735 val |= buff[i * 4 + j + 3] << (8 * j);
736 }
737
738 hdmi_writel(hdmi, val, PKT_AVI_CONTENTS1 + i * 4);
739 }
740
741 hdmi_modb(hdmi, 0, PKTSCHED_AVI_FIELDRATE, PKTSCHED_PKT_CONFIG1);
742
743 hdmi_modb(hdmi, PKTSCHED_AVI_TX_EN, PKTSCHED_AVI_TX_EN,
744 PKTSCHED_PKT_EN);
745 }
746
747 #define VSI_PKT_TYPE 0x81
748 #define VSI_PKT_VERSION 1
749 #define HDMI_FORUM_OUI 0xc45dd8
750 #define ALLM_MODE BIT(1)
751 #define HDMI_FORUM_LEN 9
752
hdmi_config_vendor_specific_infoframe(struct dw_hdmi_qp * hdmi,struct drm_display_mode * mode)753 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi_qp *hdmi,
754 struct drm_display_mode *mode)
755 {
756 struct hdmi_vendor_infoframe frame;
757 struct dw_hdmi_link_config *link_cfg = NULL;
758 u8 buffer[10];
759 u32 val;
760 ssize_t err;
761 int i, reg;
762
763 link_cfg = dw_hdmi_rockchip_get_link_cfg(hdmi->rk_hdmi);
764
765 hdmi_modb(hdmi, 0, PKTSCHED_VSI_TX_EN, PKTSCHED_PKT_EN);
766
767 for (i = 0; i <= 7; i++)
768 hdmi_writel(hdmi, 0, PKT_VSI_CONTENTS0 + i * 4);
769
770 if (link_cfg->allm_en) {
771 buffer[0] = VSI_PKT_TYPE;
772 buffer[1] = VSI_PKT_VERSION;
773 buffer[2] = 5;
774 buffer[4] = HDMI_FORUM_OUI & 0xff;
775 buffer[5] = (HDMI_FORUM_OUI >> 8) & 0xff;
776 buffer[6] = (HDMI_FORUM_OUI >> 16) & 0xff;
777 buffer[7] = VSI_PKT_VERSION;
778 buffer[8] = ALLM_MODE;
779
780 hdmi_infoframe_set_checksum(buffer, HDMI_FORUM_LEN);
781
782 err = 9;
783 } else {
784 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode);
785 if (err < 0)
786 /*
787 * Going into that statement does not means vendor infoframe
788 * fails. It just informed us that vendor infoframe is not
789 * needed for the selected mode. Only 4k or stereoscopic 3D
790 * mode requires vendor infoframe. So just simply return.
791 */
792 return;
793
794 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
795 if (err < 0) {
796 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
797 err);
798 return;
799 }
800 }
801
802 /* vsi header */
803 val = (buffer[2] << 16) | (buffer[1] << 8) | buffer[0];
804 hdmi_writel(hdmi, val, PKT_VSI_CONTENTS0);
805
806 reg = PKT_VSI_CONTENTS1;
807 for (i = 3; i < err; i++) {
808 if (i % 4 == 3)
809 val = buffer[i];
810 if (i % 4 == 0)
811 val |= buffer[i] << 8;
812 if (i % 4 == 1)
813 val |= buffer[i] << 16;
814 if (i % 4 == 2)
815 val |= buffer[i] << 24;
816
817 if ((i % 4 == 2) || (i == (err - 1))) {
818 hdmi_writel(hdmi, val, reg);
819 reg += 4;
820 }
821 }
822
823 hdmi_writel(hdmi, 0, PKT_VSI_CONTENTS7);
824
825 hdmi_modb(hdmi, 0, PKTSCHED_VSI_FIELDRATE, PKTSCHED_PKT_CONFIG1);
826 hdmi_modb(hdmi, PKTSCHED_VSI_TX_EN, PKTSCHED_VSI_TX_EN,
827 PKTSCHED_PKT_EN);
828 }
829
hdmi_config_CVTEM(struct dw_hdmi_qp * hdmi,struct dw_hdmi_link_config * link_cfg)830 static void hdmi_config_CVTEM(struct dw_hdmi_qp *hdmi,
831 struct dw_hdmi_link_config *link_cfg)
832 {
833 u8 ds_type = 0;
834 u8 sync = 1;
835 u8 vfr = 1;
836 u8 afr = 0;
837 u8 new = 1;
838 u8 end = 0;
839 u8 data_set_length = 136;
840 u8 hb1[6] = { 0x80, 0, 0, 0, 0, 0x40 };
841 u8 *pps_body;
842 u32 val, i, reg;
843 struct drm_display_mode *mode = &hdmi->previous_mode;
844 int hsync, hfront, hback;
845
846 hdmi_modb(hdmi, 0, PKTSCHED_EMP_CVTEM_TX_EN, PKTSCHED_PKT_EN);
847
848 if (!link_cfg->dsc_mode) {
849 printf("don't use dsc mode\n");
850 return;
851 }
852
853 pps_body = link_cfg->pps_payload;
854
855 hsync = mode->hsync_end - mode->hsync_start;
856 hback = mode->htotal - mode->hsync_end;
857 hfront = mode->hsync_start - mode->hdisplay;
858
859 for (i = 0; i < 6; i++) {
860 val = i << 16 | hb1[i] << 8;
861 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS0 + i * 0x20);
862 }
863
864 val = new << 7 | end << 6 | ds_type << 4 | afr << 3 |
865 vfr << 2 | sync << 1;
866 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS1);
867
868 val = data_set_length << 16 | pps_body[0] << 24;
869 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS2);
870
871 reg = PKT0_EMP_CVTEM_CONTENTS3;
872 for (i = 1; i < 125; i++) {
873 if (reg == PKT1_EMP_CVTEM_CONTENTS0 ||
874 reg == PKT2_EMP_CVTEM_CONTENTS0 ||
875 reg == PKT3_EMP_CVTEM_CONTENTS0 ||
876 reg == PKT4_EMP_CVTEM_CONTENTS0 ||
877 reg == PKT5_EMP_CVTEM_CONTENTS0) {
878 reg += 4;
879 i--;
880 continue;
881 }
882 if (i % 4 == 1)
883 val = pps_body[i];
884 if (i % 4 == 2)
885 val |= pps_body[i] << 8;
886 if (i % 4 == 3)
887 val |= pps_body[i] << 16;
888 if (!(i % 4)) {
889 val |= pps_body[i] << 24;
890 hdmi_writel(hdmi, val, reg);
891 reg += 4;
892 }
893 }
894
895 val = (hfront & 0xff) << 24 | pps_body[127] << 16 |
896 pps_body[126] << 8 | pps_body[125];
897 hdmi_writel(hdmi, val, PKT4_EMP_CVTEM_CONTENTS6);
898
899 val = (hback & 0xff) << 24 | ((hsync >> 8) & 0xff) << 16 |
900 (hsync & 0xff) << 8 | ((hfront >> 8) & 0xff);
901 hdmi_writel(hdmi, val, PKT4_EMP_CVTEM_CONTENTS7);
902
903 val = link_cfg->hcactive << 8 | ((hback >> 8) & 0xff);
904 hdmi_writel(hdmi, val, PKT5_EMP_CVTEM_CONTENTS1);
905
906 for (i = PKT5_EMP_CVTEM_CONTENTS2; i <= PKT5_EMP_CVTEM_CONTENTS7; i += 4)
907 hdmi_writel(hdmi, 0, i);
908
909 hdmi_modb(hdmi, PKTSCHED_EMP_CVTEM_TX_EN, PKTSCHED_EMP_CVTEM_TX_EN,
910 PKTSCHED_PKT_EN);
911 }
912
hdmi_set_frl_mask(int frl_rate)913 static int hdmi_set_frl_mask(int frl_rate)
914 {
915 switch (frl_rate) {
916 case 48:
917 return FRL_12GBPS_4LANE;
918 case 40:
919 return FRL_10GBPS_4LANE;
920 case 32:
921 return FRL_8GBPS_4LANE;
922 case 24:
923 return FRL_6GBPS_4LANE;
924 case 18:
925 return FRL_6GBPS_3LANE;
926 case 9:
927 return FRL_3GBPS_3LANE;
928 }
929
930 return 0;
931 }
932
hdmi_start_flt(struct dw_hdmi_qp * hdmi,u8 rate)933 static int hdmi_start_flt(struct dw_hdmi_qp *hdmi, u8 rate)
934 {
935 u8 val;
936 u32 value;
937 u8 ffe_lv = 0;
938 int i = 0;
939 bool ltsp = false;
940
941 hdmi_modb(hdmi, AVP_DATAPATH_VIDEO_SWDISABLE,
942 AVP_DATAPATH_VIDEO_SWDISABLE, GLOBAL_SWDISABLE);
943
944 hdmi_writel(hdmi, AVP_DATAPATH_SWINIT_P, GLOBAL_SWRESET_REQUEST);
945
946 /* clear flt flags */
947 drm_scdc_writeb(&hdmi->adap, 0x10, 0xff);
948
949 /* FLT_READY & FFE_LEVELS read */
950 for (i = 0; i < 20; i++) {
951 drm_scdc_readb(&hdmi->adap, SCDC_STATUS_FLAGS_0, &val);
952 if (val & BIT(6))
953 break;
954 mdelay(20);
955 }
956
957 if (i == 20) {
958 printf("sink flt isn't ready\n");
959 return -EINVAL;
960 }
961
962 /* max ffe level 3 */
963 val = 0 << 4 | hdmi_set_frl_mask(rate);
964 drm_scdc_writeb(&hdmi->adap, 0x31, val);
965 /* select FRL_RATE & FFE_LEVELS */
966 hdmi_writel(hdmi, ffe_lv, FLT_CONFIG0);
967
968 i = 500;
969 while (i--) {
970 mdelay(4);
971 drm_scdc_readb(&hdmi->adap, 0x10, &val);
972
973 if (!(val & 0x30))
974 continue;
975
976 if (val & BIT(5)) {
977 u8 reg_val, ln0, ln1, ln2, ln3;
978
979 drm_scdc_readb(&hdmi->adap, 0x41, ®_val);
980 ln0 = reg_val & 0xf;
981 ln1 = (reg_val >> 4) & 0xf;
982
983 drm_scdc_readb(&hdmi->adap, 0x42, ®_val);
984 ln2 = reg_val & 0xf;
985 ln3 = (reg_val >> 4) & 0xf;
986
987 if (!ln0 && !ln1 && !ln2 && !ln3) {
988 printf("goto ltsp\n");
989 ltsp = true;
990 hdmi_writel(hdmi, 0, FLT_CONFIG1);
991 } else if ((ln0 == 0xf) | (ln1 == 0xf) | (ln2 == 0xf) | (ln3 == 0xf)) {
992 printf("goto lts4\n");
993 break;
994 } else if ((ln0 == 0xe) | (ln1 == 0xe) | (ln2 == 0xe) | (ln3 == 0xe)) {
995 printf("goto ffe\n");
996 break;
997 } else {
998 value = (ln3 << 16) | (ln2 << 12) | (ln1 << 8) | (ln0 << 4) | 0xf;
999 hdmi_writel(hdmi, value, FLT_CONFIG1);
1000 }
1001 }
1002
1003 drm_scdc_writeb(&hdmi->adap, 0x10, val);
1004
1005 if ((val & BIT(4)) && ltsp) {
1006 hdmi_modb(hdmi, 0, AVP_DATAPATH_VIDEO_SWDISABLE, GLOBAL_SWDISABLE);
1007 printf("flt success\n");
1008 break;
1009 }
1010 }
1011
1012 if (i < 0) {
1013 printf("flt time out\n");
1014 return -ETIMEDOUT;
1015 }
1016
1017 return 0;
1018 }
1019
1020 #define HDMI_MODE_FRL_MASK BIT(30)
1021
hdmi_set_op_mode(struct dw_hdmi_qp * hdmi,struct dw_hdmi_link_config * link_cfg,struct display_state * state,struct rockchip_connector * conn)1022 static void hdmi_set_op_mode(struct dw_hdmi_qp *hdmi,
1023 struct dw_hdmi_link_config *link_cfg,
1024 struct display_state *state,
1025 struct rockchip_connector *conn)
1026 {
1027 int frl_rate;
1028 int i, ret;
1029
1030 if (!link_cfg->frl_mode) {
1031 printf("dw hdmi qp use tmds mode\n");
1032 hdmi_modb(hdmi, 0, OPMODE_FRL, LINK_CONFIG0);
1033 hdmi_modb(hdmi, 0, OPMODE_FRL_4LANES, LINK_CONFIG0);
1034 hdmi->phy.ops->init(conn, hdmi->rk_hdmi, state);
1035 hdmi->phy.enabled = true;
1036 return;
1037 }
1038
1039 if (link_cfg->frl_lanes == 4)
1040 hdmi_modb(hdmi, OPMODE_FRL_4LANES, OPMODE_FRL_4LANES,
1041 LINK_CONFIG0);
1042 else
1043 hdmi_modb(hdmi, 0, OPMODE_FRL_4LANES, LINK_CONFIG0);
1044
1045 hdmi_modb(hdmi, 1, OPMODE_FRL, LINK_CONFIG0);
1046
1047 frl_rate = link_cfg->frl_lanes * link_cfg->rate_per_lane;
1048 hdmi->phy.ops->init(conn, hdmi->rk_hdmi, state);
1049 hdmi->phy.enabled = true;
1050
1051 mdelay(200);
1052 ret = hdmi_start_flt(hdmi, frl_rate);
1053 if (ret) {
1054 hdmi_writel(hdmi, 0, FLT_CONFIG0);
1055 drm_scdc_writeb(&hdmi->adap, 0x31, 0);
1056 hdmi_modb(hdmi, 0, AVP_DATAPATH_VIDEO_SWDISABLE, GLOBAL_SWDISABLE);
1057 return;
1058 }
1059
1060 for (i = 0; i < 200; i++) {
1061 hdmi_modb(hdmi, PKTSCHED_NULL_TX_EN, PKTSCHED_NULL_TX_EN, PKTSCHED_PKT_EN);
1062 udelay(50);
1063 hdmi_modb(hdmi, 0, PKTSCHED_NULL_TX_EN, PKTSCHED_PKT_EN);
1064 udelay(50);
1065 }
1066 }
1067
dw_hdmi_setup(struct dw_hdmi_qp * hdmi,struct rockchip_connector * conn,struct drm_display_mode * mode,struct display_state * state)1068 static int dw_hdmi_setup(struct dw_hdmi_qp *hdmi,
1069 struct rockchip_connector *conn,
1070 struct drm_display_mode *mode,
1071 struct display_state *state)
1072 {
1073 int ret;
1074 void *data = hdmi->plat_data->phy_data;
1075 struct dw_hdmi_link_config *link_cfg;
1076 struct drm_hdmi_info *hdmi_info = &hdmi->edid_data.display_info.hdmi;
1077 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1078 u8 bytes = 0;
1079
1080 if (!hdmi->vic)
1081 printf("Non-CEA mode used in HDMI\n");
1082 else
1083 printf("CEA mode used vic=%d\n", hdmi->vic);
1084
1085 vmode->mpixelclock = mode->clock * 1000;
1086 vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock);
1087 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1088 vmode->mtmdsclock /= 2;
1089 printf("mtmdsclock:%d\n", vmode->mtmdsclock);
1090
1091 if (hdmi->plat_data->get_enc_out_encoding)
1092 hdmi->hdmi_data.enc_out_encoding =
1093 hdmi->plat_data->get_enc_out_encoding(data);
1094 else if (hdmi->vic == 6 || hdmi->vic == 7 ||
1095 hdmi->vic == 21 || hdmi->vic == 22 ||
1096 hdmi->vic == 2 || hdmi->vic == 3 ||
1097 hdmi->vic == 17 || hdmi->vic == 18)
1098 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
1099 else
1100 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
1101
1102 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1103 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
1104 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1;
1105 } else {
1106 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1107 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1108 }
1109
1110 /* TOFIX: Get input encoding from plat data or fallback to none */
1111 if (hdmi->plat_data->get_enc_in_encoding)
1112 hdmi->hdmi_data.enc_in_encoding =
1113 hdmi->plat_data->get_enc_in_encoding(data);
1114 else if (hdmi->plat_data->input_bus_encoding)
1115 hdmi->hdmi_data.enc_in_encoding =
1116 hdmi->plat_data->input_bus_encoding;
1117 else
1118 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
1119
1120 if (hdmi->plat_data->get_quant_range)
1121 hdmi->hdmi_data.quant_range =
1122 hdmi->plat_data->get_quant_range(data);
1123 else
1124 hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
1125
1126 /*
1127 * According to the dw-hdmi specification 6.4.2
1128 * vp_pr_cd[3:0]:
1129 * 0000b: No pixel repetition (pixel sent only once)
1130 * 0001b: Pixel sent two times (pixel repeated once)
1131 */
1132 hdmi->hdmi_data.pix_repet_factor =
1133 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0;
1134 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1135
1136 /* HDMI Initialization Step B.2 */
1137 hdmi->phy.ops->set_pll(conn, hdmi->rk_hdmi, state);
1138
1139 /* Mark yuv422 10bit */
1140 if (hdmi->hdmi_data.enc_out_bus_format == MEDIA_BUS_FMT_YUYV10_1X20)
1141 hdmi_writel(hdmi, BIT(20), VIDEO_INTERFACE_CONFIG0);
1142 dw_hdmi_qp_set_grf_cfg(hdmi->rk_hdmi);
1143 link_cfg = dw_hdmi_rockchip_get_link_cfg(hdmi->rk_hdmi);
1144
1145 /* not for DVI mode */
1146 if (hdmi->sink_is_hdmi) {
1147 printf("%s HDMI mode\n", __func__);
1148 hdmi_modb(hdmi, 0, OPMODE_DVI, LINK_CONFIG0);
1149 hdmi_modb(hdmi, HDCP2_BYPASS, HDCP2_BYPASS, HDCP2LOGIC_CONFIG0);
1150 hdmi_modb(hdmi, KEEPOUT_REKEY_ALWAYS, KEEPOUT_REKEY_CFG, FRAME_COMPOSER_CONFIG9);
1151 hdmi_writel(hdmi, 0, FLT_CONFIG0);
1152 if (hdmi_info->scdc.supported)
1153 drm_scdc_writeb(&hdmi->adap, 0x31, 0);
1154 if (!link_cfg->frl_mode) {
1155 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK) {
1156 drm_scdc_readb(&hdmi->adap, SCDC_SINK_VERSION, &bytes);
1157 drm_scdc_writeb(&hdmi->adap, SCDC_SOURCE_VERSION,
1158 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION));
1159 drm_scdc_set_high_tmds_clock_ratio(&hdmi->adap, 1);
1160 drm_scdc_set_scrambling(&hdmi->adap, 1);
1161 hdmi_writel(hdmi, 1, SCRAMB_CONFIG0);
1162 mdelay(100);
1163 } else {
1164 if (hdmi_info->scdc.supported) {
1165 drm_scdc_set_high_tmds_clock_ratio(&hdmi->adap, 0);
1166 drm_scdc_set_scrambling(&hdmi->adap, 0);
1167 }
1168 hdmi_writel(hdmi, 0, SCRAMB_CONFIG0);
1169 }
1170 }
1171 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1172 hdmi_config_AVI(hdmi, mode);
1173 hdmi_config_vendor_specific_infoframe(hdmi, mode);
1174 hdmi_config_CVTEM(hdmi, link_cfg);
1175 hdmi_set_op_mode(hdmi, link_cfg, state, conn);
1176 /* clear avmute */
1177 mdelay(50);
1178 hdmi_writel(hdmi, 2, PKTSCHED_PKT_CONTROL0);
1179 hdmi_modb(hdmi, PKTSCHED_GCP_TX_EN, PKTSCHED_GCP_TX_EN,
1180 PKTSCHED_PKT_EN);
1181 } else {
1182 hdmi_modb(hdmi, OPMODE_DVI, OPMODE_DVI, LINK_CONFIG0);
1183 ret = hdmi->phy.ops->init(conn, hdmi->rk_hdmi, state);
1184 if (ret)
1185 return ret;
1186 hdmi->phy.enabled = true;
1187 printf("%s DVI mode\n", __func__);
1188 }
1189
1190 /* Mark uboot hdmi is enabled */
1191 hdmi_writel(hdmi, BIT(21), VIDEO_INTERFACE_CONFIG0);
1192
1193 return 0;
1194 }
1195
dw_hdmi_detect_hotplug(struct dw_hdmi_qp * hdmi,struct display_state * state)1196 int dw_hdmi_detect_hotplug(struct dw_hdmi_qp *hdmi,
1197 struct display_state *state)
1198 {
1199 struct connector_state *conn_state = &state->conn_state;
1200 struct rockchip_connector *conn = conn_state->connector;
1201 int ret;
1202
1203 ret = hdmi->phy.ops->read_hpd(hdmi->rk_hdmi);
1204 if (!ret) {
1205 if (conn->bridge)
1206 ret = rockchip_bridge_detect(conn->bridge);
1207 }
1208
1209 if (ret || state->force_output) {
1210 if (!hdmi->id)
1211 conn_state->output_if |= VOP_OUTPUT_IF_HDMI0;
1212 else
1213 conn_state->output_if |= VOP_OUTPUT_IF_HDMI1;
1214 }
1215
1216 return ret;
1217 }
1218
rockchip_dw_hdmi_qp_init(struct rockchip_connector * conn,struct display_state * state)1219 int rockchip_dw_hdmi_qp_init(struct rockchip_connector *conn, struct display_state *state)
1220 {
1221 struct connector_state *conn_state = &state->conn_state;
1222 const struct dw_hdmi_plat_data *pdata =
1223 (const struct dw_hdmi_plat_data *)dev_get_driver_data(conn->dev);
1224 void *rk_hdmi = dev_get_priv(conn->dev);
1225 struct dw_hdmi_qp *hdmi;
1226 struct drm_display_mode *mode_buf;
1227 ofnode hdmi_node = conn->dev->node;
1228 struct device_node *ddc_node;
1229
1230 hdmi = malloc(sizeof(struct dw_hdmi_qp));
1231 if (!hdmi)
1232 return -ENOMEM;
1233
1234 memset(hdmi, 0, sizeof(struct dw_hdmi_qp));
1235 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode));
1236 if (!mode_buf)
1237 return -ENOMEM;
1238
1239 hdmi->rk_hdmi = rk_hdmi;
1240 hdmi->id = of_alias_get_id(ofnode_to_np(hdmi_node), "hdmi");
1241 if (hdmi->id < 0)
1242 hdmi->id = 0;
1243 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, hdmi->id);
1244
1245 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode));
1246
1247 hdmi->regs = dev_read_addr_ptr(conn->dev);
1248
1249 ddc_node = of_parse_phandle(ofnode_to_np(hdmi_node), "ddc-i2c-bus", 0);
1250 if (ddc_node) {
1251 uclass_get_device_by_ofnode(UCLASS_I2C, np_to_ofnode(ddc_node),
1252 &hdmi->adap.i2c_bus);
1253 if (hdmi->adap.i2c_bus)
1254 hdmi->adap.ops = i2c_get_ops(hdmi->adap.i2c_bus);
1255 }
1256
1257 hdmi->i2c = malloc(sizeof(struct dw_hdmi_i2c));
1258 if (!hdmi->i2c)
1259 return -ENOMEM;
1260 hdmi->adap.ddc_xfer = dw_hdmi_i2c_xfer;
1261
1262 /*
1263 * Read high and low time from device tree. If not available use
1264 * the default timing scl clock rate is about 99.6KHz.
1265 */
1266 hdmi->i2c->scl_high_ns =
1267 ofnode_read_s32_default(hdmi_node,
1268 "ddc-i2c-scl-high-time-ns", 4708);
1269 hdmi->i2c->scl_low_ns =
1270 ofnode_read_s32_default(hdmi_node,
1271 "ddc-i2c-scl-low-time-ns", 4916);
1272
1273 dw_hdmi_i2c_init(hdmi);
1274 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA;
1275
1276 hdmi->dev_type = pdata->dev_type;
1277 hdmi->plat_data = pdata;
1278 hdmi->edid_data.mode_buf = mode_buf;
1279
1280 conn->data = hdmi;
1281
1282 dw_hdmi_detect_phy(hdmi);
1283 hdmi_writel(hdmi, 0, MAINUNIT_0_INT_MASK_N);
1284 hdmi_writel(hdmi, 0, MAINUNIT_1_INT_MASK_N);
1285 hdmi_writel(hdmi, 428571429, TIMER_BASE_CONFIG0);
1286
1287 dw_hdmi_qp_io_path_init(hdmi->rk_hdmi);
1288
1289 return 0;
1290 }
1291
rockchip_dw_hdmi_qp_deinit(struct rockchip_connector * conn,struct display_state * state)1292 void rockchip_dw_hdmi_qp_deinit(struct rockchip_connector *conn, struct display_state *state)
1293 {
1294 struct dw_hdmi_qp *hdmi = conn->data;
1295
1296 if (hdmi->i2c)
1297 free(hdmi->i2c);
1298 if (hdmi->edid_data.mode_buf)
1299 free(hdmi->edid_data.mode_buf);
1300 if (hdmi)
1301 free(hdmi);
1302 }
1303
rockchip_dw_hdmi_qp_config_output(struct rockchip_connector * conn,struct display_state * state)1304 static void rockchip_dw_hdmi_qp_config_output(struct rockchip_connector *conn,
1305 struct display_state *state)
1306 {
1307 struct connector_state *conn_state = &state->conn_state;
1308 struct drm_display_mode *mode = &conn_state->mode;
1309 struct dw_hdmi_qp *hdmi = conn->data;
1310 unsigned int bus_format;
1311 unsigned long enc_out_encoding;
1312 struct overscan *overscan = &conn_state->overscan;
1313
1314 dw_hdmi_qp_select_output(&hdmi->edid_data, conn, &bus_format,
1315 overscan, hdmi->dev_type,
1316 hdmi->output_bus_format_rgb, hdmi->rk_hdmi,
1317 state);
1318
1319 *mode = *hdmi->edid_data.preferred_mode;
1320 hdmi->vic = drm_match_cea_mode(mode);
1321
1322 printf("mode:%dx%d bus_format:0x%x\n", mode->hdisplay, mode->vdisplay, bus_format);
1323 conn_state->bus_format = bus_format;
1324 hdmi->hdmi_data.enc_in_bus_format = bus_format;
1325 hdmi->hdmi_data.enc_out_bus_format = bus_format;
1326
1327 switch (bus_format) {
1328 case MEDIA_BUS_FMT_YUYV10_1X20:
1329 conn_state->bus_format = MEDIA_BUS_FMT_YUYV10_1X20;
1330 hdmi->hdmi_data.enc_in_bus_format =
1331 MEDIA_BUS_FMT_YUYV10_1X20;
1332 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV422;
1333 break;
1334 case MEDIA_BUS_FMT_YUYV8_1X16:
1335 conn_state->bus_format = MEDIA_BUS_FMT_YUYV8_1X16;
1336 hdmi->hdmi_data.enc_in_bus_format =
1337 MEDIA_BUS_FMT_YUYV8_1X16;
1338 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV422;
1339 break;
1340 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
1341 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
1342 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV420;
1343 break;
1344 }
1345
1346 if (hdmi->vic == 6 || hdmi->vic == 7 || hdmi->vic == 21 ||
1347 hdmi->vic == 22 || hdmi->vic == 2 || hdmi->vic == 3 ||
1348 hdmi->vic == 17 || hdmi->vic == 18)
1349 enc_out_encoding = V4L2_YCBCR_ENC_601;
1350 else
1351 enc_out_encoding = V4L2_YCBCR_ENC_709;
1352
1353 if (enc_out_encoding == V4L2_YCBCR_ENC_BT2020)
1354 conn_state->color_encoding = DRM_COLOR_YCBCR_BT2020;
1355 else if (bus_format == MEDIA_BUS_FMT_RGB888_1X24 ||
1356 bus_format == MEDIA_BUS_FMT_RGB101010_1X30)
1357 conn_state->color_encoding = DRM_COLOR_YCBCR_BT709;
1358 else if (enc_out_encoding == V4L2_YCBCR_ENC_709)
1359 conn_state->color_encoding = DRM_COLOR_YCBCR_BT709;
1360 else
1361 conn_state->color_encoding = DRM_COLOR_YCBCR_BT601;
1362
1363 if (bus_format == MEDIA_BUS_FMT_RGB888_1X24 ||
1364 bus_format == MEDIA_BUS_FMT_RGB101010_1X30)
1365 conn_state->color_range = hdmi->hdmi_data.quant_range ==
1366 HDMI_QUANTIZATION_RANGE_LIMITED ?
1367 DRM_COLOR_YCBCR_LIMITED_RANGE :
1368 DRM_COLOR_YCBCR_FULL_RANGE;
1369 else
1370 conn_state->color_range = hdmi->hdmi_data.quant_range ==
1371 HDMI_QUANTIZATION_RANGE_FULL ?
1372 DRM_COLOR_YCBCR_FULL_RANGE :
1373 DRM_COLOR_YCBCR_LIMITED_RANGE;
1374 }
1375
rockchip_dw_hdmi_qp_prepare(struct rockchip_connector * conn,struct display_state * state)1376 int rockchip_dw_hdmi_qp_prepare(struct rockchip_connector *conn, struct display_state *state)
1377 {
1378 struct connector_state *conn_state = &state->conn_state;
1379 struct drm_display_mode *mode = &conn_state->mode;
1380 struct dw_hdmi_qp *hdmi = conn->data;
1381
1382 if (!hdmi->edid_data.preferred_mode && conn->bridge) {
1383 drm_add_hdmi_modes(&hdmi->edid_data, mode);
1384 drm_mode_sort(&hdmi->edid_data);
1385 hdmi->sink_is_hdmi = true;
1386 hdmi->sink_has_audio = true;
1387 rockchip_dw_hdmi_qp_config_output(conn, state);
1388 }
1389
1390 return 0;
1391 }
1392
rockchip_dw_hdmi_qp_check(struct rockchip_connector * conn,struct display_state * state)1393 int rockchip_dw_hdmi_qp_check(struct rockchip_connector *conn, struct display_state *state)
1394 {
1395 struct crtc_state *cstate = &state->crtc_state;
1396 struct rockchip_crtc *crtc = cstate->crtc;
1397 struct dw_hdmi_qp *hdmi = conn->data;
1398
1399 /* clear hdmi uboot logo on flag */
1400 if (crtc->splice_mode && cstate->crtc_id == 1)
1401 hdmi_writel(hdmi, 0, I2CM_INTERFACE_CONTROL0);
1402
1403 return 0;
1404 }
1405
dw_hdmi_disable(struct rockchip_connector * conn,struct dw_hdmi_qp * hdmi,struct display_state * state)1406 static void dw_hdmi_disable(struct rockchip_connector *conn, struct dw_hdmi_qp *hdmi,
1407 struct display_state *state)
1408 {
1409 if (hdmi->phy.enabled) {
1410 hdmi->phy.ops->disable(conn, hdmi->rk_hdmi, state);
1411 hdmi->phy.enabled = false;
1412 }
1413 }
1414
rockchip_dw_hdmi_qp_enable(struct rockchip_connector * conn,struct display_state * state)1415 int rockchip_dw_hdmi_qp_enable(struct rockchip_connector *conn, struct display_state *state)
1416 {
1417 struct connector_state *conn_state = &state->conn_state;
1418 struct drm_display_mode *mode = &conn_state->mode;
1419 struct dw_hdmi_qp *hdmi = conn->data;
1420
1421 if (!hdmi)
1422 return -EFAULT;
1423
1424 /* Store the display mode for plugin/DKMS poweron events */
1425 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1426
1427 dw_hdmi_setup(hdmi, conn, mode, state);
1428
1429 return 0;
1430 }
1431
rockchip_dw_hdmi_qp_disable(struct rockchip_connector * conn,struct display_state * state)1432 int rockchip_dw_hdmi_qp_disable(struct rockchip_connector *conn, struct display_state *state)
1433 {
1434 struct dw_hdmi_qp *hdmi = conn->data;
1435
1436 dw_hdmi_disable(conn, hdmi, state);
1437 return 0;
1438 }
1439
rockchip_dw_hdmi_qp_mode_valid(struct dw_hdmi_qp * hdmi)1440 static void rockchip_dw_hdmi_qp_mode_valid(struct dw_hdmi_qp *hdmi)
1441 {
1442 struct hdmi_edid_data *edid_data = &hdmi->edid_data;
1443 int i;
1444 bool enable_gpio = dw_hdmi_qp_check_enable_gpio(hdmi->rk_hdmi);
1445
1446 for (i = 0; i < edid_data->modes; i++) {
1447 if (edid_data->mode_buf[i].invalid)
1448 continue;
1449
1450 if (edid_data->mode_buf[i].clock <= 25000)
1451 edid_data->mode_buf[i].invalid = true;
1452
1453 if (edid_data->mode_buf[i].clock > 600000 && !enable_gpio)
1454 edid_data->mode_buf[i].invalid = true;
1455 }
1456 }
1457
_rockchip_dw_hdmi_qp_get_timing(struct rockchip_connector * conn,struct display_state * state)1458 static int _rockchip_dw_hdmi_qp_get_timing(struct rockchip_connector *conn,
1459 struct display_state *state)
1460 {
1461 int i;
1462 struct connector_state *conn_state = &state->conn_state;
1463 struct dw_hdmi_qp *hdmi = conn->data;
1464 struct edid *edid = (struct edid *)conn_state->edid;
1465 const u8 def_modes_vic[6] = {4, 16, 2, 17, 31, 19};
1466 int ret = 0;
1467
1468 if (!hdmi)
1469 return -EFAULT;
1470
1471 if (edid) {
1472 hdmi->sink_is_hdmi =
1473 drm_detect_hdmi_monitor(edid);
1474 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1475 ret = drm_add_edid_modes(&hdmi->edid_data, conn_state->edid);
1476 }
1477 if (ret <= 0) {
1478 hdmi->sink_is_hdmi = true;
1479 hdmi->sink_has_audio = true;
1480 do_cea_modes(&hdmi->edid_data, def_modes_vic,
1481 sizeof(def_modes_vic));
1482 hdmi->edid_data.preferred_mode = &hdmi->edid_data.mode_buf[0];
1483 printf("failed to get edid\n");
1484 }
1485 drm_rk_filter_whitelist(&hdmi->edid_data);
1486 rockchip_dw_hdmi_qp_mode_valid(hdmi);
1487 drm_mode_max_resolution_filter(&hdmi->edid_data,
1488 &state->crtc_state.max_output);
1489 if (!drm_mode_prune_invalid(&hdmi->edid_data)) {
1490 printf("can't find valid hdmi mode\n");
1491 return -EINVAL;
1492 }
1493
1494 for (i = 0; i < hdmi->edid_data.modes; i++)
1495 hdmi->edid_data.mode_buf[i].vrefresh =
1496 drm_mode_vrefresh(&hdmi->edid_data.mode_buf[i]);
1497
1498 drm_mode_sort(&hdmi->edid_data);
1499
1500 rockchip_dw_hdmi_qp_config_output(conn, state);
1501
1502 return 0;
1503 }
1504
rockchip_dw_hdmi_qp_get_timing(struct rockchip_connector * conn,struct display_state * state)1505 int rockchip_dw_hdmi_qp_get_timing(struct rockchip_connector *conn, struct display_state *state)
1506 {
1507 struct connector_state *conn_state = &state->conn_state;
1508 struct dw_hdmi_qp *hdmi = conn->data;
1509
1510 conn_state->edid = drm_do_get_edid(&hdmi->adap);
1511
1512 if (conn_state->secondary)
1513 _rockchip_dw_hdmi_qp_get_timing(conn_state->secondary, state);
1514
1515 return _rockchip_dw_hdmi_qp_get_timing(conn, state);
1516 }
1517
1518
rockchip_dw_hdmi_qp_detect(struct rockchip_connector * conn,struct display_state * state)1519 int rockchip_dw_hdmi_qp_detect(struct rockchip_connector *conn, struct display_state *state)
1520 {
1521 int ret;
1522 struct dw_hdmi_qp *hdmi = conn->data;
1523
1524 if (!hdmi)
1525 return -EFAULT;
1526
1527 ret = dw_hdmi_detect_hotplug(hdmi, state);
1528
1529 return ret;
1530 }
1531
rockchip_dw_hdmi_qp_get_edid(struct rockchip_connector * conn,struct display_state * state)1532 int rockchip_dw_hdmi_qp_get_edid(struct rockchip_connector *conn, struct display_state *state)
1533 {
1534 int ret = 0;
1535 struct connector_state *conn_state = &state->conn_state;
1536 struct dw_hdmi_qp *hdmi = conn->data;
1537
1538 conn_state->edid = drm_do_get_edid(&hdmi->adap);
1539 if (!conn_state->edid)
1540 ret = -EINVAL;
1541
1542 return ret;
1543 }
1544