1 /* 2 * Copyright 2024-2026 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <plat/common/common_def.h> 11 12 #define PLATFORM_STACK_SIZE U(0x1000) 13 14 /* Caches */ 15 #define CACHE_WRITEBACK_SHIFT U(6) 16 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 17 18 /* CPU Topology */ 19 #define PLATFORM_CORE_COUNT U(4) 20 #define PLATFORM_SYSTEM_COUNT U(1) 21 #define PLATFORM_CLUSTER_COUNT U(2) 22 #define PLATFORM_PRIMARY_CPU U(0) 23 #define PLATFORM_MPIDR_CPU_MASK_BITS U(1) 24 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(2) 25 26 /* Power Domains */ 27 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_SYSTEM_COUNT + \ 28 PLATFORM_CLUSTER_COUNT + \ 29 PLATFORM_CORE_COUNT) 30 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 31 #define PLAT_MAX_OFF_STATE U(2) 32 #define PLAT_MAX_RET_STATE U(1) 33 #define PLAT_MAX_PWR_LVL_STATES U(2) 34 35 #define S32G_DDR0_END UL(0xffffffff) 36 37 #define S32G_BL33_IMAGE_SIZE (7 * SZ_1M) 38 39 /* BL2 stage */ 40 #define BL2_BASE UL(0x34078000) 41 #define BL2_LIMIT UL(0x34100000) 42 43 /* BL33 stage */ 44 #define BL33_BASE (S32G_DDR0_END - S32G_BL33_IMAGE_SIZE - \ 45 SZ_1M + 1) 46 #define BL33_LIMIT (S32G_DDR0_END) 47 48 /* BL31 stage */ 49 #define BL31_BASE ((BL33_BASE - 1) - (2 * SZ_1M) + 1) 50 #define BL31_LIMIT (BL33_BASE - 1) 51 52 /* IO buffer used to copy images from storage */ 53 #define IO_BUFFER_BASE UL(0x345ff000) 54 #define IO_BUFFER_SIZE U(0x13000) 55 56 #define DDR_PHY_BASE_ADDR UL(0x40380000) 57 #define DDR_PHY_SIZE U(0x80000) 58 59 #define GPR_BASE_PAGE_ADDR UL(0x4007C000) 60 #define GPR_SIZE U(0x1000) 61 62 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 36) 63 /* We'll be doing a 1:1 mapping anyway */ 64 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 36) 65 66 #define MAX_MMAP_REGIONS U(23) 67 #define MAX_XLAT_TABLES U(33) 68 69 /* Console settings */ 70 #define UART_BASE UL(0x401C8000) 71 #define UART_BAUDRATE U(115200) 72 #define UART_CLOCK_HZ U(125000000) 73 74 /* uSDHC */ 75 #define S32G_USDHC_BASE UL(0x402F0000) 76 77 #define S32G_FIP_BASE UL(0x34100000) 78 #define S32G_FIP_SIZE UL(0x100000) 79 80 #define MAX_IO_HANDLES U(2) 81 #define MAX_IO_DEVICES U(2) 82 83 /* uSDHC as block device */ 84 #define MAX_IO_BLOCK_DEVICES U(1) 85 86 /* GIC settings */ 87 #define S32G_GIC_BASE UL(0x50800000) 88 #define PLAT_GICD_BASE S32G_GIC_BASE 89 #define PLAT_GICR_BASE (S32G_GIC_BASE + UL(0x80000)) 90 91 /* Generic timer frequency; this goes directly into CNTFRQ_EL0. 92 * Its end-value is 5MHz; this is based on the assumption that 93 * GPR00[CA53_COUNTER_CLK_DIV_VAL] contains the reset value of 0x7, hence 94 * producing a divider value of 8, applied to the FXOSC frequency of 40MHz. 95 */ 96 #define COUNTER_FREQUENCY U(5000000) 97 98 #endif /* PLATFORM_DEF_H */ 99