1 /*
2 * (C) Copyright 2015 Google, Inc
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7 #ifndef _ASM_ARCH_CLOCK_H
8 #define _ASM_ARCH_CLOCK_H
9
10 /* define pll mode */
11 #define RKCLK_PLL_MODE_SLOW 0
12 #define RKCLK_PLL_MODE_NORMAL 1
13 #define RKCLK_PLL_MODE_DEEP 2
14
15 /*
16 * PLL flags
17 */
18 #define ROCKCHIP_PLL_SYNC_RATE BIT(0)
19 /* normal mode only. now only for pll_rk3036, pll_rk3328 type */
20 #define ROCKCHIP_PLL_FIXED_MODE BIT(1)
21
22 enum {
23 ROCKCHIP_SYSCON_NOC,
24 ROCKCHIP_SYSCON_GRF,
25 ROCKCHIP_SYSCON_SGRF,
26 ROCKCHIP_SYSCON_PMU,
27 ROCKCHIP_SYSCON_PMUGRF,
28 ROCKCHIP_SYSCON_PMUSGRF,
29 ROCKCHIP_SYSCON_CIC,
30 ROCKCHIP_SYSCON_MSCH,
31 ROCKCHIP_SYSCON_USBGRF,
32 ROCKCHIP_SYSCON_PCIE30_PHY_GRF,
33 ROCKCHIP_SYSCON_PHP_GRF,
34 ROCKCHIP_SYSCON_PIPE_PHY0_GRF,
35 ROCKCHIP_SYSCON_PIPE_PHY1_GRF,
36 ROCKCHIP_SYSCON_PIPE_PHY2_GRF,
37 ROCKCHIP_SYSCON_VOP_GRF,
38 ROCKCHIP_SYSCON_VO_GRF,
39 ROCKCHIP_SYSCON_IOC,
40 ROCKCHIP_SYSCON_SDGMAC_GRF,
41 };
42
43 /* Standard Rockchip clock numbers */
44 enum rk_clk_id {
45 CLK_OSC,
46 CLK_ARM,
47 CLK_DDR,
48 CLK_CODEC,
49 CLK_GENERAL,
50 CLK_NEW,
51
52 CLK_COUNT,
53 };
54
55 #define PLL(_type, _id, _con, _mode, _mshift, \
56 _lshift, _pflags, _rtable) \
57 { \
58 .id = _id, \
59 .type = _type, \
60 .con_offset = _con, \
61 .mode_offset = _mode, \
62 .mode_shift = _mshift, \
63 .lock_shift = _lshift, \
64 .pll_flags = _pflags, \
65 .rate_table = _rtable, \
66 }
67
68 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
69 _postdiv2, _dsmpd, _frac) \
70 { \
71 .rate = _rate##U, \
72 .fbdiv = _fbdiv, \
73 .postdiv1 = _postdiv1, \
74 .refdiv = _refdiv, \
75 .postdiv2 = _postdiv2, \
76 .dsmpd = _dsmpd, \
77 .frac = _frac, \
78 }
79
80 #define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \
81 { \
82 .rate = _rate##U, \
83 .p = _p, \
84 .m = _m, \
85 .s = _s, \
86 .k = _k, \
87 }
88
89 struct rockchip_pll_rate_table {
90 unsigned long rate;
91 unsigned int nr;
92 unsigned int nf;
93 unsigned int no;
94 unsigned int nb;
95 /* for RK3036/RK3399 */
96 unsigned int fbdiv;
97 unsigned int postdiv1;
98 unsigned int refdiv;
99 unsigned int postdiv2;
100 unsigned int dsmpd;
101 unsigned int frac;
102 /* for RK3588 */
103 unsigned int m;
104 unsigned int p;
105 unsigned int s;
106 unsigned int k;
107 };
108
109 enum rockchip_pll_type {
110 pll_rk3036,
111 pll_rk3066,
112 pll_rk3328,
113 pll_rk3366,
114 pll_rk3399,
115 pll_rk3588,
116 };
117
118 struct rockchip_pll_clock {
119 unsigned int id;
120 unsigned int con_offset;
121 unsigned int mode_offset;
122 unsigned int mode_shift;
123 unsigned int lock_shift;
124 enum rockchip_pll_type type;
125 unsigned int pll_flags;
126 struct rockchip_pll_rate_table *rate_table;
127 unsigned int mode_mask;
128 };
129
130 struct rockchip_cpu_rate_table {
131 unsigned long rate;
132 unsigned int aclk_div;
133 unsigned int pclk_div;
134 };
135
136 #ifdef CONFIG_ROCKCHIP_IMAGE_TINY
rockchip_pll_get_rate(struct rockchip_pll_clock * pll,void __iomem * base,ulong pll_id)137 static inline ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll,
138 void __iomem *base,
139 ulong pll_id)
140 {
141 return 0;
142 }
143
rockchip_pll_set_rate(struct rockchip_pll_clock * pll,void __iomem * base,ulong pll_id,ulong drate)144 static inline int rockchip_pll_set_rate(struct rockchip_pll_clock *pll,
145 void __iomem *base, ulong pll_id,
146 ulong drate)
147 {
148 return 0;
149 }
150
151 static inline const struct rockchip_cpu_rate_table *
rockchip_get_cpu_settings(struct rockchip_cpu_rate_table * cpu_table,ulong rate)152 rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table,
153 ulong rate)
154 {
155 return NULL;
156 }
157 #else
158 int rockchip_pll_set_rate(struct rockchip_pll_clock *pll,
159 void __iomem *base, ulong clk_id,
160 ulong drate);
161 ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll,
162 void __iomem *base, ulong clk_id);
163 const struct rockchip_cpu_rate_table *
164 rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table,
165 ulong rate);
166 #endif
167
rk_pll_id(enum rk_clk_id clk_id)168 static inline int rk_pll_id(enum rk_clk_id clk_id)
169 {
170 return clk_id - 1;
171 }
172
173 struct sysreset_reg {
174 unsigned int glb_srst_fst_value;
175 unsigned int glb_srst_snd_value;
176 };
177
178 struct softreset_reg {
179 void __iomem *base;
180 unsigned int sf_reset_offset;
181 unsigned int sf_reset_num;
182 };
183
184 /**
185 * clk_get_divisor() - Calculate the required clock divisior
186 *
187 * Given an input rate and a required output_rate, calculate the Rockchip
188 * divisor needed to achieve this.
189 *
190 * @input_rate: Input clock rate in Hz
191 * @output_rate: Output clock rate in Hz
192 * @return divisor register value to use
193 */
clk_get_divisor(ulong input_rate,uint output_rate)194 static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
195 {
196 uint clk_div;
197
198 clk_div = input_rate / output_rate;
199 clk_div = (clk_div + 1) & 0xfffe;
200
201 return clk_div;
202 }
203
204 /**
205 * rockchip_get_cru() - get a pointer to the clock/reset unit registers
206 *
207 * @return pointer to registers, or -ve error on error
208 */
209 void *rockchip_get_cru(void);
210
211 /**
212 * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers
213 *
214 * @return pointer to registers, or -ve error on error
215 */
216 void *rockchip_get_pmucru(void);
217
218 struct rk3288_cru;
219 struct rk3288_grf;
220
221 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
222
223 int rockchip_get_clk(struct udevice **devp);
224
225 int rockchip_get_scmi_clk(struct udevice **devp);
226
227 #endif
228