1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2019-2020, Linaro Limited and Contributors. 4 * All rights reserved. 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <plat/common/common_def.h> 12 #include <tbbr_img_def.h> 13 14 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 15 #define QEMU_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 16 17 #define PLATFORM_STACK_SIZE 0x1000 18 19 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) 20 /* 21 * Define the number of cores per cluster used in calculating core position. 22 * The cluster number is shifted by this value and added to the core ID, 23 * so its value represents log2(cores/cluster). 24 * Default is 2**(3) = 8 cores per cluster. 25 */ 26 #define PLATFORM_CPU_PER_CLUSTER_SHIFT U(3) 27 #define PLATFORM_CLUSTER_COUNT U(64) 28 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 29 PLATFORM_MAX_CPUS_PER_CLUSTER) 30 #define QEMU_PRIMARY_CPU U(0) 31 32 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ 33 PLATFORM_CORE_COUNT) 34 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 35 36 #define PLAT_MAX_RET_STATE 1 37 #define PLAT_MAX_OFF_STATE 2 38 39 /* Local power state for power domains in Run state. */ 40 #define PLAT_LOCAL_STATE_RUN 0 41 /* Local power state for retention. Valid only for CPU power domains */ 42 #define PLAT_LOCAL_STATE_RET 1 43 /* 44 * Local power state for OFF/power-down. Valid for CPU and cluster power 45 * domains. 46 */ 47 #define PLAT_LOCAL_STATE_OFF 2 48 49 /* 50 * Macros used to parse state information from State-ID if it is using the 51 * recommended encoding for State-ID. 52 */ 53 #define PLAT_LOCAL_PSTATE_WIDTH 4 54 #define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1) 55 56 /* 57 * Some data must be aligned on the biggest cache line size in the platform. 58 * This is known only to the platform as it might have a combination of 59 * integrated and external caches. 60 */ 61 #define CACHE_WRITEBACK_SHIFT 6 62 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 63 64 /* 65 * Define the max number of memory nodes. 66 */ 67 #define PLAT_MAX_MEM_NODES 128 68 69 /* Where QEMU starts the NS RAM */ 70 #define PLAT_QEMU_DRAM0_BASE 0x10000000000ULL 71 72 /* 73 * Partition memory into secure ROM, non-secure DRAM, secure "SRAM", 74 * and secure DRAM. 75 */ 76 #define SEC_ROM_BASE 0x00000000 77 #define SEC_ROM_SIZE 0x00020000 78 79 /* 80 * When the RME extension is enabled, the base of the NS RAM is shifted after 81 * RMM. 82 */ 83 #define NS_DRAM0_BASE (PLAT_QEMU_DRAM0_BASE + \ 84 NS_DRAM0_BASE_OFFSET) 85 #define NS_DRAM0_SIZE 0x00020000000 86 87 #define SEC_SRAM_BASE 0x20000000 88 #define SEC_SRAM_SIZE 0x20000000 89 90 /* 91 * RAD just placeholders, need to be chosen after finalizing mem map 92 */ 93 #define SEC_DRAM_BASE 0x1000 94 #define SEC_DRAM_SIZE 0x1000 95 96 /* Load pageable part of OP-TEE 2MB above secure DRAM base */ 97 #define QEMU_OPTEE_PAGEABLE_LOAD_BASE (SEC_DRAM_BASE + 0x00200000) 98 #define QEMU_OPTEE_PAGEABLE_LOAD_SIZE 0x00400000 99 100 /* 101 * ARM-TF lives in SRAM, partition it here 102 */ 103 104 #define SHARED_RAM_BASE SEC_SRAM_BASE 105 #define SHARED_RAM_SIZE 0x00002000 106 107 #define PLAT_QEMU_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE 108 #define PLAT_QEMU_TRUSTED_MAILBOX_SIZE (8 + PLAT_QEMU_HOLD_SIZE) 109 #define PLAT_QEMU_HOLD_BASE (PLAT_QEMU_TRUSTED_MAILBOX_BASE + 8) 110 #define PLAT_QEMU_HOLD_SIZE (PLATFORM_CORE_COUNT * \ 111 PLAT_QEMU_HOLD_ENTRY_SIZE) 112 #define PLAT_QEMU_HOLD_ENTRY_SHIFT 3 113 #define PLAT_QEMU_HOLD_ENTRY_SIZE (1 << PLAT_QEMU_HOLD_ENTRY_SHIFT) 114 #define PLAT_QEMU_HOLD_STATE_WAIT 0 115 #define PLAT_QEMU_HOLD_STATE_GO 1 116 117 #define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE) 118 #define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) 119 120 /* 121 * BL1 specific defines. 122 * 123 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 124 * addresses. 125 * Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using 126 * the current BL1 RW debug size plus a little space for growth. 127 */ 128 #define BL1_SIZE 0x12000 129 #define BL1_RO_BASE SEC_ROM_BASE 130 #define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE) 131 #define BL1_RW_BASE (BL1_RW_LIMIT - BL1_SIZE) 132 #define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE - \ 133 RME_GPT_DRAM_SIZE) 134 135 /* 136 * BL2 specific defines. 137 * 138 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 139 * size plus a little space for growth. 140 */ 141 #define BL2_SIZE 0x1D000 142 #define BL2_BASE (BL31_BASE - BL2_SIZE) 143 #define BL2_LIMIT BL31_BASE 144 145 /* 146 * BL3-1 specific defines. 147 * 148 * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the 149 * current BL3-1 debug size plus a little space for growth. 150 */ 151 #define BL31_SIZE 0x400000 152 #define BL31_BASE (BL31_LIMIT - BL31_SIZE) 153 #define BL31_LIMIT (BL1_RW_BASE - FW_HANDOFF_SIZE - \ 154 TB_FW_CONFIG_SIZE - TOS_FW_CONFIG_SIZE) 155 #define BL31_PROGBITS_LIMIT BL1_RW_BASE 156 157 #if TRANSFER_LIST 158 #define FW_HANDOFF_BASE BL31_LIMIT 159 #define FW_HANDOFF_LIMIT (FW_HANDOFF_BASE + FW_HANDOFF_SIZE) 160 #define FW_HANDOFF_SIZE 0x4000 161 #else 162 #define FW_HANDOFF_SIZE 0 163 #endif 164 #if TRANSFER_LIST 165 #define FW_NS_HANDOFF_BASE (NS_IMAGE_OFFSET - FW_HANDOFF_SIZE) 166 #endif 167 168 #if defined(SPD_spmd) 169 #define TB_FW_CONFIG_SIZE PAGE_SIZE 170 #else 171 #define TB_FW_CONFIG_SIZE 0 172 #endif 173 174 #if defined(SPD_spmd) && defined(SPMD_SPM_AT_SEL2) 175 #define TOS_FW_CONFIG_SIZE PAGE_SIZE 176 #else 177 #define TOS_FW_CONFIG_SIZE 0 178 #endif 179 180 #define TB_FW_CONFIG_BASE (BL31_LIMIT + FW_HANDOFF_SIZE) 181 #define TB_FW_CONFIG_LIMIT (TB_FW_CONFIG_BASE + TB_FW_CONFIG_SIZE) 182 183 #define TOS_FW_CONFIG_BASE TB_FW_CONFIG_LIMIT 184 #define TOS_FW_CONFIG_LIMIT (TOS_FW_CONFIG_BASE + \ 185 TOS_FW_CONFIG_SIZE) 186 187 /* 188 * BL3-2 specific defines. 189 * 190 * BL3-2 can execute from Secure SRAM, or Secure DRAM. 191 */ 192 #define BL32_SRAM_BASE BL_RAM_BASE 193 #define BL32_SRAM_LIMIT BL2_BASE 194 195 #define BL32_MEM_BASE BL_RAM_BASE 196 #define BL32_MEM_SIZE (BL_RAM_SIZE - RME_GPT_DRAM_SIZE - \ 197 BL1_SIZE - BL2_SIZE - BL31_SIZE - \ 198 FW_HANDOFF_SIZE - TB_FW_CONFIG_SIZE - \ 199 TOS_FW_CONFIG_SIZE) 200 #define BL32_BASE BL32_SRAM_BASE 201 #define BL32_LIMIT BL32_SRAM_LIMIT 202 203 #define NS_IMAGE_OFFSET (NS_DRAM0_BASE + 0x20000000) 204 #define NS_IMAGE_MAX_SIZE (NS_DRAM0_SIZE - 0x20000000) 205 206 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 42) 207 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 42) 208 #if SPM_MM 209 #define MAX_MMAP_REGIONS 13 210 #define MAX_XLAT_TABLES 13 211 #elif ENABLE_RME 212 #define MAX_MMAP_REGIONS 15 213 #define MAX_XLAT_TABLES 15 214 #else 215 #define MAX_MMAP_REGIONS 12 216 #define MAX_XLAT_TABLES 12 217 #endif 218 #define MAX_IO_DEVICES 3 219 #define MAX_IO_HANDLES 4 220 221 #if SPM_MM && defined(IMAGE_BL31) 222 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 223 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 50 224 #endif 225 226 /* 227 * PL011 related constants 228 */ 229 #define UART0_BASE 0x60000000 230 #define UART1_BASE 0x60030000 231 #define UART0_CLK_IN_HZ 1 232 #define UART1_CLK_IN_HZ 1 233 234 /* Secure UART */ 235 #define UART2_BASE 0x60040000 236 #define UART2_CLK_IN_HZ 1 237 238 #define PLAT_QEMU_BOOT_UART_BASE UART0_BASE 239 #define PLAT_QEMU_BOOT_UART_CLK_IN_HZ UART0_CLK_IN_HZ 240 241 #define PLAT_QEMU_CRASH_UART_BASE UART1_BASE 242 #define PLAT_QEMU_CRASH_UART_CLK_IN_HZ UART1_CLK_IN_HZ 243 244 #define PLAT_QEMU_CONSOLE_BAUDRATE 115200 245 246 #define QEMU_FLASH0_BASE 0x00000000 247 #define QEMU_FLASH0_SIZE 0x10000000 248 #define QEMU_FLASH1_BASE 0x10000000 249 #define QEMU_FLASH1_SIZE 0x10000000 250 251 #define PLAT_QEMU_FIP_BASE BL1_SIZE 252 #define PLAT_QEMU_FIP_MAX_SIZE (QEMU_FLASH0_SIZE - BL1_SIZE) 253 254 /* This is map from GIC_DIST up to last CPU (255) GIC_REDISTR */ 255 #define DEVICE0_BASE 0x40000000 256 #define DEVICE0_SIZE 0x04080000 257 /* This is map from NORMAL_UART up to SECURE_UART_MM */ 258 #define DEVICE1_BASE 0x60000000 259 #define DEVICE1_SIZE 0x10041000 260 /* This is a map for SECURE_EC */ 261 #define DEVICE2_BASE 0x50000000 262 #define DEVICE2_SIZE 0x00001000 263 264 /* 265 * GIC related constants 266 * We use GICv3 where CPU Interface registers are not memory mapped 267 * 268 * Legacy values - on platform version 0.1+ they are read from DT 269 */ 270 #define GICD_BASE 0x40060000 271 #define GICR_BASE 0x40080000 272 #define GICC_BASE 0x0 273 274 #define QEMU_IRQ_SEC_SGI_0 8 275 #define QEMU_IRQ_SEC_SGI_1 9 276 #define QEMU_IRQ_SEC_SGI_2 10 277 #define QEMU_IRQ_SEC_SGI_3 11 278 #define QEMU_IRQ_SEC_SGI_4 12 279 #define QEMU_IRQ_SEC_SGI_5 13 280 #define QEMU_IRQ_SEC_SGI_6 14 281 #define QEMU_IRQ_SEC_SGI_7 15 282 283 /****************************************************************************** 284 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 285 * interrupts. 286 *****************************************************************************/ 287 #define PLATFORM_G1S_PROPS(grp) \ 288 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \ 289 grp, GIC_INTR_CFG_EDGE), \ 290 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ 291 grp, GIC_INTR_CFG_EDGE), \ 292 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ 293 grp, GIC_INTR_CFG_EDGE), \ 294 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ 295 grp, GIC_INTR_CFG_EDGE), \ 296 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ 297 grp, GIC_INTR_CFG_EDGE), \ 298 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ 299 grp, GIC_INTR_CFG_EDGE), \ 300 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ 301 grp, GIC_INTR_CFG_EDGE), \ 302 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ 303 grp, GIC_INTR_CFG_EDGE) 304 305 #define PLATFORM_G0_PROPS(grp) 306 307 /* 308 * DT related constants 309 */ 310 #define PLAT_QEMU_DT_BASE NS_DRAM0_BASE 311 #define PLAT_QEMU_DT_MAX_SIZE 0x100000 312 313 #if SPM_MM 314 #define PLAT_QEMU_SP_IMAGE_BASE BL_RAM_BASE 315 #define PLAT_QEMU_SP_IMAGE_SIZE ULL(0x300000) 316 317 #ifdef IMAGE_BL2 318 /* In BL2 all memory allocated to the SPM Payload image is marked as RW. */ 319 # define QEMU_SP_IMAGE_MMAP MAP_REGION_FLAT( \ 320 PLAT_QEMU_SP_IMAGE_BASE, \ 321 PLAT_QEMU_SP_IMAGE_SIZE, \ 322 MT_MEMORY | MT_RW | \ 323 MT_SECURE) 324 #elif IMAGE_BL31 325 /* All SPM Payload memory is marked as code in S-EL0 */ 326 # define QEMU_SP_IMAGE_MMAP MAP_REGION2(PLAT_QEMU_SP_IMAGE_BASE, \ 327 PLAT_QEMU_SP_IMAGE_BASE, \ 328 PLAT_QEMU_SP_IMAGE_SIZE, \ 329 MT_CODE | MT_SECURE | \ 330 MT_USER, \ 331 PAGE_SIZE) 332 #endif 333 334 /* 335 * EL3 -> S-EL0 secure shared memory 336 */ 337 #define PLAT_SPM_BUF_PCPU_SIZE ULL(0x10000) 338 #define PLAT_SPM_BUF_SIZE (PLATFORM_CORE_COUNT * \ 339 PLAT_SPM_BUF_PCPU_SIZE) 340 #define PLAT_SPM_BUF_BASE (BL32_LIMIT - PLAT_SPM_BUF_SIZE) 341 342 #define QEMU_SPM_BUF_EL3_MMAP MAP_REGION_FLAT(PLAT_SPM_BUF_BASE, \ 343 PLAT_SPM_BUF_SIZE, \ 344 MT_RW_DATA | MT_SECURE) 345 346 #define QEMU_SPM_BUF_EL0_MMAP MAP_REGION2(PLAT_SPM_BUF_BASE, \ 347 PLAT_SPM_BUF_BASE, \ 348 PLAT_SPM_BUF_SIZE, \ 349 MT_RO_DATA | MT_SECURE | \ 350 MT_USER, \ 351 PAGE_SIZE) 352 353 /* 354 * Shared memory between Normal world and S-EL0 for 355 * passing data during service requests. It will be marked as RW and NS. 356 * This buffer is allocated at the top of NS_DRAM, the base address is 357 * overridden in SPM initialization. 358 */ 359 #define PLAT_QEMU_SP_IMAGE_NS_BUF_BASE (PLAT_QEMU_DT_BASE + \ 360 PLAT_QEMU_DT_MAX_SIZE) 361 #define PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE ULL(0x200000) 362 363 #define QEMU_SP_IMAGE_NS_BUF_MMAP MAP_REGION2( \ 364 PLAT_QEMU_SP_IMAGE_NS_BUF_BASE, \ 365 PLAT_QEMU_SP_IMAGE_NS_BUF_BASE, \ 366 PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE, \ 367 MT_RW_DATA | MT_NS | \ 368 MT_USER, \ 369 PAGE_SIZE) 370 371 #define PLAT_SP_IMAGE_NS_BUF_BASE PLAT_QEMU_SP_IMAGE_NS_BUF_BASE 372 #define PLAT_SP_IMAGE_NS_BUF_SIZE PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE 373 374 #define PLAT_QEMU_SP_IMAGE_HEAP_BASE (PLAT_QEMU_SP_IMAGE_BASE + \ 375 PLAT_QEMU_SP_IMAGE_SIZE) 376 #define PLAT_QEMU_SP_IMAGE_HEAP_SIZE ULL(0x800000) 377 378 #define PLAT_SP_IMAGE_STACK_BASE (PLAT_QEMU_SP_IMAGE_HEAP_BASE + \ 379 PLAT_QEMU_SP_IMAGE_HEAP_SIZE) 380 #define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x10000) 381 #define QEMU_SP_IMAGE_STACK_TOTAL_SIZE (PLATFORM_CORE_COUNT * \ 382 PLAT_SP_IMAGE_STACK_PCPU_SIZE) 383 384 #define QEMU_SP_IMAGE_RW_MMAP MAP_REGION2( \ 385 PLAT_QEMU_SP_IMAGE_HEAP_BASE, \ 386 PLAT_QEMU_SP_IMAGE_HEAP_BASE, \ 387 (QEMU_SP_IMAGE_STACK_TOTAL_SIZE + \ 388 PLAT_QEMU_SP_IMAGE_HEAP_SIZE), \ 389 MT_RW_DATA | MT_SECURE | \ 390 MT_USER, \ 391 PAGE_SIZE) 392 393 /* 394 * Secure variable storage is located at Secure Flash. 395 */ 396 #if SPM_MM 397 #define QEMU_SECURE_VARSTORE_BASE 0x01000000 398 #define QEMU_SECURE_VARSTORE_SIZE 0x00100000 399 #define MAP_SECURE_VARSTORE MAP_REGION_FLAT( \ 400 QEMU_SECURE_VARSTORE_BASE, \ 401 QEMU_SECURE_VARSTORE_SIZE, \ 402 MT_DEVICE | MT_RW | \ 403 MT_SECURE | MT_USER) 404 #endif 405 406 /* Total number of memory regions with distinct properties */ 407 #define PLAT_QEMU_SP_IMAGE_NUM_MEM_REGIONS 6 408 409 /* 410 * Name of the section to put the translation tables used by the S-EL1/S-EL0 411 * context of a Secure Partition. 412 */ 413 #define PLAT_SP_IMAGE_XLAT_SECTION_NAME ".qemu_sp_xlat_table" 414 #define PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME ".qemu_sp_xlat_table" 415 416 /* Cookies passed to the Secure Partition at boot. Not used by QEMU platforms.*/ 417 #define PLAT_SPM_COOKIE_0 ULL(0) 418 #define PLAT_SPM_COOKIE_1 ULL(0) 419 #endif 420 421 #define QEMU_PRI_BITS 2 422 #define PLAT_SP_PRI 0x20 423 424 #if !ENABLE_RME 425 #define RME_GPT_DRAM_SIZE 0 426 #define NS_DRAM0_BASE_OFFSET 0 427 #else /* !ENABLE_RME */ 428 /* 429 * SBSA RAM starts at 1TB and we support up to 1TB of RAM. As such we 430 * have 2TB of physical address space to cover. Since the GPT size can be 431 * 4GB, 64GB, 1TB, 4TB and so on, we need to select 4GB. Note that it is 432 * possible to support more than 1TB of RAM but that will take more room in 433 * secure memory due to the L1 GPTES. See PLAT_QEMU_L1_GPT_SIZE for details. 434 * 435 * 4TB / 1GB == 4096 GPTEs 436 * 4096 * 8 (bytes per GPTE) == 32768 i.e 8 pages 437 */ 438 #define PLAT_QEMU_L0_GPT_SIZE (8 * PAGE_SIZE) 439 #define PLAT_QEMU_L0_GPT_BASE (PLAT_QEMU_L1_GPT_BASE - \ 440 PLAT_QEMU_L0_GPT_SIZE) 441 442 443 /* 444 * If we have 1TB of RAM and each L1GPT covers 1GB, we need 1024 L1GPTs. With 445 * one more L1GPT to cover the other physical address spaces (see pas_regions[] 446 * in qemu_bl31_setup.c), we need a total of 1025 L1GPTs. Each L1GPT is 131072 447 * bytes, so we need 1025 * 131072 bytes = 0x8020000 of RAM to hold the L1GPTS. 448 */ 449 #define PLAT_QEMU_L1_GPT_SIZE UL(0x08020000) 450 #define PLAT_QEMU_L1_GPT_BASE (BL_RAM_BASE + BL_RAM_SIZE - \ 451 PLAT_QEMU_L1_GPT_SIZE) 452 453 #define RME_GPT_DRAM_BASE PLAT_QEMU_L0_GPT_BASE 454 #define RME_GPT_DRAM_SIZE (PLAT_QEMU_L1_GPT_SIZE + \ 455 PLAT_QEMU_L0_GPT_SIZE) 456 457 #ifndef __ASSEMBLER__ 458 /* L0 table greater than 4KB must be naturally aligned */ 459 CASSERT((PLAT_QEMU_L0_GPT_BASE & (PLAT_QEMU_L0_GPT_SIZE - 1)) == 0, 460 assert_l0_gpt_naturally_aligned); 461 #endif 462 463 /* Reserved some DRAM space for RMM (1072MB) */ 464 #define REALM_DRAM_BASE PLAT_QEMU_DRAM0_BASE 465 #define REALM_DRAM_SIZE 0x43000000 466 467 #define PLAT_QEMU_RMM_SIZE (REALM_DRAM_SIZE - RMM_SHARED_SIZE) 468 #define PLAT_QEMU_RMM_SHARED_SIZE (PAGE_SIZE) /* 4KB */ 469 470 #define RMM_BASE (REALM_DRAM_BASE) 471 #define RMM_LIMIT (RMM_BASE + PLAT_QEMU_RMM_SIZE) 472 #define RMM_SHARED_BASE (RMM_LIMIT) 473 #define RMM_SHARED_SIZE PLAT_QEMU_RMM_SHARED_SIZE 474 475 #define MAP_GPT_L0_REGION MAP_REGION_FLAT( \ 476 PLAT_QEMU_L0_GPT_BASE, \ 477 (PLAT_QEMU_L0_GPT_SIZE), \ 478 MT_MEMORY | MT_RW | EL3_PAS) 479 480 #define MAP_GPT_L1_REGION MAP_REGION_FLAT( \ 481 PLAT_QEMU_L1_GPT_BASE, \ 482 PLAT_QEMU_L1_GPT_SIZE, \ 483 MT_MEMORY | MT_RW | EL3_PAS) 484 /* 485 * We add the RMM_SHARED size to RMM mapping to map the region as a block. 486 * Else we end up requiring more pagetables in BL2 for ROMLIB build. 487 */ 488 #define MAP_RMM_DRAM MAP_REGION_FLAT( \ 489 RMM_BASE, \ 490 (PLAT_QEMU_RMM_SIZE + \ 491 RMM_SHARED_SIZE), \ 492 MT_MEMORY | MT_RW | MT_REALM) 493 494 #define MAP_RMM_SHARED_MEM MAP_REGION_FLAT( \ 495 RMM_SHARED_BASE, \ 496 RMM_SHARED_SIZE, \ 497 MT_MEMORY | MT_RW | MT_REALM) 498 499 /* When RME is enabled, the base of NS DRAM is moved forward after the RMM */ 500 #define NS_DRAM0_BASE_OFFSET REALM_DRAM_SIZE 501 #endif /* !ENABLE_RME */ 502 503 #endif /* PLATFORM_DEF_H */ 504