1 /* 2 * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #include <lib/utils_def.h> 12 #include <plat/arm/board/common/v2m_def.h> 13 #include <plat/arm/common/arm_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/common/common_def.h> 16 17 #include "../fvp_def.h" 18 19 #if TRUSTED_BOARD_BOOT 20 #include MBEDTLS_CONFIG_FILE 21 #endif 22 23 /* Required platform porting definitions */ 24 #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ 25 U(FVP_MAX_CPUS_PER_CLUSTER) * \ 26 U(FVP_MAX_PE_PER_CPU)) 27 28 #define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ 29 PLATFORM_CORE_COUNT + U(1)) 30 31 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 32 33 #if PSCI_OS_INIT_MODE 34 #define PLAT_MAX_CPU_SUSPEND_PWR_LVL ARM_PWR_LVL1 35 #endif 36 37 /* 38 * Other platform porting definitions are provided by included headers 39 */ 40 41 /* 42 * Required ARM standard platform porting definitions 43 */ 44 #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) 45 46 #define PLAT_ARM_TRUSTED_SRAM_SIZE (FVP_TRUSTED_SRAM_SIZE * UL(1024)) 47 48 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 49 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 50 51 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 52 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 53 54 #if ENABLE_RMM 55 #define PLAT_ARM_RMM_BASE (RMM_BASE) 56 #define PLAT_ARM_RMM_SIZE (RMM_LIMIT - RMM_BASE) 57 58 #define PLAT_ARM_RMM_PAYLOAD_SIZE UL(0x600000) /* 2 * 3MB */ 59 60 #endif /* ENABLE_RMM */ 61 62 #if ENABLE_FEAT_RME 63 /* Protected physical address size */ 64 #define PLAT_ARM_PPS (SZ_1T) 65 #endif 66 67 /* 68 * Max size of SPMC is 16MB for fvp. With SPMD enabled this value corresponds to 69 * max size of BL32 image. 70 */ 71 #if defined(SPD_spmd) 72 #define PLAT_ARM_SPMC_BASE PLAT_ARM_TRUSTED_DRAM_BASE 73 #define PLAT_ARM_SPMC_SIZE SZ_16M 74 75 #if BL2_ENABLE_SP_LOAD 76 #define PLAT_ARM_SP_MAX_SIZE (3 * SZ_1M) 77 #endif /* BL2_ENABLE_SP_LOAD */ 78 #endif 79 80 /* Virtual address used by dynamic mem_protect for chunk_base */ 81 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 82 83 /* No SCP in FVP */ 84 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 85 86 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) /* 36-bit range */ 87 #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) /* 30 GB */ 88 89 #define FVP_DRAM3_BASE ULL(0x8800000000) /* 40-bit range */ 90 #define FVP_DRAM3_SIZE ULL(0x7800000000) /* 480 GB */ 91 #define FVP_DRAM3_END (FVP_DRAM3_BASE + FVP_DRAM3_SIZE - 1U) 92 93 #define FVP_DRAM4_BASE ULL(0x88000000000) /* 44-bit range */ 94 #define FVP_DRAM4_SIZE ULL(0x78000000000) /* 7.5 TB */ 95 #define FVP_DRAM4_END (FVP_DRAM4_BASE + FVP_DRAM4_SIZE - 1U) 96 97 #define FVP_DRAM5_BASE ULL(0x880000000000) /* 48-bit range */ 98 #define FVP_DRAM5_SIZE ULL(0x780000000000) /* 120 TB */ 99 #define FVP_DRAM5_END (FVP_DRAM5_BASE + FVP_DRAM5_SIZE - 1U) 100 101 #define FVP_DRAM6_BASE ULL(0x8800000000000) /* 52-bit range */ 102 #define FVP_DRAM6_SIZE ULL(0x7800000000000) /* 1920 TB */ 103 #define FVP_DRAM6_END (FVP_DRAM6_BASE + FVP_DRAM6_SIZE - 1U) 104 105 /* 106 * On the FVP platform when using the EL3 SPMC implementation allocate the 107 * datastore for tracking shared memory descriptors in the TZC DRAM section 108 * to ensure sufficient storage can be allocated. 109 * Provide an implementation of the accessor method to allow the datastore 110 * details to be retrieved by the SPMC. 111 * The SPMC will take care of initializing the memory region. 112 */ 113 114 #define PLAT_SPMC_SHMEM_DATASTORE_SIZE 512 * 1024 115 116 /* Define memory configuration for device tree files. */ 117 #define PLAT_ARM_HW_CONFIG_SIZE U(0x4000) 118 119 #if SPMC_AT_EL3 120 121 /* 122 * Number of Secure Partitions supported. 123 * SPMC at EL3, uses this count to configure the maximum number of supported 124 * secure partitions. 125 */ 126 #define SECURE_PARTITION_COUNT 1 127 128 /* 129 * Number of Normal World Partitions supported. 130 * SPMC at EL3, uses this count to configure the maximum number of supported 131 * NWd partitions. 132 */ 133 #define NS_PARTITION_COUNT 1 134 135 /* 136 * Number of Logical Partitions supported. 137 * SPMC at EL3, uses this count to configure the maximum number of supported 138 * logical partitions. 139 */ 140 #define MAX_EL3_LP_DESCS_COUNT 1 141 142 #endif /* SPMC_AT_EL3 */ 143 144 /* 145 * Load address of BL33 for this platform port 146 */ 147 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) 148 149 #if TRANSFER_LIST 150 151 /* Define maximum size of sp manifest file. */ 152 #if defined(SPD_spmd) 153 #define PLAT_ARM_SPMC_SP_MANIFEST_SIZE SZ_4K 154 155 #if BL2_ENABLE_SP_LOAD 156 /* 157 * TODO: 158 * There is no standard tag_id defined for TB_FW_CONFIG in 159 * the xferlist. As a temporary measure, 160 * use the first value in the non-standard range as 161 * the tag_id for TB_FW_CONFIG in the xferlist. 162 */ 163 #define PLAT_ARM_TB_FW_CONFIG_TL_TAG 0x00fff000 164 #define PLAT_ARM_TB_FW_CONFIG_SIZE SZ_4K 165 166 #else /* !BL2_ENABLE_SP_LOAD */ 167 #define PLAT_ARM_TB_FW_CONFIG_SIZE UL(0x0) 168 #endif /* BL2_ENABLE_SP_LOAD */ 169 170 #else /* !SPD_spmd */ 171 172 #define PLAT_ARM_SPMC_SP_MANIFEST_SIZE UL(0x0) 173 #define PLAT_ARM_TB_FW_CONFIG_SIZE UL(0x0) 174 175 #endif /* SPD_spmd */ 176 177 /* 178 * PLAT_ARM_FW_HANDOFF_SIZE should be page-aligned to ensure proper xlat mapping. 179 * If it is not, generating the page table mapping for FW_HANDOFF will fail. 180 * Because EVENT_LOG_ENTRY_SIZE is not guaranteed to be aligned, 181 * PLAT_ARM_FW_HANDOFF_SIZE must be explicitly aligned. 182 */ 183 #define PLAT_ARM_FW_HANDOFF_SIZE ((((PLAT_ARM_HW_CONFIG_SIZE + \ 184 EVENT_LOG_ENTRY_SIZE + \ 185 PLAT_ARM_TB_FW_CONFIG_SIZE + \ 186 PLAT_ARM_SPMC_SP_MANIFEST_SIZE) + \ 187 PAGE_SIZE_MASK) >> \ 188 PAGE_SIZE_SHIFT) << PAGE_SIZE_SHIFT) 189 190 #define FW_NS_HANDOFF_BASE (PLAT_ARM_NS_IMAGE_BASE - PLAT_ARM_FW_HANDOFF_SIZE) 191 #define PLAT_ARM_EL3_FW_HANDOFF_BASE ARM_BL_RAM_BASE 192 #define PLAT_ARM_EL3_FW_HANDOFF_LIMIT PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE 193 194 #if RESET_TO_BL31 195 #define PLAT_ARM_TRANSFER_LIST_DTB_OFFSET FW_NS_HANDOFF_BASE + TRANSFER_LIST_DTB_OFFSET 196 #define EVENT_LOG_ENTRY_SIZE PLAT_ARM_EVENT_LOG_MAX_SIZE 197 #else 198 /* 199 * The maximum PLAT_ARM_EVENT_LOG_MAX_SIZE for BL2 is SZ_4K 200 * SZ_512 is maximum event log size for BL1. 201 */ 202 #define EVENT_LOG_ENTRY_SIZE (SZ_512 + SZ_4K) 203 #endif 204 205 #else 206 #define PLAT_ARM_FW_HANDOFF_SIZE U(0) 207 #endif 208 209 /* 210 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 211 * plat_arm_mmap array defined for each BL stage. 212 */ 213 #if defined(IMAGE_BL31) 214 # if SPM_MM 215 # define PLAT_ARM_MMAP_ENTRIES 10 216 # define MAX_XLAT_TABLES 9 217 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 218 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 12 219 # elif SPMC_AT_EL3 220 # define PLAT_ARM_MMAP_ENTRIES 13 221 # define MAX_XLAT_TABLES 11 222 # define PLAT_SP_IMAGE_MMAP_REGIONS 31 223 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 13 224 # else 225 # define PLAT_ARM_MMAP_ENTRIES 9 226 # if USE_DEBUGFS 227 # if ENABLE_RMM 228 # define MAX_XLAT_TABLES 9 229 # else 230 # define MAX_XLAT_TABLES 8 231 # endif 232 # else 233 # if ENABLE_RMM 234 # define MAX_XLAT_TABLES 8 235 # elif DRTM_SUPPORT 236 # define MAX_XLAT_TABLES 8 237 # else 238 # define MAX_XLAT_TABLES 7 239 # endif 240 # endif 241 # endif 242 #elif defined(IMAGE_BL32) 243 # if SPMC_AT_EL3 244 # define PLAT_ARM_MMAP_ENTRIES 270 245 # define MAX_XLAT_TABLES 10 246 # else 247 # define PLAT_ARM_MMAP_ENTRIES 9 248 # define MAX_XLAT_TABLES 6 249 # endif 250 #elif !USE_ROMLIB 251 # if defined(IMAGE_BL2) && (ENABLE_RMM || SPMC_AT_EL3) 252 # define PLAT_ARM_MMAP_ENTRIES 12 253 # define MAX_XLAT_TABLES 6 254 # else 255 # define PLAT_ARM_MMAP_ENTRIES 12 256 # define MAX_XLAT_TABLES 5 257 # endif /* (IMAGE_BL2 && ENABLE_RMM) */ 258 #else 259 # define PLAT_ARM_MMAP_ENTRIES 12 260 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 261 defined(IMAGE_BL2) && MEASURED_BOOT 262 # define MAX_XLAT_TABLES 7 263 # else 264 # define MAX_XLAT_TABLES 6 265 # endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && IMAGE_BL2 && MEASURED_BOOT */ 266 #endif 267 268 /* 269 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 270 * plus a little space for growth. 271 * In case of PSA Crypto API, few algorithms like ECDSA needs bigger BL1 RW 272 * area. 273 */ 274 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA || PSA_CRYPTO || \ 275 FVP_TRUSTED_SRAM_SIZE == 512 276 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xD000) 277 #else 278 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 279 #endif 280 281 /* 282 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 283 */ 284 285 #if USE_ROMLIB 286 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 287 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 288 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x5000) 289 #else 290 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 291 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 292 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) 293 #endif 294 295 /* 296 * Set the maximum size of BL2 to be close to half of the Trusted SRAM. 297 * Maximum size of BL2 increases as Trusted SRAM size increases. 298 */ 299 #if (defined(TF_MBEDTLS_KEY_ALG_ID) && \ 300 (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA)) || \ 301 (TRUSTED_BOARD_BOOT && COT_DESC_IN_DTB) 302 # define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ 303 (2 * PAGE_SIZE) - \ 304 FVP_BL2_ROMLIB_OPTIMIZATION) 305 #elif TRUSTED_BOARD_BOOT || MEASURED_BOOT 306 # define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ 307 (3 * PAGE_SIZE) - \ 308 FVP_BL2_ROMLIB_OPTIMIZATION) 309 #elif ARM_BL31_IN_DRAM 310 /* When ARM_BL31_IN_DRAM is set, BL2 can use almost all of Trusted SRAM. */ 311 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - FVP_BL2_ROMLIB_OPTIMIZATION) 312 #else 313 /** 314 * Default to just under half of SRAM to ensure there's enough room for really 315 * large BL31 build configurations when using the default SRAM size (256 Kb). 316 */ 317 #define PLAT_ARM_MAX_BL2_SIZE \ 318 (((PLAT_ARM_TRUSTED_SRAM_SIZE / 3) & ~PAGE_SIZE_MASK) - PAGE_SIZE - \ 319 FVP_BL2_ROMLIB_OPTIMIZATION) 320 #endif 321 322 /* 323 * Enabling CPU library code that requires to set build flags 324 * HW_ASSISTED_COHERENCY=1 and USE_COHERENT_MEM=0 along with RESET_TO_BL2=1 325 * (BL2 in EL3 case) causes increase in resident text size of BL2 beyond 4K. 326 * This is due to FVP including many CPU libs. So set BL2_TEXT_RESIDENT_LIMIT 327 * to 8K. 328 */ 329 #if defined(IMAGE_BL2) && BL2_RUNS_AT_EL3 && SEPARATE_CODE_AND_RODATA 330 #define BL2_TEXT_RESIDENT_LIMIT (SZ_8K) 331 #endif 332 333 #if RESET_TO_BL31 334 /* Size of Trusted SRAM - the first 4KB of shared memory - GPT L0 Tables */ 335 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 336 ARM_SHARED_RAM_SIZE - \ 337 ARM_L0_GPT_SIZE) 338 #else 339 /* 340 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 341 * calculated using the current BL31 PROGBITS debug size plus the sizes of 342 * BL2 and BL1-RW. 343 * Size of the BL31 PROGBITS increases as the SRAM size increases. 344 */ 345 #if TRANSFER_LIST 346 #define PLAT_ARM_MAX_BL31_SIZE \ 347 (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE - \ 348 PLAT_ARM_FW_HANDOFF_SIZE - ARM_L0_GPT_SIZE) 349 #else 350 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 351 ARM_SHARED_RAM_SIZE - \ 352 ARM_FW_CONFIGS_SIZE - ARM_L0_GPT_SIZE) 353 #endif /* TRANSFER_LIST */ 354 #endif /* RESET_TO_BL31 */ 355 356 #ifndef __aarch64__ 357 #if RESET_TO_SP_MIN 358 /* Size of Trusted SRAM - the first 4KB of shared memory */ 359 #define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 360 ARM_SHARED_RAM_SIZE) 361 #else 362 /* 363 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 364 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 365 * BL2 and BL1-RW 366 */ 367 #if TRANSFER_LIST 368 # define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 369 ARM_SHARED_RAM_SIZE - \ 370 PLAT_ARM_FW_HANDOFF_SIZE) 371 #else 372 # define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 373 ARM_SHARED_RAM_SIZE - \ 374 ARM_FW_CONFIGS_SIZE) 375 #endif /* TRANSFER_LIST */ 376 #endif /* RESET_TO_SP_MIN */ 377 #endif 378 379 /* 380 * Size of cacheable stacks 381 */ 382 #if defined(IMAGE_BL1) 383 # if CRYPTO_SUPPORT 384 # define PLATFORM_STACK_SIZE UL(0x1000) 385 # else 386 # define PLATFORM_STACK_SIZE UL(0x500) 387 # endif /* CRYPTO_SUPPORT */ 388 #elif defined(IMAGE_BL2) 389 # if CRYPTO_SUPPORT 390 # define PLATFORM_STACK_SIZE UL(0x1000) 391 # else 392 # define PLATFORM_STACK_SIZE UL(0x600) 393 # endif /* CRYPTO_SUPPORT */ 394 #elif defined(IMAGE_BL2U) 395 # define PLATFORM_STACK_SIZE UL(0x400) 396 #elif defined(IMAGE_BL31) 397 # if DRTM_SUPPORT 398 # define PLATFORM_STACK_SIZE UL(0x1000) 399 # else 400 # define PLATFORM_STACK_SIZE UL(0x800) 401 # endif /* DRTM_SUPPORT */ 402 #elif defined(IMAGE_BL32) 403 # if SPMC_AT_EL3 404 # define PLATFORM_STACK_SIZE UL(0x1000) 405 # else 406 # define PLATFORM_STACK_SIZE UL(0x440) 407 # endif /* SPMC_AT_EL3 */ 408 #elif defined(IMAGE_RMM) 409 # define PLATFORM_STACK_SIZE UL(0x440) 410 #endif 411 412 #define MAX_IO_DEVICES 4 413 #define MAX_IO_HANDLES 4 414 415 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 416 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 417 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 418 419 #if ARM_GPT_SUPPORT && IMAGE_BL1 420 /* 421 * Offset of the FIP in the GPT image. BL1 component uses this option 422 * as it does not load the partition table to get the FIP base 423 * address. At sector 34 by default (i.e. after reserved sectors 0-33) 424 * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 425 */ 426 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 427 #endif /* ARM_GPT_SUPPORT */ 428 429 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 430 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 431 432 /* 433 * PL011 related constants 434 */ 435 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 436 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 437 438 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 439 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 440 441 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 442 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 443 444 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 445 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 446 447 #define PLAT_ARM_TRP_UART_BASE V2M_IOFPGA_UART3_BASE 448 #define PLAT_ARM_TRP_UART_CLK_IN_HZ V2M_IOFPGA_UART3_CLK_IN_HZ 449 450 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 451 #define PLAT_ARM_SMMUV3_ROOT_REG_OFFSET UL(0x20000) 452 453 /* CCI related constants */ 454 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 455 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 456 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 457 458 /* CCI-500/CCI-550 on Base platform */ 459 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 460 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 461 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 462 463 /* CCN related constants. Only CCN 502 is currently supported */ 464 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 465 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 466 467 /* System timer related constants */ 468 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 469 470 /* Mailbox base address */ 471 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 472 473 /* PCIe memory region 1 (Base Platform RevC only) */ 474 #define PLAT_ARM_PCI_MEM_1_BASE (ULL(0x50000000)) 475 #define PLAT_ARM_PCI_MEM_1_SIZE (SZ_256M) /* 256MB */ 476 477 /* 478 * PCIe memory region 2 (Base Platform RevC only) 479 * The full size of the second PCI memory region is 256GB 480 * but for now we only allocate the L1 GPTs for the first 3GB. 481 */ 482 #define PLAT_ARM_PCI_MEM_2_BASE (ULL(0x4000000000)) 483 #define PLAT_ARM_PCI_MEM_2_SIZE (3 * SZ_1G) /* 3GB */ 484 485 /* TrustZone controller related constants 486 * 487 * Currently only filters 0 and 2 are connected on Base FVP. 488 * Filter 0 : CPU clusters (no access to DRAM by default) 489 * Filter 1 : not connected 490 * Filter 2 : LCDs (access to VRAM allowed by default) 491 * Filter 3 : not connected 492 * Programming unconnected filters will have no effect at the 493 * moment. These filter could, however, be connected in future. 494 * So care should be taken not to configure the unused filters. 495 * 496 * Allow only non-secure access to all DRAM to supported devices. 497 * Give access to the CPUs and Virtio. Some devices 498 * would normally use the default ID so allow that too. 499 */ 500 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 501 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 502 503 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 504 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 505 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 506 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 507 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 508 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 509 510 /* 511 * GIC related constants to cater for both GICv2 and GICv3 instances of an 512 * FVP. They could be overridden at runtime in case the FVP implements the 513 * legacy VE memory map. 514 */ 515 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 516 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 517 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 518 519 /* 520 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 521 * terminology. On a GICv2 system or mode, the lists will be merged and treated 522 * as Group 0 interrupts. 523 */ 524 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 525 ARM_G1S_IRQ_PROPS(grp), \ 526 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 527 GIC_INTR_CFG_LEVEL), \ 528 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 529 GIC_INTR_CFG_LEVEL) 530 531 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 532 533 #if SDEI_IN_FCONF 534 #define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT 535 #define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT 536 #else 537 #if PLATFORM_TEST_RAS_FFH || PLATFORM_TEST_FFH_LSP_RAS_SP 538 #define PLAT_ARM_PRIVATE_SDEI_EVENTS \ 539 ARM_SDEI_PRIVATE_EVENTS, \ 540 SDEI_EXPLICIT_EVENT(5000, SDEI_MAPF_NORMAL), \ 541 SDEI_EXPLICIT_EVENT(5001, SDEI_MAPF_NORMAL), \ 542 SDEI_EXPLICIT_EVENT(5002, SDEI_MAPF_NORMAL), \ 543 SDEI_EXPLICIT_EVENT(5003, SDEI_MAPF_CRITICAL), \ 544 SDEI_EXPLICIT_EVENT(5004, SDEI_MAPF_CRITICAL) 545 #else 546 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 547 #endif 548 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 549 #endif 550 551 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SPM_BUF_BASE + \ 552 PLAT_SPM_BUF_SIZE) 553 554 #define PLAT_SP_PRI 0x20 555 556 /* 557 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 558 */ 559 #ifdef __aarch64__ 560 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 561 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 562 #else 563 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 564 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 565 #endif 566 567 /* 568 * Maximum size of Event Log buffer used in Measured Boot Event Log driver 569 * TODO: calculate maximum EventLog size using the calculation: 570 * Maximum size of Event Log * Number of images 571 */ 572 #if defined(IMAGE_BL1) && TRANSFER_LIST 573 #define PLAT_ARM_EVENT_LOG_MAX_SIZE SZ_512 574 #elif (defined(SPD_spmd)) || (ENABLE_RMM && (defined(SPD_tspd) || defined(SPD_opteed))) 575 /* 576 * Account for additional measurements of secure partitions and SPM. 577 * Also, account for OP-TEE running with maximum number of SPs. 578 */ 579 #define PLAT_ARM_EVENT_LOG_MAX_SIZE SZ_4K 580 #elif ENABLE_RMM 581 #define PLAT_ARM_EVENT_LOG_MAX_SIZE SZ_2K 582 #else 583 #define PLAT_ARM_EVENT_LOG_MAX_SIZE SZ_1K 584 #endif 585 586 /* 587 * Maximum size of Event Log buffer used for DRTM 588 */ 589 #define PLAT_DRTM_EVENT_LOG_MAX_SIZE UL(0x300) 590 591 /* 592 * Number of MMAP entries used by DRTM implementation 593 */ 594 #define PLAT_DRTM_MMAP_ENTRIES PLAT_ARM_MMAP_ENTRIES 595 596 #endif /* PLATFORM_DEF_H */ 597