1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ 4 * Andrew F. Davis <afd@ti.com> 5 */ 6 7 #ifndef PLATFORM_CONFIG_H 8 #define PLATFORM_CONFIG_H 9 10 #include <mm/generic_ram_layout.h> 11 12 #define UART0_BASE 0x02800000 13 14 #define CONSOLE_UART_BASE (UART0_BASE + CFG_CONSOLE_UART * 0x10000) 15 #define CONSOLE_BAUDRATE 115200 16 #define CONSOLE_UART_CLK_IN_HZ 48000000 17 18 #define DRAM0_BASE 0x80000000 19 #define DRAM0_SIZE 0x80000000 20 21 #define DRAM1_BASE 0x880000000 22 #define DRAM1_SIZE 0x780000000 23 24 #define SCU_BASE 0x01800000 25 #if defined(PLATFORM_FLAVOR_j721e) || defined(PLATFORM_FLAVOR_j784s4) 26 #define GICC_OFFSET 0x100000 27 #define GICC_SIZE 0x100000 28 #define GICD_OFFSET 0x0 29 #define GICD_SIZE 0x10000 30 #else 31 #define GICC_OFFSET 0x80000 32 #define GICC_SIZE 0x90000 33 #define GICD_OFFSET 0x0 34 #define GICD_SIZE 0x10000 35 #endif 36 #if defined(PLATFORM_FLAVOR_am62lx) 37 #define TI_MAILBOX_SYSC 0x10UL 38 #define TI_MAILBOX_MSG 0x40UL 39 #define TI_MAILBOX_FIFO_STATUS 0x80UL 40 #define TI_MAILBOX_FIFO_LENGTH 0x4UL 41 #define TI_MAILBOX_MSG_STATUS 0xc0UL 42 #define TI_MAILBOX_TX_BASE 0x44241000UL 43 #define TI_MAILBOX_RX_BASE 0x44251000UL 44 #define MAILBOX_TX_START_REGION 0x70814800UL 45 #define MAILBOX_RX_START_REGION 0x70815800UL 46 #define TI_SCI_MAX_MESSAGE_SIZE 60 47 #define TI_MAILBOX_DEFAULT_SIZE 0x1000 48 #elif defined(PLATFORM_FLAVOR_am65x) || defined(PLATFORM_FLAVOR_j721e) || \ 49 defined(PLATFORM_FLAVOR_j784s4) 50 #define SEC_PROXY_DATA_BASE 0x32c00000 51 #define SEC_PROXY_DATA_SIZE 0x100000 52 #define SEC_PROXY_SCFG_BASE 0x32800000 53 #define SEC_PROXY_SCFG_SIZE 0x100000 54 #define SEC_PROXY_RT_BASE 0x32400000 55 #define SEC_PROXY_RT_SIZE 0x100000 56 #define SEC_PROXY_RESPONSE_THREAD 6 57 #define SEC_PROXY_REQUEST_THREAD 7 58 #define TI_SCI_MAX_MESSAGE_SIZE 56 59 #else 60 #define SEC_PROXY_DATA_BASE 0x4d000000 61 #define SEC_PROXY_DATA_SIZE 0x80000 62 #define SEC_PROXY_SCFG_BASE 0x4a400000 63 #define SEC_PROXY_SCFG_SIZE 0x80000 64 #define SEC_PROXY_RT_BASE 0x4a600000 65 #define SEC_PROXY_RT_SIZE 0x80000 66 #define SEC_PROXY_RESPONSE_THREAD 10 67 #define SEC_PROXY_REQUEST_THREAD 11 68 #define TI_SCI_MAX_MESSAGE_SIZE 56 69 #endif 70 #define OPTEE_HOST_ID 11 71 #define SEC_PROXY_TIMEOUT_US 1000000 72 #define GICC_BASE (SCU_BASE + GICC_OFFSET) 73 #define GICD_BASE (SCU_BASE + GICD_OFFSET) 74 75 /* SA2UL */ 76 #if defined(PLATFORM_FLAVOR_am65x) 77 #define SA2UL_BASE 0x04e00000 78 #define SA2UL_TI_SCI_DEV_ID 136 79 #define SA2UL_TI_SCI_FW_ID 2112 80 #define SA2UL_TI_SCI_FW_RGN_ID 0 81 #elif defined(PLATFORM_FLAVOR_j721e) 82 #define SA2UL_BASE 0x40900000 83 #define SA2UL_TI_SCI_DEV_ID 265 84 #define SA2UL_TI_SCI_FW_ID 1196 85 #define SA2UL_TI_SCI_FW_RGN_ID 0 86 #elif defined(PLATFORM_FLAVOR_j784s4) 87 #define SA2UL_BASE 0x40900000 88 #define SA2UL_TI_SCI_DEV_ID -1 89 #define SA2UL_TI_SCI_FW_ID 1196 90 #define SA2UL_TI_SCI_FW_RGN_ID 0 91 #elif defined(PLATFORM_FLAVOR_am64x) 92 #define SA2UL_BASE 0x40900000 93 #define SA2UL_TI_SCI_DEV_ID 133 94 #define SA2UL_TI_SCI_FW_ID 35 95 #define SA2UL_TI_SCI_FW_RGN_ID 0 96 #elif defined(PLATFORM_FLAVOR_am62x) || \ 97 defined(PLATFORM_FLAVOR_am62ax) || \ 98 defined(PLATFORM_FLAVOR_am62px) 99 #define SA2UL_BASE 0x40900000 100 #define SA2UL_TI_SCI_DEV_ID -1 101 #define SA2UL_TI_SCI_FW_ID 66 102 #define SA2UL_TI_SCI_FW_RGN_ID 1 103 #elif defined(PLATFORM_FLAVOR_am62lx) 104 #define DTHEv2_TI_SCI_FW_ID 11 105 #define DTHEv2_TI_SCI_FW_RGN_ID 0 106 #endif 107 #define SA2UL_REG_SIZE 0x1000 108 109 /* RNG */ 110 #if defined(PLATFORM_FLAVOR_am62lx) 111 #define RNG_BASE 0x3B100000 112 #define RNG_REG_SIZE 0x80 113 #elif defined(SA2UL_BASE) 114 #define RNG_BASE (SA2UL_BASE + 0x10000) 115 #define RNG_REG_SIZE 0x1000 116 #elif !defined(CFG_WITH_SOFTWARE_PRNG) 117 /* 118 * If we got here we're trying to build a hardware based RNG driver 119 * but are missing some crticial definitions. This is usually because 120 * we're using the wrong platform flavor. 121 */ 122 #error "Unknown platform flavor! No base address is defined for RNG" 123 #endif 124 125 /* Firewall bitmaps */ 126 #define FW_ENABLE_REGION 0x0a 127 #define FW_BACKGROUND_REGION BIT(8) 128 #define FW_TIFS_PRIVID 0xca 129 #define FW_WILDCARD_PRIVID 0xc3 130 #define FW_SECURE_ONLY GENMASK_32(7, 0) 131 #define FW_NON_SECURE GENMASK_32(15, 0) 132 #if defined(PLATFORM_FLAVOR_am62lx) 133 #define FW_BIG_ARM_PRIVID 0x04 134 #else 135 #define FW_BIG_ARM_PRIVID 0x01 136 #endif 137 138 #if defined(PLATFORM_FLAVOR_am62x) || \ 139 defined(PLATFORM_FLAVOR_am62ax) || \ 140 defined(PLATFORM_FLAVOR_am62px) 141 #define RNG_TI_SCI_FW_RGN_ID 2 142 #else 143 #define RNG_TI_SCI_FW_RGN_ID 3 144 #endif 145 146 /* Make stacks aligned to data cache line length */ 147 #define STACK_ALIGNMENT 64 148 149 #endif /*PLATFORM_CONFIG_H*/ 150