1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd
4 */
5
6 #include <common.h>
7 #include <spl.h>
8 #include <asm/io.h>
9 #include <asm/arch/cpu.h>
10 #include <asm/arch/hardware.h>
11 #include <asm/arch/ioc_rk3588.h>
12 #include <dt-bindings/clock/rk3588-cru.h>
13 #include <pci.h>
14 #include <asm/arch/rk_atags.h>
15
16 #ifndef CONFIG_SPL_LOAD_FIT_ADDRESS
17 #error "SPL_LOAD_FIT_ADDRESS not defined!"
18 #endif
19
20 #define printep(fmt, ...) \
21 do { \
22 printf("RKEP: %d - ", readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x2c) / 24); \
23 printf(fmt, ##__VA_ARGS__); \
24 } while (0)
25
26 #ifdef CONFIG_ROCKCHIP_RK3588
27 #define PCIE_SNPS_DBI_BASE 0xf5000000
28 #define PCIE_SNPS_APB_BASE 0xfe150000
29 #define PCIE_SNPS_IATU_BASE 0xa40300000
30
31 #define PCI_RESBAR 0x2e8
32 #elif CONFIG_ROCKCHIP_RK3568
33 #define PCIE_SNPS_DBI_BASE 0xf6000000
34 #define PCIE_SNPS_APB_BASE 0xfe280000
35 #define PCIE_SNPS_IATU_BASE 0x3c0b00000
36
37 #define PCI_RESBAR 0x2b8
38 #else
39 #error "this soc is not support pcie ep!"
40 #endif
41
42 #define RKEP_BAR0_ADDR 0x3c000000
43 #define RKEP_BAR2_ADDR CONFIG_SPL_LOAD_FIT_ADDRESS
44 #define RKEP_BAR0_CMD_ADDR (RKEP_BAR0_ADDR + 0x400)
45 #define RKEP_BOOT_MAGIC 0x524b4550 /* RKEP */
46 #define RKEP_CMD_LOADER_RUN 0x524b4501
47
48 #define PCI_EXP_LNKCAP 12 /* Link Capabilities */
49 #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
50 #define PCI_EXP_LNKCTL2_TLS 0x000f
51 #define PCI_EXP_LNKCAP_SLS 0x0000000f
52
53 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */
54 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */
55 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
56
57 /* Synopsys-specific PCIe configuration registers */
58 #define PCIE_PORT_LINK_CONTROL 0x710
59 #define PORT_LINK_MODE_MASK (0x3f << 16)
60 #define PORT_LINK_MODE_1_LANES (0x1 << 16)
61 #define PORT_LINK_MODE_2_LANES (0x3 << 16)
62 #define PORT_LINK_MODE_4_LANES (0x7 << 16)
63 #define PORT_LINK_MODE_8_LANES (0xf << 16)
64
65 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
66 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
67 #define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
68 #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
69 #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
70 #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
71 #define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)
72
73 #define PCIE_DIRECT_SPEED_CHANGE (0x1 << 17)
74
75 #define LINK_WAIT_IATU 10000
76 #define PCIE_ATU_ENABLE (0x1 << 31)
77 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30 | 1 << 19)
78 #define PCIE_ATU_UNR_REGION_CTRL1 0x00
79 #define PCIE_ATU_UNR_REGION_CTRL2 0x04
80 #define PCIE_ATU_CPU_ADDR_LOW 0x14
81 #define PCIE_ATU_CPU_ADDR_HIGH 0x18
82
83 /* SRNS: Use Separate refclk(internal clock) instead of from RC */
84 // #define PCIE_ENABLE_SRNS_PLL_REFCLK
85
86 struct rkpcie_cmd {
87 u32 cmd;
88 u32 size;
89 u32 data[6];
90 };
91
92 /* rkep device mode status definition */
93 #define RKEP_MODE_BOOTROM 1
94 #define RKEP_MODE_LOADER 2
95 #define RKEP_MODE_KERNEL 3
96
97 /* Common status */
98 #define RKEP_SMODE_INIT 0
99 #define RKEP_SMODE_LNKRDY 1
100 #define RKEP_SMODE_LNKUP 2
101 #define RKEP_SMODE_ERR 0xff
102 /* Firmware download status */
103 #define RKEP_SMODE_FWDLRDY 0x10
104 #define RKEP_SMODE_FWDLDONE 0x11
105 /* Application status*/
106 #define RKEP_SMODE_APPRDY 0x20
107
108 struct rkpcie_boot {
109 /* magic: "RKEP" */
110 u32 magic;
111 u32 version;
112 struct {
113 u16 mode;
114 u16 submode;
115 } devmode;
116 /* Size of ATAGS for cap */
117 u32 cap_size;
118 struct {
119 u8 cmd;
120 u8 status;
121 /* Error code for current CMD */
122 u16 opcode;
123 } cmd_status;
124 u32 reserved[2];
125 /* RK ATAGS, for mem and other info */
126 struct tag cap;
127 /* offset 0x400 */
128 struct rkpcie_cmd cmd;
129 };
130
pcie_inbound_config(void)131 static void pcie_inbound_config(void)
132 {
133 u64 base = PCIE_SNPS_IATU_BASE + 0x100;
134 u32 val;
135 char i;
136
137 /* BAR0: RKEP_BAR0_ADDR */
138 writel(RKEP_BAR0_ADDR, base + PCIE_ATU_CPU_ADDR_LOW);
139 writel(0, base + PCIE_ATU_CPU_ADDR_HIGH);
140 writel(0, base + PCIE_ATU_UNR_REGION_CTRL1);
141 /* PCIE_ATU_UNR_REGION_CTRL2 */
142 writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE | (0 << 8),
143 base + PCIE_ATU_UNR_REGION_CTRL2);
144 for (i = 0; i < 5; i++) {
145 val = readl(base + PCIE_ATU_UNR_REGION_CTRL2);
146 if (val & PCIE_ATU_ENABLE)
147 break;
148 udelay(LINK_WAIT_IATU);
149 }
150 printep("BAR0: 0x%x\n", RKEP_BAR0_ADDR);
151
152 /* BAR2: RKEP_BAR2_ADDR */
153 writel(RKEP_BAR2_ADDR, base + PCIE_ATU_CPU_ADDR_LOW + 0x200);
154 writel(0, base + PCIE_ATU_CPU_ADDR_HIGH + 0x200);
155 writel(0, base + PCIE_ATU_UNR_REGION_CTRL1 + 0x200);
156 writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE | (2 << 8),
157 base + PCIE_ATU_UNR_REGION_CTRL2 + 0x200);
158 for (i = 0; i < 5; i++) {
159 val = readl(base + PCIE_ATU_UNR_REGION_CTRL2 + 0x200);
160 if (val & PCIE_ATU_ENABLE)
161 break;
162 udelay(LINK_WAIT_IATU);
163 }
164 printep("BAR2: 0x%x%x\n", 0, RKEP_BAR2_ADDR);
165
166 /* BAR4 is wired reg, no need iATU */
167 }
168
rockchip_pcie_ep_set_bar_flag(void * dbi_base,u32 barno,int flags)169 static int rockchip_pcie_ep_set_bar_flag(void *dbi_base, u32 barno, int flags)
170 {
171 u32 reg;
172
173 reg = PCI_BASE_ADDRESS_0 + (4 * barno);
174
175 /* Disabled the upper 32bits BAR to make a 64bits bar pair */
176 if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
177 writel(0, dbi_base + reg + 0x100000 + 4);
178
179 writel(flags, dbi_base + reg);
180 if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
181 writel(0, dbi_base + reg + 4);
182
183 return 0;
184 }
185
pcie_bar_init(void * dbi_base)186 static void pcie_bar_init(void *dbi_base)
187 {
188 void *resbar_base;
189 u32 val;
190
191 writel(0, dbi_base + 0x10);
192 writel(0, dbi_base + 0x14);
193 writel(0, dbi_base + 0x18);
194 writel(0, dbi_base + 0x1c);
195 writel(0, dbi_base + 0x20);
196 writel(0, dbi_base + 0x24);
197
198 /* Disable ASPM */
199 val = readl(dbi_base + 0x7c);
200 val &= ~(3 << 10);
201 writel(val, dbi_base + 0x7c);
202
203 /* Resize BAR0 to support 4M 32bits */
204 resbar_base = dbi_base + PCI_RESBAR;
205 writel(0x40, resbar_base + 0x4);
206 writel(0x2c0, resbar_base + 0x8);
207 /* BAR2: 64M 64bits */
208 writel(0x400, resbar_base + 0x14);
209 writel(0x6c0, resbar_base + 0x18);
210 /* BAR4: Fixed for EP wired register, 1M 32bits */
211 writel(0x10, resbar_base + 0x24);
212 writel(0xc0, resbar_base + 0x28);
213 /* Set flags */
214 rockchip_pcie_ep_set_bar_flag(dbi_base, 0, PCI_BASE_ADDRESS_MEM_TYPE_32);
215 rockchip_pcie_ep_set_bar_flag(dbi_base, 2,
216 PCI_BASE_ADDRESS_MEM_PREFETCH | PCI_BASE_ADDRESS_MEM_TYPE_64);
217 rockchip_pcie_ep_set_bar_flag(dbi_base, 4, PCI_BASE_ADDRESS_MEM_TYPE_32);
218
219 /* Close bar1 bar5 */
220 writel(0x0, dbi_base + 0x100000 + 0x14);
221 //writel(0x0, dbi_base + 0x100000 + 0x18);
222 //writel(0x0, dbi_base + 0x100000 + 0x1c);
223 //writel(0x0, dbi_base + 0x100000 + 0x20);
224 writel(0x0, dbi_base + 0x100000 + 0x24);
225 /* Close ROM BAR */
226 writel(0x0, dbi_base + 0x100000 + 0x30);
227 }
228
pcie_bar0_header_init(void)229 static void pcie_bar0_header_init(void)
230 {
231 struct rkpcie_boot *bh = (struct rkpcie_boot *)RKEP_BAR0_ADDR;
232
233 bh->magic = RKEP_BOOT_MAGIC;
234 bh->version = 0x100;
235 bh->devmode.mode = RKEP_MODE_LOADER;
236 bh->devmode.submode = RKEP_SMODE_INIT;
237 bh->cap_size = 0;
238
239 memset((char *)RKEP_BAR0_CMD_ADDR, 0, sizeof(struct rkpcie_cmd));
240 }
241
pcie_link_set_max_speed(void * dbi_base,u32 link_gen)242 static void pcie_link_set_max_speed(void *dbi_base, u32 link_gen)
243 {
244 u32 cap, ctrl2, link_speed;
245 u8 offset = 0x70;
246
247 cap = readl(dbi_base + offset + PCI_EXP_LNKCAP);
248 ctrl2 = readl(dbi_base + offset + PCI_EXP_LNKCTL2);
249 ctrl2 &= ~PCI_EXP_LNKCTL2_TLS;
250
251 link_speed = link_gen;
252
253 cap &= ~((u32)PCI_EXP_LNKCAP_SLS);
254 writel(ctrl2 | link_speed, dbi_base + offset + PCI_EXP_LNKCTL2);
255 writel(cap | link_speed, dbi_base + offset + PCI_EXP_LNKCAP);
256 }
257
pcie_link_set_lanes(void * dbi_base,u32 lanes)258 static void pcie_link_set_lanes(void *dbi_base, u32 lanes)
259 {
260 u32 val;
261
262 /* Set the number of lanes */
263 val = readl(dbi_base + PCIE_PORT_LINK_CONTROL);
264 val &= ~PORT_LINK_MODE_MASK;
265 switch (lanes) {
266 case 1:
267 val |= PORT_LINK_MODE_1_LANES;
268 break;
269 case 2:
270 val |= PORT_LINK_MODE_2_LANES;
271 break;
272 case 4:
273 val |= PORT_LINK_MODE_4_LANES;
274 break;
275 default:
276 printf("RKEP: num-lanes %u: invalid value\n", lanes);
277 return;
278 }
279 writel(val, dbi_base + PCIE_PORT_LINK_CONTROL);
280
281 /* Set link width speed control register */
282 val = readl(dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
283 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
284 switch (lanes) {
285 case 1:
286 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
287 break;
288 case 2:
289 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
290 break;
291 case 4:
292 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
293 break;
294 }
295
296 val |= PCIE_DIRECT_SPEED_CHANGE;
297
298 writel(val, dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
299 }
300
pcie_devmode_update(int mode,int submode)301 static void pcie_devmode_update(int mode, int submode)
302 {
303 struct rkpcie_boot *bh = (struct rkpcie_boot *)RKEP_BAR0_ADDR;
304
305 bh->devmode.mode = mode;
306 bh->devmode.submode = submode;
307 flush_dcache_range(RKEP_BAR0_ADDR, RKEP_BAR0_ADDR + 64);
308 }
309
310 #ifdef CONFIG_SPL_RAM_DEVICE
pcie_wait_for_fw(void)311 static void pcie_wait_for_fw(void)
312 {
313 struct rkpcie_cmd *cmd = (struct rkpcie_cmd *)(RKEP_BAR0_CMD_ADDR);
314 int val;
315 int i = 0;
316
317 printep("Link ready! Waiting RC to download Firmware:\n");
318 printep("Download uboot.img to BAR2+0\n");
319 printep("Download boot.img to BAR2+0x400000\n");
320 printep("Send CMD_LOADER_RUN to BAR0+0x400\n");
321 while (1) {
322 invalidate_dcache_range(RKEP_BAR0_CMD_ADDR,
323 RKEP_BAR0_CMD_ADDR + 32);
324 val = readl(&cmd->cmd);
325 if (val == RKEP_CMD_LOADER_RUN)
326 break;
327 i++;
328 if (!(i % 10))
329 printep("Waiting for FW, CMD: %x\n", val);
330 mdelay(100);
331 }
332 /* Invalidate Cache for firmware area: BAR2, 64MB */
333 invalidate_dcache_range(RKEP_BAR2_ADDR, RKEP_BAR2_ADDR + 0x4000000);
334 printep("Firmware Download complete!\n");
335 }
336
pcie_update_atags(void)337 static void pcie_update_atags(void)
338 {
339 struct tag_ram_partition t_ram_part;
340
341 if (!atags_is_available()) {
342 printep("RKEP: No ATAGS data found, create new!\n");
343 atags_destroy();
344 }
345
346 /* ram partition */
347 memset(&t_ram_part, 0, sizeof(t_ram_part));
348 t_ram_part.version = 0;
349 t_ram_part.count = 1;
350 strcpy(t_ram_part.part[0].name, "boot");
351 t_ram_part.part[0].start = RKEP_BAR2_ADDR + 0x400000; /* 4M offset */
352 t_ram_part.part[0].size = 0x3c00000; /* 60M size */
353 atags_set_tag(ATAG_RAM_PARTITION, &t_ram_part);
354 }
355
rockchip_pcie_ep_get_firmware(void)356 void rockchip_pcie_ep_get_firmware(void)
357 {
358 pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_FWDLRDY);
359 pcie_wait_for_fw();
360 pcie_update_atags();
361 pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_FWDLDONE);
362 }
363 #endif
364
365 #ifdef CONFIG_ROCKCHIP_RK3588
366 #define BUS_IOC_GPIO3D_IOMUX_SEL_H 0xfd5f807c
367 #define GPIO3_BASE 0xfec40000
368 #define GPIO3_SWPORT_DR_H (GPIO3_BASE + 0x4)
369 #define GPIO3_SWPORT_DDR_H (GPIO3_BASE + 0xc)
370
pcie_board_init(void)371 static void pcie_board_init(void)
372 {
373 /* Enable AU5426 buffer chip on EVB4v10 */
374 /* Set GPIO3D4 to gpio output HIGH mode PCIE20_CLK_PWREN */
375 writel(0xf << 16, BUS_IOC_GPIO3D_IOMUX_SEL_H);
376 writel(0x10001000, GPIO3_SWPORT_DDR_H);
377 writel(0x10001000, GPIO3_SWPORT_DR_H);
378 udelay(100);
379 }
380
381 #define PHY_MODE_PCIE_AGGREGATION 4 /* PCIe3x4 */
382 #define PHY_MODE_PCIE_NANBNB 0 /* P1:PCIe3x2 + P0:PCIe3x2 */
383 #define PHY_MODE_PCIE_NANBBI 1 /* P1:PCIe3x2 + P0:PCIe3x1*2 */
384 #define PHY_MODE_PCIE_NABINB 2 /* P1:PCIe3x1*2 + P0:PCIe3x2 */
385 #define PHY_MODE_PCIE_NABIBI 3 /* P1:PCIe3x1*2 + P0:PCIe3x1*2 */
386
387 #define PHY_MODE_PCIE PHY_MODE_PCIE_AGGREGATION
388
389 #define CRU_BASE_ADDR 0xfd7c0000
390 #define CRU_SOFTRST_CON32 (CRU_BASE_ADDR + 0x0a80)
391 #define CRU_SOFTRST_CON33 (CRU_BASE_ADDR + 0x0a84)
392 #define CRU_SOFTRST_CON34 (CRU_BASE_ADDR + 0x0a88)
393 #define CRU_GATE_CON32 (CRU_BASE_ADDR + 0x0880)
394 #define CRU_GATE_CON33 (CRU_BASE_ADDR + 0x0884)
395 #define CRU_GATE_CON34 (CRU_BASE_ADDR + 0x0888)
396 #define CRU_GATE_CON38 (CRU_BASE_ADDR + 0x0898)
397 #define CRU_GATE_CON39 (CRU_BASE_ADDR + 0x089c)
398 #define PHPTOPCRU_BASE_ADDR 0xfd7c8000
399 #define PHPTOPCRU_SOFTRST_CON00 (PHPTOPCRU_BASE_ADDR + 0x0a00)
400 #define PHPTOPCRU_GATE_CON00 (PHPTOPCRU_BASE_ADDR + 0x0800)
401 #define PCIE3PHY_GRF_BASE 0xfd5b8000
402 #define RK3588_PCIE3PHY_GRF_CMN_CON0 (PCIE3PHY_GRF_BASE + 0x0000)
403 #define PCIE3PHY_GRF_PHY0_CON6 (PCIE3PHY_GRF_BASE + 0x0118)
404 #define PCIE3PHY_GRF_PHY1_CON6 (PCIE3PHY_GRF_BASE + 0x0218)
405 #define PCIE3PHY_GRF_PHY0_LN0_CON1 (PCIE3PHY_GRF_BASE + 0x1004)
406 #define PCIE3PHY_GRF_PHY0_LN1_CON1 (PCIE3PHY_GRF_BASE + 0x1104)
407 #define PCIE3PHY_GRF_PHY1_LN0_CON1 (PCIE3PHY_GRF_BASE + 0x2004)
408 #define PCIE3PHY_GRF_PHY1_LN1_CON1 (PCIE3PHY_GRF_BASE + 0x2104)
409 #define FIREWALL_PCIE_MASTER_SEC 0xfe0300f0
410 #define FIREWALL_PCIE_ACCESS 0xfd586040
411 #define CRU_PHYREF_ALT_GATE_CON (CRU_BASE_ADDR + 0x0c38)
412 #define PMU1_GRF_BASE 0xfd58a000
413 #define PMU_PWR_GATE_SFTCON1 0xfd8d8150
414 #define PMU1_IOC_BASE 0xfd5F0000
415 #define CRU_GLB_RST_CON_OFFSET (0xC10U)
416 #define CRU_GLB_SRST_FST_VALUE_OFFSET (0xC08U)
417
418 #define RK3588_SRAM_INIT_DONE(reg) ((reg & 0xf) == 0xf)
419
pcie_first_reset(void)420 void pcie_first_reset(void)
421 {
422 printep("Fst Reset\n");
423 mdelay(1);
424
425 writel(0xFFDF, CRU_BASE_ADDR + CRU_GLB_RST_CON_OFFSET);
426 writel(0xffffffff, PMU1_GRF_BASE + 0x4); // reset width
427 writel(0x30003000, PMU1_GRF_BASE + 0x1c); // pmu1_grf pmu1_ioc hiold
428 writel(0x00f00020, PMU1_IOC_BASE + 0x0); //select tsad_shut_m0 iomux
429 writel(0xFDB9, CRU_BASE_ADDR + CRU_GLB_SRST_FST_VALUE_OFFSET);
430
431 while (1)
432 ;
433 }
434
pcie_cru_init(void)435 static void pcie_cru_init(void)
436 {
437 u32 phy0_mplla, phy1_mplla, t0 = 0, t1 = 0;
438 u32 i, timeout = 500;
439
440 /* Enable power domain: PD_PCIE & PD_PHP */
441 writel(0x1 << 23 | 0x1 << 21, PMU_PWR_GATE_SFTCON1);
442
443 /* FixMe init 3.0 PHY */
444 /* Phy mode: Aggregation NBNB */
445 writel((0x7 << 16) | PHY_MODE_PCIE, RK3588_PCIE3PHY_GRF_CMN_CON0);
446 printep("PHY Mode 0x%x\n", readl(RK3588_PCIE3PHY_GRF_CMN_CON0) & 7);
447 /* Enable clock and sfreset for Controller and PHY */
448 writel(0xFFFC0000, CRU_SOFTRST_CON33);
449 writel(0xffff0000, CRU_SOFTRST_CON34);
450 writel(0xffff0000, CRU_GATE_CON32);
451 writel(0xffff0000, CRU_GATE_CON33);
452 writel(0xffff0000, CRU_GATE_CON34);
453 writel(0xffff0000, CRU_GATE_CON38);
454 writel(0xffff0000, CRU_GATE_CON39);
455
456 writel((0x1 << 24), PHPTOPCRU_SOFTRST_CON00);
457 writel(0xffff0000, PHPTOPCRU_GATE_CON00);
458
459 /* PHY Reset */
460 writel((0x1 << 10) | (0x1 << 26), PHPTOPCRU_SOFTRST_CON00);
461
462 udelay(1);
463
464 #ifdef PCIE_ENABLE_SRNS_PLL_REFCLK
465 writel(0x000f0000, CRU_PHYREF_ALT_GATE_CON);
466
467 /* PHY0 & PHY1 use internal clock */
468 writel(0x0 | (0x1 << 18), PCIE3PHY_GRF_PHY0_CON6);
469 writel(0x0 | (0x1 << 18), PCIE3PHY_GRF_PHY1_CON6);
470
471 /* phy0_rx0_cmn_refclk_mod */
472 writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY0_LN0_CON1);
473 /* phy1_rx0_cmn_refclk_mod */
474 writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY0_LN1_CON1);
475 /* phy0_rx0_cmn_refclk_mod */
476 writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY1_LN0_CON1);
477 /* phy1_rx0_cmn_refclk_mod */
478 writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY1_LN1_CON1);
479 #endif
480
481 udelay(1000);
482
483 /* Deassert PCIe PMA output clamp mode */
484 writel((0x1 << 8) | (0x1 << 24), RK3588_PCIE3PHY_GRF_CMN_CON0);
485
486 /* Deassert PHY Reset */
487 writel((0x1 << 26), PHPTOPCRU_SOFTRST_CON00);
488 udelay(10);
489
490 /* release resetn_pcie_4l_power_up */
491 writel(0x20000000, CRU_SOFTRST_CON32);
492 udelay(10);
493
494 /* S-Phy: waiting for phy locked */
495 for (i = 0; i < timeout; i++) {
496 phy0_mplla = readl(PCIE3PHY_GRF_BASE + 0x904);
497 phy1_mplla = readl(PCIE3PHY_GRF_BASE + 0xA04);
498
499 if (phy0_mplla != t0 || phy1_mplla != t1) {
500 printep("RKEP: GRF:904=%x, a04=%x...\n", phy0_mplla, phy1_mplla);
501
502 t0 = phy0_mplla;
503 t1 = phy1_mplla;
504
505 if (RK3588_SRAM_INIT_DONE(phy0_mplla)) {
506 if (PHY_MODE_PCIE == PHY_MODE_PCIE_AGGREGATION && RK3588_SRAM_INIT_DONE(phy1_mplla))
507 break;
508 else
509 break;
510 }
511 }
512
513 udelay(10);
514 }
515
516 if (i >= timeout) {
517 printep("lock fail\n");
518 mdelay(1);
519 pcie_first_reset();
520 }
521
522 /* PHY config: no config need for snps3.0phy */
523 }
524
pcie_firewall_init(void)525 static void pcie_firewall_init(void)
526 {
527 /* Enable PCIe Access in firewall and master secure mode */
528 writel(0xffff0000, FIREWALL_PCIE_MASTER_SEC);
529 writel(0x03000000, FIREWALL_PCIE_ACCESS);
530 }
531 #elif CONFIG_ROCKCHIP_RK3568
532
pcie_board_init(void)533 static void pcie_board_init(void)
534 {
535 /* to-do */
536 }
537
538 static const u16 phy_fw[] = {
539 #include "./../../../drivers/phy/phy-rockchip-snps-pcie3.fw"
540 };
541
542 #define GRF_PCIE30PHY_RK3568_CON1 0x4
543 #define GRF_PCIE30PHY_RK3568_CON3 0xC
544 #define GRF_PCIE30PHY_RK3568_CON4 0x10
545 #define GRF_PCIE30PHY_RK3568_CON5 0x14
546 #define GRF_PCIE30PHY_RK3568_CON6 0x18
547 #define GRF_PCIE30PHY_RK3568_CON9 0x24
548 #define GRF_PCIE30PHY_RK3568_STATUS0 0x80
549 #define RK3568_SRAM_INIT_DONE(reg) ((reg) & BIT(14))
550
551 #define PMUCRU_BASE 0xFDD00000
552 #define PMUCRU_PMUGATE_CON02 (PMUCRU_BASE + 0x188)
553
554 #define CRU_BASE 0xFDD20000
555 #define CRU_GATE_CON12 (CRU_BASE + 0x330)
556 #define CRU_GATE_CON13 (CRU_BASE + 0x334)
557 #define CRU_GATE_CON33 (CRU_BASE + 0x384)
558 #define CRU_SOFTRST_CON12 (CRU_BASE + 0x430)
559 #define CRU_SOFTRST_CON27 (CRU_BASE + 0x46c)
560 #define CRU_GLB_SRST_FST_OFFSET (0xD4U)
561
562 #define PCIE30_PHY_GRF 0xFDCB8000
563
564 #define SYS_GRF_BASE 0xFDC60000
565
pcie_first_reset(void)566 void pcie_first_reset(void)
567 {
568 printep("Fst Reset\n");
569 mdelay(1);
570
571 writel(0x00040004, CRU_BASE + 0x104);
572 writel(0x00700010, CRU_BASE);
573 writel(0x00100010, SYS_GRF_BASE + 0x508);
574 writel(0xFDB9, CRU_BASE + CRU_GLB_SRST_FST_OFFSET);
575
576 while (1)
577 ;
578 }
579
pcie_cru_init(void)580 void pcie_cru_init(void)
581 {
582 u32 i, reg, timeout = 500;
583 void __iomem *mmio = (void __iomem *)0xFE8C0000;
584 u32 phy0_status0, phy0_status1, t0 = 0, t1 = 0;
585
586 /* Enable phy and controoler clk */
587 writel(0xffff0000, PMUCRU_PMUGATE_CON02);
588 writel(0xffff0000, CRU_GATE_CON12);
589 writel(0xffff0000, CRU_GATE_CON13);
590 writel(0xffff0000, CRU_GATE_CON33);
591 writel(0xffff0000, CRU_SOFTRST_CON27);
592
593 writel(0x40004000, CRU_SOFTRST_CON27);
594 writel(0x80008000, PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9);
595
596 writel((0x1 << 15) | (0x1 << 31),
597 PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9); //map to access sram
598
599 #ifdef PCIE_ENABLE_SRNS_PLL_REFCLK
600 /* use internal clock */
601 writel(0x0 | (0x1 << 31), PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON3);
602
603 /* rx0_cmn_refclk_mode disabled */
604 writel((0x0) | (0x1 << 25), PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON5);
605 /* rx1_cmn_refclk_mode disabled */
606 writel((0x0) | (0x1 << 25), PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON6);
607 #endif
608
609 writel((0x0 << 14) | (0x1 << (14 + 16)),
610 PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON4); //sdram_ld_done
611 writel((0x0 << 13) | (0x1 << (13 + 16)),
612 PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON4); //sdram_bypass
613
614 writel(0x40000000, CRU_SOFTRST_CON27);
615
616 udelay(5);
617 printep("RKEP: sram initial\n");
618 while (1) {
619 reg = readl(PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_STATUS0);
620 if (RK3568_SRAM_INIT_DONE(reg))
621 break;
622 }
623 printep("RKEP: sram init done\n");
624
625 writel((0x3 << 8) | (0x3 << (8 + 16)),
626 PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9); //map to access sram
627 for (i = 0; i < ARRAY_SIZE(phy_fw); i++)
628 writel(phy_fw[i], mmio + (i << 2));
629
630 printep("RKEP: snps pcie3phy FW update! size %ld\n", ARRAY_SIZE(phy_fw));
631 writel((0x0 << 8) | (0x3 << (8 + 16)),
632 PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9);
633 writel((0x1 << 14) | (0x1 << (14 + 16)),
634 PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON4); //sdram_ld_done
635
636 writel(0xffff0000, CRU_SOFTRST_CON12);
637 writel(0x100010, PCIE_SNPS_APB_BASE + 0x180);
638
639 /* S-Phy: waiting for phy locked */
640 for (i = 0; i < timeout; i++) {
641 phy0_status0 = readl(PCIE30_PHY_GRF + 0x80);
642 phy0_status1 = readl(PCIE30_PHY_GRF + 0x84);
643
644 if (phy0_status0 != t0 || phy0_status1 != t1) {
645 printep("RKEP: GRF:0x80=%x, 0x84=%x...\n", phy0_status0, phy0_status1);
646
647 t0 = phy0_status0;
648 t1 = phy0_status1;
649 if (RK3568_SRAM_INIT_DONE(phy0_status0))
650 break;
651 }
652
653 udelay(10);
654 }
655
656 if (i >= timeout) {
657 printep("lock fail\n");
658 mdelay(1);
659 pcie_first_reset();
660 }
661
662 udelay(1);
663 }
664
pcie_firewall_init(void)665 static void pcie_firewall_init(void)
666 {
667 }
668 #endif
669
pcie_ep_init(void)670 static void pcie_ep_init(void)
671 {
672 u32 val;
673 void *dbi_base = (void *)PCIE_SNPS_DBI_BASE;
674 u64 apb_base = PCIE_SNPS_APB_BASE;
675 int i, retries = 0, phy_linkup;
676
677 #ifdef PCIE_ENABLE_SRNS_PLL_REFCLK
678 printep("RefClock in SRNS clock mode\n");
679 #else
680 printep("RefClock in common clock_mode\n");
681 #endif
682
683 /*
684 * ltssm_enable enhance mode and enable delaying the link training
685 * after Hot Reset
686 */
687 writel(0x120012, apb_base + 0x180);
688
689 /* Unmask pm_turnoff_int */
690 writel(0x04000000, apb_base + 0x18);
691
692 /* PortLorgic DBI_RO_WR_EN */
693 val = readl((dbi_base + 0x8bc));
694 val |= 0x1;
695 writel(val, dbi_base + 0x8bc);
696
697 reinit:
698 pcie_bar_init(dbi_base);
699 pcie_inbound_config();
700
701 /* Device PID, DID */
702 writel(0x1d87, dbi_base + 0x00);
703 writel(0x356a, dbi_base + 0x02);
704 /* Device Class: Processing accelerators */
705 writel(0x1200, dbi_base + 0x0a);
706
707 pcie_link_set_max_speed(dbi_base, PCI_EXP_LNKCTL2_TLS_8_0GT);
708
709 #ifdef CONFIG_ROCKCHIP_RK3588
710 pcie_link_set_lanes(dbi_base, 4);
711 #elif CONFIG_ROCKCHIP_RK3568
712 pcie_link_set_lanes(dbi_base, 2);
713 #endif
714
715 /* EP mode */
716 writel(0xf00000, apb_base);
717 udelay(100);
718
719 val = readl(apb_base + 0x10);
720 if (val & 0x4) {
721 printep("Link is reset, int status misc=%x\n", val);
722 retries++;
723 }
724
725 if (retries) /* Set app_dly2_done to enable app_ltssm_enable */
726 writel(0x80008, apb_base + 0x180);
727 else /* Enable LTSSM */
728 writel(0xc000c, apb_base);
729 printep("init PCIe fast Link up\n");
730 pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_LNKRDY);
731
732 /* Waiting for Link up */
733 phy_linkup = 0;
734 while (1) {
735 val = readl(apb_base + 0x300);
736 if (((val & 0x3ffff) & ((0x3 << 16))) == 0x30000)
737 break;
738
739 if (((val & 0x3ffff) & ((0x3 << 16))) == 0x10000)
740 phy_linkup = 1;
741
742 if (val == 0 && phy_linkup)
743 pcie_first_reset();
744
745 udelay(10);
746 }
747 printep("Link up %x\n", val);
748 mdelay(3);
749
750 /* Wait for link stable */
751 for (i = 0; i < 10000; i++) {
752 val = readl(apb_base + 0x10);
753 if (val & 0x4) {
754 writel(0x4, apb_base + 0x10);
755 printep("Link is reset, int status misc=%x\n", val);
756 if (retries < 3) {
757 retries++;
758 goto reinit;
759 } else {
760 break;
761 }
762 }
763
764 /* L2 */
765 val = readl(apb_base + 0x4);
766 if (val & 0x400) {
767 writel(0x4, apb_base + 0x10);
768 pcie_first_reset();
769 }
770 udelay(1);
771 }
772 printep("Done\n");
773 pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_LNKUP);
774 }
775
rockchip_pcie_ep_init(void)776 void rockchip_pcie_ep_init(void)
777 {
778 u32 val;
779
780 printf("\nRKEP: Init PCIe EP\n");
781 pcie_bar0_header_init();
782
783 #ifdef CONFIG_ROCKCHIP_RK3588
784 writel(0x1 << 23 | 0x1 << 21, PMU_PWR_GATE_SFTCON1);
785 udelay(10);
786 #endif
787
788 pcie_firewall_init();
789 /* Re-in pcie initial */
790 val = readl(PCIE_SNPS_APB_BASE + 0x300);
791 if (((val & 0x3ffff) & ((0x3 << 16))) == 0x30000) {
792 printf("RKEP: already link up\n");
793 pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_LNKUP);
794 return;
795 }
796
797 pcie_board_init();
798 /* CRU and PHY Init */
799 pcie_cru_init();
800
801 pcie_ep_init();
802 }
803