1 /* 2 * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #include <lib/utils_def.h> 12 #include <plat/arm/board/common/v2m_def.h> 13 #include <plat/arm/common/arm_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/common/common_def.h> 16 17 #include "../fvp_def.h" 18 19 #if TRUSTED_BOARD_BOOT 20 #include MBEDTLS_CONFIG_FILE 21 #endif 22 23 /* Required platform porting definitions */ 24 #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ 25 U(FVP_MAX_CPUS_PER_CLUSTER) * \ 26 U(FVP_MAX_PE_PER_CPU)) 27 28 #define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ 29 PLATFORM_CORE_COUNT + U(1)) 30 31 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 32 33 #if PSCI_OS_INIT_MODE 34 #define PLAT_MAX_CPU_SUSPEND_PWR_LVL ARM_PWR_LVL1 35 #endif 36 37 /* 38 * Other platform porting definitions are provided by included headers 39 */ 40 41 /* 42 * Required ARM standard platform porting definitions 43 */ 44 #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) 45 46 #define PLAT_ARM_TRUSTED_SRAM_SIZE (FVP_TRUSTED_SRAM_SIZE * UL(1024)) 47 48 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 49 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 50 51 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 52 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 53 54 #if ENABLE_RME 55 #define PLAT_ARM_RMM_BASE (RMM_BASE) 56 #define PLAT_ARM_RMM_SIZE (RMM_LIMIT - RMM_BASE) 57 58 #define PLAT_ARM_RMM_PAYLOAD_SIZE UL(0x600000) /* 2 * 3MB */ 59 60 /* Protected physical address size */ 61 #define PLAT_ARM_PPS (SZ_1T) 62 #endif /* ENABLE_RME */ 63 64 /* 65 * Max size of SPMC is 16MB for fvp. With SPMD enabled this value corresponds to 66 * max size of BL32 image. 67 */ 68 #if defined(SPD_spmd) 69 #define PLAT_ARM_SPMC_BASE PLAT_ARM_TRUSTED_DRAM_BASE 70 #define PLAT_ARM_SPMC_SIZE SZ_16M 71 72 #if BL2_ENABLE_SP_LOAD 73 #define PLAT_ARM_SP_MAX_SIZE (3 * SZ_1M) 74 #endif /* BL2_ENABLE_SP_LOAD */ 75 #endif 76 77 /* Virtual address used by dynamic mem_protect for chunk_base */ 78 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 79 80 /* No SCP in FVP */ 81 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 82 83 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) /* 36-bit range */ 84 #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) /* 30 GB */ 85 86 #define FVP_DRAM3_BASE ULL(0x8800000000) /* 40-bit range */ 87 #define FVP_DRAM3_SIZE ULL(0x7800000000) /* 480 GB */ 88 #define FVP_DRAM3_END (FVP_DRAM3_BASE + FVP_DRAM3_SIZE - 1U) 89 90 #define FVP_DRAM4_BASE ULL(0x88000000000) /* 44-bit range */ 91 #define FVP_DRAM4_SIZE ULL(0x78000000000) /* 7.5 TB */ 92 #define FVP_DRAM4_END (FVP_DRAM4_BASE + FVP_DRAM4_SIZE - 1U) 93 94 #define FVP_DRAM5_BASE ULL(0x880000000000) /* 48-bit range */ 95 #define FVP_DRAM5_SIZE ULL(0x780000000000) /* 120 TB */ 96 #define FVP_DRAM5_END (FVP_DRAM5_BASE + FVP_DRAM5_SIZE - 1U) 97 98 #define FVP_DRAM6_BASE ULL(0x8800000000000) /* 52-bit range */ 99 #define FVP_DRAM6_SIZE ULL(0x7800000000000) /* 1920 TB */ 100 #define FVP_DRAM6_END (FVP_DRAM6_BASE + FVP_DRAM6_SIZE - 1U) 101 102 /* 103 * On the FVP platform when using the EL3 SPMC implementation allocate the 104 * datastore for tracking shared memory descriptors in the TZC DRAM section 105 * to ensure sufficient storage can be allocated. 106 * Provide an implementation of the accessor method to allow the datastore 107 * details to be retrieved by the SPMC. 108 * The SPMC will take care of initializing the memory region. 109 */ 110 111 #define PLAT_SPMC_SHMEM_DATASTORE_SIZE 512 * 1024 112 113 /* Define memory configuration for device tree files. */ 114 #define PLAT_ARM_HW_CONFIG_SIZE U(0x4000) 115 116 #if SPMC_AT_EL3 117 118 /* 119 * Number of Secure Partitions supported. 120 * SPMC at EL3, uses this count to configure the maximum number of supported 121 * secure partitions. 122 */ 123 #define SECURE_PARTITION_COUNT 1 124 125 /* 126 * Number of Normal World Partitions supported. 127 * SPMC at EL3, uses this count to configure the maximum number of supported 128 * NWd partitions. 129 */ 130 #define NS_PARTITION_COUNT 1 131 132 /* 133 * Number of Logical Partitions supported. 134 * SPMC at EL3, uses this count to configure the maximum number of supported 135 * logical partitions. 136 */ 137 #define MAX_EL3_LP_DESCS_COUNT 1 138 139 #endif /* SPMC_AT_EL3 */ 140 141 /* 142 * Load address of BL33 for this platform port 143 */ 144 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) 145 146 #if TRANSFER_LIST 147 148 /* Define maximum size of sp manifest file. */ 149 #if defined(SPD_spmd) 150 #define PLAT_ARM_SPMC_SP_MANIFEST_SIZE SZ_4K 151 152 #if BL2_ENABLE_SP_LOAD 153 /* 154 * TODO: 155 * There is no standard tag_id defined for TB_FW_CONFIG in 156 * the xferlist. As a temporary measure, 157 * use the first value in the non-standard range as 158 * the tag_id for TB_FW_CONFIG in the xferlist. 159 */ 160 #define PLAT_ARM_TB_FW_CONFIG_TL_TAG 0x00fff000 161 #define PLAT_ARM_TB_FW_CONFIG_SIZE SZ_4K 162 163 #else /* !BL2_ENABLE_SP_LOAD */ 164 #define PLAT_ARM_TB_FW_CONFIG_SIZE UL(0x0) 165 #endif /* BL2_ENABLE_SP_LOAD */ 166 167 #else /* !SPD_spmd */ 168 169 #define PLAT_ARM_SPMC_SP_MANIFEST_SIZE UL(0x0) 170 #define PLAT_ARM_TB_FW_CONFIG_SIZE UL(0x0) 171 172 #endif /* SPD_spmd */ 173 174 /* 175 * PLAT_ARM_FW_HANDOFF_SIZE should be page-aligned to ensure proper xlat mapping. 176 * If it is not, generating the page table mapping for FW_HANDOFF will fail. 177 * Because PLAT_ARM_EVENT_LOG_MAX_SIZE is not guaranteed to be aligned, 178 * PLAT_ARM_FW_HANDOFF_SIZE must be explicitly aligned. 179 */ 180 #define PLAT_ARM_FW_HANDOFF_SIZE ((((PLAT_ARM_HW_CONFIG_SIZE + \ 181 PLAT_ARM_EVENT_LOG_MAX_SIZE + \ 182 PLAT_ARM_TB_FW_CONFIG_SIZE + \ 183 PLAT_ARM_SPMC_SP_MANIFEST_SIZE) + \ 184 PAGE_SIZE_MASK) >> \ 185 PAGE_SIZE_SHIFT) << PAGE_SIZE_SHIFT) 186 187 #define FW_NS_HANDOFF_BASE (PLAT_ARM_NS_IMAGE_BASE - PLAT_ARM_FW_HANDOFF_SIZE) 188 #define PLAT_ARM_EL3_FW_HANDOFF_BASE ARM_BL_RAM_BASE 189 #define PLAT_ARM_EL3_FW_HANDOFF_LIMIT PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE 190 191 #if RESET_TO_BL31 192 #define PLAT_ARM_TRANSFER_LIST_DTB_OFFSET FW_NS_HANDOFF_BASE + TRANSFER_LIST_DTB_OFFSET 193 #endif 194 195 #else 196 #define PLAT_ARM_FW_HANDOFF_SIZE U(0) 197 #endif 198 199 /* 200 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 201 * plat_arm_mmap array defined for each BL stage. 202 */ 203 #if defined(IMAGE_BL31) 204 # if SPM_MM 205 # define PLAT_ARM_MMAP_ENTRIES 10 206 # define MAX_XLAT_TABLES 9 207 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 208 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 12 209 # elif SPMC_AT_EL3 210 # define PLAT_ARM_MMAP_ENTRIES 13 211 # define MAX_XLAT_TABLES 11 212 # define PLAT_SP_IMAGE_MMAP_REGIONS 31 213 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 13 214 # else 215 # define PLAT_ARM_MMAP_ENTRIES 9 216 # if USE_DEBUGFS 217 # if ENABLE_RME 218 # define MAX_XLAT_TABLES 9 219 # else 220 # define MAX_XLAT_TABLES 8 221 # endif 222 # else 223 # if ENABLE_RME 224 # define MAX_XLAT_TABLES 8 225 # elif DRTM_SUPPORT 226 # define MAX_XLAT_TABLES 8 227 # else 228 # define MAX_XLAT_TABLES 7 229 # endif 230 # endif 231 # endif 232 #elif defined(IMAGE_BL32) 233 # if SPMC_AT_EL3 234 # define PLAT_ARM_MMAP_ENTRIES 270 235 # define MAX_XLAT_TABLES 10 236 # else 237 # define PLAT_ARM_MMAP_ENTRIES 9 238 # define MAX_XLAT_TABLES 6 239 # endif 240 #elif !USE_ROMLIB 241 # if defined(IMAGE_BL2) && (ENABLE_RME || SPMC_AT_EL3) 242 # define PLAT_ARM_MMAP_ENTRIES 12 243 # define MAX_XLAT_TABLES 6 244 # else 245 # define PLAT_ARM_MMAP_ENTRIES 12 246 # define MAX_XLAT_TABLES 5 247 # endif /* (IMAGE_BL2 && ENABLE_RME) */ 248 #else 249 # define PLAT_ARM_MMAP_ENTRIES 12 250 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 251 defined(IMAGE_BL2) && MEASURED_BOOT 252 # define MAX_XLAT_TABLES 7 253 # else 254 # define MAX_XLAT_TABLES 6 255 # endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && IMAGE_BL2 && MEASURED_BOOT */ 256 #endif 257 258 /* 259 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 260 * plus a little space for growth. 261 * In case of PSA Crypto API, few algorithms like ECDSA needs bigger BL1 RW 262 * area. 263 */ 264 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA || PSA_CRYPTO || \ 265 FVP_TRUSTED_SRAM_SIZE == 512 266 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xD000) 267 #else 268 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 269 #endif 270 271 /* 272 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 273 */ 274 275 #if USE_ROMLIB 276 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 277 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 278 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x5000) 279 #else 280 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 281 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 282 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) 283 #endif 284 285 /* 286 * Set the maximum size of BL2 to be close to half of the Trusted SRAM. 287 * Maximum size of BL2 increases as Trusted SRAM size increases. 288 */ 289 #if (defined(TF_MBEDTLS_KEY_ALG_ID) && \ 290 (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA)) || \ 291 (TRUSTED_BOARD_BOOT && COT_DESC_IN_DTB) 292 # define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ 293 (2 * PAGE_SIZE) - \ 294 FVP_BL2_ROMLIB_OPTIMIZATION) 295 #elif TRUSTED_BOARD_BOOT || MEASURED_BOOT 296 # define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ 297 (3 * PAGE_SIZE) - \ 298 FVP_BL2_ROMLIB_OPTIMIZATION) 299 #elif ARM_BL31_IN_DRAM 300 /* When ARM_BL31_IN_DRAM is set, BL2 can use almost all of Trusted SRAM. */ 301 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - FVP_BL2_ROMLIB_OPTIMIZATION) 302 #else 303 /** 304 * Default to just under half of SRAM to ensure there's enough room for really 305 * large BL31 build configurations when using the default SRAM size (256 Kb). 306 */ 307 #define PLAT_ARM_MAX_BL2_SIZE \ 308 (((PLAT_ARM_TRUSTED_SRAM_SIZE / 3) & ~PAGE_SIZE_MASK) - PAGE_SIZE - \ 309 FVP_BL2_ROMLIB_OPTIMIZATION) 310 #endif 311 312 #if RESET_TO_BL31 313 /* Size of Trusted SRAM - the first 4KB of shared memory - GPT L0 Tables */ 314 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 315 ARM_SHARED_RAM_SIZE - \ 316 ARM_L0_GPT_SIZE) 317 #else 318 /* 319 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 320 * calculated using the current BL31 PROGBITS debug size plus the sizes of 321 * BL2 and BL1-RW. 322 * Size of the BL31 PROGBITS increases as the SRAM size increases. 323 */ 324 #if TRANSFER_LIST 325 #define PLAT_ARM_MAX_BL31_SIZE \ 326 (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE - \ 327 PLAT_ARM_FW_HANDOFF_SIZE - ARM_L0_GPT_SIZE) 328 #else 329 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 330 ARM_SHARED_RAM_SIZE - \ 331 ARM_FW_CONFIGS_SIZE - ARM_L0_GPT_SIZE) 332 #endif /* TRANSFER_LIST */ 333 #endif /* RESET_TO_BL31 */ 334 335 #ifndef __aarch64__ 336 #if RESET_TO_SP_MIN 337 /* Size of Trusted SRAM - the first 4KB of shared memory */ 338 #define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 339 ARM_SHARED_RAM_SIZE) 340 #else 341 /* 342 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 343 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 344 * BL2 and BL1-RW 345 */ 346 #if TRANSFER_LIST 347 # define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 348 ARM_SHARED_RAM_SIZE - \ 349 PLAT_ARM_FW_HANDOFF_SIZE) 350 #else 351 # define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 352 ARM_SHARED_RAM_SIZE - \ 353 ARM_FW_CONFIGS_SIZE) 354 #endif /* TRANSFER_LIST */ 355 #endif /* RESET_TO_SP_MIN */ 356 #endif 357 358 /* 359 * Size of cacheable stacks 360 */ 361 #if defined(IMAGE_BL1) 362 # if CRYPTO_SUPPORT 363 # define PLATFORM_STACK_SIZE UL(0x1000) 364 # else 365 # define PLATFORM_STACK_SIZE UL(0x500) 366 # endif /* CRYPTO_SUPPORT */ 367 #elif defined(IMAGE_BL2) 368 # if CRYPTO_SUPPORT 369 # define PLATFORM_STACK_SIZE UL(0x1000) 370 # else 371 # define PLATFORM_STACK_SIZE UL(0x600) 372 # endif /* CRYPTO_SUPPORT */ 373 #elif defined(IMAGE_BL2U) 374 # define PLATFORM_STACK_SIZE UL(0x400) 375 #elif defined(IMAGE_BL31) 376 # if DRTM_SUPPORT 377 # define PLATFORM_STACK_SIZE UL(0x1000) 378 # else 379 # define PLATFORM_STACK_SIZE UL(0x800) 380 # endif /* DRTM_SUPPORT */ 381 #elif defined(IMAGE_BL32) 382 # if SPMC_AT_EL3 383 # define PLATFORM_STACK_SIZE UL(0x1000) 384 # else 385 # define PLATFORM_STACK_SIZE UL(0x440) 386 # endif /* SPMC_AT_EL3 */ 387 #elif defined(IMAGE_RMM) 388 # define PLATFORM_STACK_SIZE UL(0x440) 389 #endif 390 391 #define MAX_IO_DEVICES 4 392 #define MAX_IO_HANDLES 4 393 394 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 395 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 396 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 397 398 #if ARM_GPT_SUPPORT && IMAGE_BL1 399 /* 400 * Offset of the FIP in the GPT image. BL1 component uses this option 401 * as it does not load the partition table to get the FIP base 402 * address. At sector 34 by default (i.e. after reserved sectors 0-33) 403 * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 404 */ 405 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 406 #endif /* ARM_GPT_SUPPORT */ 407 408 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 409 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 410 411 /* 412 * PL011 related constants 413 */ 414 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 415 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 416 417 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 418 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 419 420 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 421 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 422 423 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 424 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 425 426 #define PLAT_ARM_TRP_UART_BASE V2M_IOFPGA_UART3_BASE 427 #define PLAT_ARM_TRP_UART_CLK_IN_HZ V2M_IOFPGA_UART3_CLK_IN_HZ 428 429 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 430 #define PLAT_ARM_SMMUV3_ROOT_REG_OFFSET UL(0x20000) 431 432 /* CCI related constants */ 433 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 434 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 435 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 436 437 /* CCI-500/CCI-550 on Base platform */ 438 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 439 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 440 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 441 442 /* CCN related constants. Only CCN 502 is currently supported */ 443 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 444 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 445 446 /* System timer related constants */ 447 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 448 449 /* Mailbox base address */ 450 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 451 452 /* PCIe memory region 1 (Base Platform RevC only) */ 453 #define PLAT_ARM_PCI_MEM_1_BASE (ULL(0x50000000)) 454 #define PLAT_ARM_PCI_MEM_1_SIZE (SZ_256M) /* 256MB */ 455 456 /* 457 * PCIe memory region 2 (Base Platform RevC only) 458 * The full size of the second PCI memory region is 256GB 459 * but for now we only allocate the L1 GPTs for the first 3GB. 460 */ 461 #define PLAT_ARM_PCI_MEM_2_BASE (ULL(0x4000000000)) 462 #define PLAT_ARM_PCI_MEM_2_SIZE (3 * SZ_1G) /* 3GB */ 463 464 /* TrustZone controller related constants 465 * 466 * Currently only filters 0 and 2 are connected on Base FVP. 467 * Filter 0 : CPU clusters (no access to DRAM by default) 468 * Filter 1 : not connected 469 * Filter 2 : LCDs (access to VRAM allowed by default) 470 * Filter 3 : not connected 471 * Programming unconnected filters will have no effect at the 472 * moment. These filter could, however, be connected in future. 473 * So care should be taken not to configure the unused filters. 474 * 475 * Allow only non-secure access to all DRAM to supported devices. 476 * Give access to the CPUs and Virtio. Some devices 477 * would normally use the default ID so allow that too. 478 */ 479 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 480 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 481 482 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 483 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 484 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 485 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 486 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 487 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 488 489 /* 490 * GIC related constants to cater for both GICv2 and GICv3 instances of an 491 * FVP. They could be overridden at runtime in case the FVP implements the 492 * legacy VE memory map. 493 */ 494 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 495 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 496 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 497 498 /* 499 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 500 * terminology. On a GICv2 system or mode, the lists will be merged and treated 501 * as Group 0 interrupts. 502 */ 503 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 504 ARM_G1S_IRQ_PROPS(grp), \ 505 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 506 GIC_INTR_CFG_LEVEL), \ 507 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 508 GIC_INTR_CFG_LEVEL) 509 510 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 511 512 #if SDEI_IN_FCONF 513 #define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT 514 #define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT 515 #else 516 #if PLATFORM_TEST_RAS_FFH || PLATFORM_TEST_FFH_LSP_RAS_SP 517 #define PLAT_ARM_PRIVATE_SDEI_EVENTS \ 518 ARM_SDEI_PRIVATE_EVENTS, \ 519 SDEI_EXPLICIT_EVENT(5000, SDEI_MAPF_NORMAL), \ 520 SDEI_EXPLICIT_EVENT(5001, SDEI_MAPF_NORMAL), \ 521 SDEI_EXPLICIT_EVENT(5002, SDEI_MAPF_NORMAL), \ 522 SDEI_EXPLICIT_EVENT(5003, SDEI_MAPF_CRITICAL), \ 523 SDEI_EXPLICIT_EVENT(5004, SDEI_MAPF_CRITICAL) 524 #else 525 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 526 #endif 527 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 528 #endif 529 530 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SPM_BUF_BASE + \ 531 PLAT_SPM_BUF_SIZE) 532 533 #define PLAT_SP_PRI 0x20 534 535 /* 536 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 537 */ 538 #ifdef __aarch64__ 539 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 540 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 541 #else 542 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 543 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 544 #endif 545 546 /* 547 * Maximum size of Event Log buffer used in Measured Boot Event Log driver 548 * TODO: calculate maximum EventLog size using the calculation: 549 * Maximum size of Event Log * Number of images 550 */ 551 #if (defined(SPD_spmd)) || (ENABLE_RME && (defined(SPD_tspd) || defined(SPD_opteed))) 552 /* 553 * Account for additional measurements of secure partitions and SPM. 554 * Also, account for OP-TEE running with maximum number of SPs. 555 */ 556 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x800) 557 #elif defined(IMAGE_BL1) && TRANSFER_LIST 558 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x200) 559 #else 560 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400) 561 #endif 562 563 /* 564 * Maximum size of Event Log buffer used for DRTM 565 */ 566 #define PLAT_DRTM_EVENT_LOG_MAX_SIZE UL(0x300) 567 568 /* 569 * Number of MMAP entries used by DRTM implementation 570 */ 571 #define PLAT_DRTM_MMAP_ENTRIES PLAT_ARM_MMAP_ENTRIES 572 573 #endif /* PLATFORM_DEF_H */ 574