1 /* 2 * Copyright 2020-2026 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef DDR_UTILS_H 8 #define DDR_UTILS_H 9 10 #include <stdbool.h> 11 #include <stdlib.h> 12 13 #include <lib/mmio.h> 14 15 #include <platform_def.h> 16 17 /* Possible errors */ 18 #define NO_ERR 0x00000000U 19 #define TIMEOUT_ERR 0x00000002U 20 #define TRAINING_FAILED 0x00000003U 21 #define BITFIELD_EXCEEDED 0x00000004U 22 #define DEASSERT_FAILED 0x00000005U 23 24 /* DDRC related */ 25 #define DDRC_BASE 0x403C0000U 26 #define OFFSET_DDRC_SWCTL 0x320U 27 #define OFFSET_DDRC_DFIMISC 0x1B0U 28 #define OFFSET_DDRC_DFISTAT 0x1BCU 29 #define OFFSET_DDRC_PWRCTL 0x30U 30 #define OFFSET_DDRC_SWSTAT 0x324U 31 #define OFFSET_DDRC_STAT 0x04U 32 #define OFFSET_DDRC_DFITMG0 0x190U 33 #define OFFSET_DDRC_DBG1 0x304U 34 35 #define OFFSET_DDRC_DRAMTMG2 0x108U 36 #define OFFSET_DDRC_INIT6 0xE8U 37 #define OFFSET_DDRC_INIT7 0xECU 38 #define OFFSET_DDRC_RANKCTL 0xF4U 39 #define OFFSET_DDRC_DFITMG1 0x194U 40 41 /* DDRC masks and values */ 42 #define MSTR_LPDDR4_VAL 0x20U 43 #define SWSTAT_SW_DONE 1U 44 #define SWSTAT_SW_NOT_DONE 0U 45 #define SWCTL_SWDONE_DONE 0x1U 46 #define SWCTL_SWDONE_ENABLE 0x0U 47 #define SWSTAT_SWDONE_ACK_MASK GENMASK_32(1U, 0U) 48 49 #define MSTR_DRAM_MASK GENMASK_32(5U, 0U) 50 #define MSTR_ACT_RANKS_MASK GENMASK_32(25U, 24U) 51 #define MSTR_DUAL_RANK_VAL 0x3000000U 52 #define MSTR_BURST_RDWR_POS 16 53 #define MSTR_BURST_RDWR_MASK 0xFU 54 #define DFITMG0_PHY_CLK_POS 15 55 #define DFITMG0_PHY_CLK_MASK 0x1U 56 #define DRAMTMG2_RD_WR_POS 8 57 #define DRAMTMG2_RD_WR_MASK GENMASK_32(4U, 0U) 58 #define DRAMTMG2_WR_RD_POS 0 59 #define DRAMTMG2_WR_RD_MASK GENMASK_32(4U, 0U) 60 #define INIT6_MR5_MASK 0xFFFFU 61 #define INIT7_MR6_MASK 0xFFFFU 62 #define DFITMG1_WRDATA_DELAY_POS 16 63 #define DFITMG1_WRDATA_DELAY_MASK GENMASK_32(4U, 0U) 64 #define RANKCTL_RD_GAP_POS 4 65 #define RANKCTL_RD_GAP_MASK GENMASK_32(3U, 0U) 66 #define RANKCTL_WR_GAP_POS 8 67 #define RANKCTL_WR_GAP_MASK GENMASK_32(3U, 0U) 68 69 #define DDR_SS_AXI_PARITY_ENABLE_MASK GENMASK_32(12U, 4U) 70 #define DDR_SS_AXI_PARITY_TYPE_MASK GENMASK_32(24U, 16U) 71 #define DDR_SS_DFI_1_ENABLED 0x1U 72 #define DBG1_DISABLE_DE_QUEUEING 0x0U 73 #define RFSHCTL3_DISABLE_AUTO_REFRESH 0x1U 74 #define ENABLE_AXI_PORT 0x000000001 75 76 #define PWRCTL_POWER_DOWN_ENABLE_MASK BIT_32(1) 77 #define PWRCTL_SELF_REFRESH_ENABLE_MASK BIT_32(0) 78 #define PWRCTL_EN_DFI_DRAM_CLOCK_DIS_MASK BIT_32(3) 79 #define DFIMISC_DFI_INIT_COMPLETE_EN_MASK BIT_32(0) 80 81 #define MASTER0_CAL_ACTIVE 0x1U 82 #define MASTER0_CAL_DONE 0x0U 83 #define DFIMISC_DFI_INIT_START_MASK BIT_32(5) 84 #define DFISTAT_DFI_INIT_DONE 0x1U 85 #define DFISTAT_DFI_INIT_INCOMPLETE 0x0U 86 #define PWRCTL_SELFREF_SW_MASK BIT_32(5) 87 #define STAT_OPERATING_MODE_MASK GENMASK_32(2U, 0U) 88 #define STAT_OPERATING_MODE_INIT 0x0U 89 #define RFSHCTL3_DIS_AUTO_REFRESH_MASK BIT_32(0) 90 #define TRAINING_OK_MSG 0x07U 91 #define TRAINING_FAILED_MSG 0xFFU 92 93 #define APBONLY_DCTWRITEPROT_ACK_EN 0U 94 #define APBONLY_DCTWRITEPROT_ACK_DIS 1U 95 96 #define ADJUST_DDRC_DISABLED 0x0U 97 98 /* uMCTL2 Multi-Port Registers */ 99 #define DDRC_UMCTL2_MP_BASE 0x403C03F8U 100 #define OFFSET_DDRC_PCTRL_0 0x98U 101 #define OFFSET_DDRC_PCTRL_1 0x148U 102 #define OFFSET_DDRC_PCTRL_2 0x1F8U 103 104 /* PHY related */ 105 #define DDR_PHYA_MASTER0_CALBUSY 0x4038165CU 106 #define DDR_PHYA_APBONLY_UCTSHADOWREGS 0x40380404U 107 #define UCT_WRITE_PROT_SHADOW_MASK 0x1U 108 #define DDR_PHYA_DCTWRITEPROT 0x4038040CU 109 #define DDR_PHYA_APBONLY_UCTWRITEONLYSHADOW 0x40380410U 110 #define OFFSET_DDRC_RFSHCTL3 0x60U 111 #define UCT_WRITE_PROT_SHADOW_ACK 0x0U 112 #define TXDQDLY_COARSE 6U 113 #define DDRPHY_PIPE_DFI_MISC 1U 114 #define ARDPTR_INITVAL_ADDR 0x40381494U 115 116 #define CDD_CHA_RR_1_0 0x403B004CU 117 #define CDD_CHA_RR_0_1 0x403B004DU 118 #define CDD_CHA_RW_1_1 0x403B0050U 119 #define CDD_CHA_RW_1_0 0x403B0051U 120 #define CDD_CHA_RW_0_1 0x403B0054U 121 #define CDD_CHA_RW_0_0 0x403B0055U 122 #define CDD_CHA_WR_1_1 0x403B0058U 123 #define CDD_CHA_WR_1_0 0x403B0059U 124 #define CDD_CHA_WR_0_1 0x403B005CU 125 #define CDD_CHA_WR_0_0 0x403B005DU 126 #define CDD_CHA_WW_1_0 0x403B0060U 127 #define CDD_CHA_WW_0_1 0x403B0061U 128 129 #define CDD_CHB_RR_1_0 0x403B00B1U 130 #define CDD_CHB_RR_0_1 0x403B00B4U 131 #define CDD_CHB_RW_1_1 0x403B00B5U 132 #define CDD_CHB_RW_1_0 0x403B00B8U 133 #define CDD_CHB_RW_0_1 0x403B00B9U 134 #define CDD_CHB_RW_0_0 0x403B00BCU 135 #define CDD_CHB_WR_1_1 0x403B00BDU 136 #define CDD_CHB_WR_1_0 0x403B00C0U 137 #define CDD_CHB_WR_0_1 0x403B00C1U 138 #define CDD_CHB_WR_0_0 0x403B00C4U 139 #define CDD_CHB_WW_1_0 0x403B00C5U 140 #define CDD_CHB_WW_0_1 0x403B00C8U 141 142 #define CDD_CHA_RR_1_0_DDR3 0x403B0059U 143 #define CDD_CHA_RR_0_1_DDR3 0x403B0060U 144 #define CDD_CHA_RW_1_1_DDR3 0x403B008DU 145 #define CDD_CHA_RW_1_0_DDR3 0x403B0090U 146 #define CDD_CHA_RW_0_1_DDR3 0x403B0095U 147 #define CDD_CHA_RW_0_0_DDR3 0x403B0098U 148 #define CDD_CHA_WR_1_1_DDR3 0x403B00ADU 149 #define CDD_CHA_WR_1_0_DDR3 0x403B00B0U 150 #define CDD_CHA_WR_0_1_DDR3 0x403B00B5U 151 #define CDD_CHA_WR_0_0_DDR3 0x403B00B8U 152 #define CDD_CHA_WW_1_0_DDR3 0x403B0071U 153 #define CDD_CHA_WW_0_1_DDR3 0x403B0078U 154 155 #define DBYTE0_TXDQSDLYTG0_U0 0x40394B4CU 156 #define DBYTE0_TXDQSDLYTG0_U1 0x40394B50U 157 #define DBYTE1_TXDQSDLYTG0_U0 0x40396B4CU 158 #define DBYTE1_TXDQSDLYTG0_U1 0x40396B50U 159 #define DBYTE2_TXDQSDLYTG0_U0 0x40398B4CU 160 #define DBYTE2_TXDQSDLYTG0_U1 0x40398B50U 161 #define DBYTE3_TXDQSDLYTG0_U0 0x4039AB4CU 162 #define DBYTE3_TXDQSDLYTG0_U1 0x4039AB50U 163 164 #define DBYTE0_TXDQSDLYTG1_U0 0x40394B6CU 165 #define DBYTE0_TXDQSDLYTG1_U1 0x40394B70U 166 #define DBYTE1_TXDQSDLYTG1_U0 0x40396B6CU 167 #define DBYTE1_TXDQSDLYTG1_U1 0x40396B70U 168 #define DBYTE2_TXDQSDLYTG1_U0 0x40398B6CU 169 #define DBYTE2_TXDQSDLYTG1_U1 0x40398B70U 170 #define DBYTE3_TXDQSDLYTG1_U0 0x4039AB6CU 171 #define DBYTE3_TXDQSDLYTG1_U1 0x4039AB70U 172 173 #define VREF_CA_A0 0x403B0095U 174 #define VREF_CA_A1 0x403B0098U 175 #define VREF_CA_B0 0x403B00FCU 176 #define VREF_CA_B1 0x403B00FDU 177 178 #define VREF_DQ_A0 0x403B0099U 179 #define VREF_DQ_A1 0x403B009CU 180 #define VREF_DQ_B0 0x403B0100U 181 #define VREF_DQ_B1 0x403B0101U 182 183 #define ADJUST_DDRC_MASK BIT_32(2) 184 #define SELFREF_TYPE_MASK GENMASK_32(5U, 4U) 185 186 /* DDR Subsystem */ 187 #define DDR_SS_REG 0x403D0000U 188 189 /* Default timeout for DDR PHY operations */ 190 #define DEFAULT_TIMEOUT_US 1000000U 191 192 /* Start addresses of IMEM and DMEM memory areas */ 193 #define IMEM_START_ADDR 0x403A0000U 194 #define DMEM_START_ADDR 0x403B0000U 195 196 #define OFFSET_DFIPHYMSTR 0x1C4U 197 #define DFIPHYMSTR_ENABLE 0x1U 198 #define DFIPHYMSTR_DISABLED 0x0U 199 #define SELFREF_TYPE_POS 4 200 #define PHY_MASTER_REQUEST 0x1U 201 202 struct cdd_type { 203 uint8_t rr; 204 uint8_t rw; 205 uint8_t wr; 206 uint8_t ww; 207 }; 208 209 struct space_timing_params { 210 struct cdd_type cdd; 211 uint8_t vref_ca; 212 uint8_t vref_dq; 213 uint16_t tphy_wrdata_delay; 214 }; 215 216 /* 217 * Post PHY train setup - complementary settings 218 * that needs to be performed after running the firmware. 219 * @param options - various flags controlling post training actions 220 */ 221 uint32_t post_train_setup(uint8_t options); 222 223 /* Wait until firmware finishes execution and return training result */ 224 uint32_t wait_firmware_execution(void); 225 226 /* Set default AXI parity. */ 227 uint32_t set_axi_parity(void); 228 229 /* Modify bitfield value with delta, given bitfield position and mask */ 230 bool update_bf(uint32_t *v, uint8_t pos, uint32_t mask, int32_t delta); 231 232 /* Read Critical Delay Differences from message block and store max values */ 233 void read_cdds(void); 234 235 /* Read trained VrefCA from message block and store average value */ 236 void read_vref_ca(void); 237 238 /* Read trained VrefDQ from message block and store average value */ 239 void read_vref_dq(void); 240 241 /* Calculate DFITMG1.dfi_t_wrdata_delay */ 242 void compute_tphy_wrdata_delay(void); 243 244 #endif /* DDR_UTILS_H */ 245