1 /* 2 * Copyright 2020-2026 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef DDR_UTILS_H 8 #define DDR_UTILS_H 9 10 #include <stdbool.h> 11 #include <stdlib.h> 12 13 #include <lib/mmio.h> 14 15 #include <platform_def.h> 16 17 /* Possible errors */ 18 #define NO_ERR 0x00000000U 19 #define TIMEOUT_ERR 0x00000002U 20 #define TRAINING_FAILED 0x00000003U 21 #define BITFIELD_EXCEEDED 0x00000004U 22 #define DEASSERT_FAILED 0x00000005U 23 #define MAPPING_FAILED 0x00000006U 24 25 /* DDRC related */ 26 #define DDRC_BASE 0x403C0000U 27 #define OFFSET_DDRC_SWCTL 0x320U 28 #define OFFSET_DDRC_DFIMISC 0x1B0U 29 #define OFFSET_DDRC_DFISTAT 0x1BCU 30 #define OFFSET_DDRC_PWRCTL 0x30U 31 #define OFFSET_DDRC_SWSTAT 0x324U 32 #define OFFSET_DDRC_STAT 0x04U 33 #define OFFSET_DDRC_DFITMG0 0x190U 34 #define OFFSET_DDRC_DBG1 0x304U 35 36 #define OFFSET_DDRC_DRAMTMG2 0x108U 37 #define OFFSET_DDRC_INIT6 0xE8U 38 #define OFFSET_DDRC_INIT7 0xECU 39 #define OFFSET_DDRC_RANKCTL 0xF4U 40 #define OFFSET_DDRC_DFITMG1 0x194U 41 42 /* DDRC masks and values */ 43 #define MSTR_LPDDR4_VAL 0x20U 44 #define SWSTAT_SW_DONE 1U 45 #define SWSTAT_SW_NOT_DONE 0U 46 #define SWCTL_SWDONE_DONE 0x1U 47 #define SWCTL_SWDONE_ENABLE 0x0U 48 #define SWSTAT_SWDONE_ACK_MASK GENMASK_32(1U, 0U) 49 50 #define MSTR_DRAM_MASK GENMASK_32(5U, 0U) 51 #define MSTR_ACT_RANKS_MASK GENMASK_32(25U, 24U) 52 #define MSTR_DUAL_RANK_VAL 0x3000000U 53 #define MSTR_BURST_RDWR_POS 16 54 #define MSTR_BURST_RDWR_MASK 0xFU 55 #define DFITMG0_PHY_CLK_POS 15 56 #define DFITMG0_PHY_CLK_MASK 0x1U 57 #define DRAMTMG2_RD_WR_POS 8 58 #define DRAMTMG2_RD_WR_MASK GENMASK_32(4U, 0U) 59 #define DRAMTMG2_WR_RD_POS 0 60 #define DRAMTMG2_WR_RD_MASK GENMASK_32(4U, 0U) 61 #define INIT6_MR5_MASK 0xFFFFU 62 #define INIT7_MR6_MASK 0xFFFFU 63 #define DFITMG1_WRDATA_DELAY_POS 16 64 #define DFITMG1_WRDATA_DELAY_MASK GENMASK_32(4U, 0U) 65 #define RANKCTL_RD_GAP_POS 4 66 #define RANKCTL_RD_GAP_MASK GENMASK_32(3U, 0U) 67 #define RANKCTL_WR_GAP_POS 8 68 #define RANKCTL_WR_GAP_MASK GENMASK_32(3U, 0U) 69 70 #define DDR_SS_AXI_PARITY_ENABLE_MASK GENMASK_32(12U, 4U) 71 #define DDR_SS_AXI_PARITY_TYPE_MASK GENMASK_32(24U, 16U) 72 #define DDR_SS_DFI_1_ENABLED 0x1U 73 #define DBG1_DISABLE_DE_QUEUEING 0x0U 74 #define RFSHCTL3_DISABLE_AUTO_REFRESH 0x1U 75 #define ENABLE_AXI_PORT 0x000000001 76 77 #define PWRCTL_POWER_DOWN_ENABLE_MASK BIT_32(1) 78 #define PWRCTL_SELF_REFRESH_ENABLE_MASK BIT_32(0) 79 #define PWRCTL_EN_DFI_DRAM_CLOCK_DIS_MASK BIT_32(3) 80 #define DFIMISC_DFI_INIT_COMPLETE_EN_MASK BIT_32(0) 81 82 #define MASTER0_CAL_ACTIVE 0x1U 83 #define MASTER0_CAL_DONE 0x0U 84 #define DFIMISC_DFI_INIT_START_MASK BIT_32(5) 85 #define DFISTAT_DFI_INIT_DONE 0x1U 86 #define DFISTAT_DFI_INIT_INCOMPLETE 0x0U 87 #define PWRCTL_SELFREF_SW_MASK BIT_32(5) 88 #define STAT_OPERATING_MODE_MASK GENMASK_32(2U, 0U) 89 #define STAT_OPERATING_MODE_INIT 0x0U 90 #define RFSHCTL3_DIS_AUTO_REFRESH_MASK BIT_32(0) 91 #define TRAINING_OK_MSG 0x07U 92 #define TRAINING_FAILED_MSG 0xFFU 93 94 #define APBONLY_DCTWRITEPROT_ACK_EN 0U 95 #define APBONLY_DCTWRITEPROT_ACK_DIS 1U 96 97 #define ADJUST_DDRC_DISABLED 0x0U 98 99 /* uMCTL2 Multi-Port Registers */ 100 #define DDRC_UMCTL2_MP_BASE 0x403C03F8U 101 #define OFFSET_DDRC_PCTRL_0 0x98U 102 #define OFFSET_DDRC_PCTRL_1 0x148U 103 #define OFFSET_DDRC_PCTRL_2 0x1F8U 104 105 /* PHY related */ 106 #define DDR_PHYA_MASTER0_CALBUSY 0x4038165CU 107 #define DDR_PHYA_APBONLY_UCTSHADOWREGS 0x40380404U 108 #define UCT_WRITE_PROT_SHADOW_MASK 0x1U 109 #define DDR_PHYA_DCTWRITEPROT 0x4038040CU 110 #define DDR_PHYA_APBONLY_UCTWRITEONLYSHADOW 0x40380410U 111 #define OFFSET_DDRC_RFSHCTL3 0x60U 112 #define UCT_WRITE_PROT_SHADOW_ACK 0x0U 113 #define TXDQDLY_COARSE 6U 114 #define DDRPHY_PIPE_DFI_MISC 1U 115 #define ARDPTR_INITVAL_ADDR 0x40381494U 116 117 #define CDD_CHA_RR_1_0 0x403B004CU 118 #define CDD_CHA_RR_0_1 0x403B004DU 119 #define CDD_CHA_RW_1_1 0x403B0050U 120 #define CDD_CHA_RW_1_0 0x403B0051U 121 #define CDD_CHA_RW_0_1 0x403B0054U 122 #define CDD_CHA_RW_0_0 0x403B0055U 123 #define CDD_CHA_WR_1_1 0x403B0058U 124 #define CDD_CHA_WR_1_0 0x403B0059U 125 #define CDD_CHA_WR_0_1 0x403B005CU 126 #define CDD_CHA_WR_0_0 0x403B005DU 127 #define CDD_CHA_WW_1_0 0x403B0060U 128 #define CDD_CHA_WW_0_1 0x403B0061U 129 130 #define CDD_CHB_RR_1_0 0x403B00B1U 131 #define CDD_CHB_RR_0_1 0x403B00B4U 132 #define CDD_CHB_RW_1_1 0x403B00B5U 133 #define CDD_CHB_RW_1_0 0x403B00B8U 134 #define CDD_CHB_RW_0_1 0x403B00B9U 135 #define CDD_CHB_RW_0_0 0x403B00BCU 136 #define CDD_CHB_WR_1_1 0x403B00BDU 137 #define CDD_CHB_WR_1_0 0x403B00C0U 138 #define CDD_CHB_WR_0_1 0x403B00C1U 139 #define CDD_CHB_WR_0_0 0x403B00C4U 140 #define CDD_CHB_WW_1_0 0x403B00C5U 141 #define CDD_CHB_WW_0_1 0x403B00C8U 142 143 #define CDD_CHA_RR_1_0_DDR3 0x403B0059U 144 #define CDD_CHA_RR_0_1_DDR3 0x403B0060U 145 #define CDD_CHA_RW_1_1_DDR3 0x403B008DU 146 #define CDD_CHA_RW_1_0_DDR3 0x403B0090U 147 #define CDD_CHA_RW_0_1_DDR3 0x403B0095U 148 #define CDD_CHA_RW_0_0_DDR3 0x403B0098U 149 #define CDD_CHA_WR_1_1_DDR3 0x403B00ADU 150 #define CDD_CHA_WR_1_0_DDR3 0x403B00B0U 151 #define CDD_CHA_WR_0_1_DDR3 0x403B00B5U 152 #define CDD_CHA_WR_0_0_DDR3 0x403B00B8U 153 #define CDD_CHA_WW_1_0_DDR3 0x403B0071U 154 #define CDD_CHA_WW_0_1_DDR3 0x403B0078U 155 156 #define DBYTE0_TXDQSDLYTG0_U0 0x40394B4CU 157 #define DBYTE0_TXDQSDLYTG0_U1 0x40394B50U 158 #define DBYTE1_TXDQSDLYTG0_U0 0x40396B4CU 159 #define DBYTE1_TXDQSDLYTG0_U1 0x40396B50U 160 #define DBYTE2_TXDQSDLYTG0_U0 0x40398B4CU 161 #define DBYTE2_TXDQSDLYTG0_U1 0x40398B50U 162 #define DBYTE3_TXDQSDLYTG0_U0 0x4039AB4CU 163 #define DBYTE3_TXDQSDLYTG0_U1 0x4039AB50U 164 165 #define DBYTE0_TXDQSDLYTG1_U0 0x40394B6CU 166 #define DBYTE0_TXDQSDLYTG1_U1 0x40394B70U 167 #define DBYTE1_TXDQSDLYTG1_U0 0x40396B6CU 168 #define DBYTE1_TXDQSDLYTG1_U1 0x40396B70U 169 #define DBYTE2_TXDQSDLYTG1_U0 0x40398B6CU 170 #define DBYTE2_TXDQSDLYTG1_U1 0x40398B70U 171 #define DBYTE3_TXDQSDLYTG1_U0 0x4039AB6CU 172 #define DBYTE3_TXDQSDLYTG1_U1 0x4039AB70U 173 174 #define VREF_CA_A0 0x403B0095U 175 #define VREF_CA_A1 0x403B0098U 176 #define VREF_CA_B0 0x403B00FCU 177 #define VREF_CA_B1 0x403B00FDU 178 179 #define VREF_DQ_A0 0x403B0099U 180 #define VREF_DQ_A1 0x403B009CU 181 #define VREF_DQ_B0 0x403B0100U 182 #define VREF_DQ_B1 0x403B0101U 183 184 #define ADJUST_DDRC_MASK BIT_32(2) 185 #define SELFREF_TYPE_MASK GENMASK_32(5U, 4U) 186 187 /* DDR Subsystem */ 188 #define DDR_SS_REG 0x403D0000U 189 190 /* Default timeout for DDR PHY operations */ 191 #define DEFAULT_TIMEOUT_US 1000000U 192 193 /* Start addresses of IMEM and DMEM memory areas */ 194 #define IMEM_START_ADDR 0x403A0000U 195 #define DMEM_START_ADDR 0x403B0000U 196 197 #define OFFSET_DFIPHYMSTR 0x1C4U 198 #define DFIPHYMSTR_ENABLE 0x1U 199 #define DFIPHYMSTR_DISABLED 0x0U 200 #define SELFREF_TYPE_POS 4 201 #define PHY_MASTER_REQUEST 0x1U 202 203 struct cdd_type { 204 uint8_t rr; 205 uint8_t rw; 206 uint8_t wr; 207 uint8_t ww; 208 }; 209 210 struct space_timing_params { 211 struct cdd_type cdd; 212 uint8_t vref_ca; 213 uint8_t vref_dq; 214 uint16_t tphy_wrdata_delay; 215 }; 216 217 /* 218 * Post PHY train setup - complementary settings 219 * that needs to be performed after running the firmware. 220 * @param options - various flags controlling post training actions 221 */ 222 uint32_t post_train_setup(uint8_t options); 223 224 /* Wait until firmware finishes execution and return training result */ 225 uint32_t wait_firmware_execution(void); 226 227 /* Set default AXI parity. */ 228 uint32_t set_axi_parity(void); 229 230 /* Modify bitfield value with delta, given bitfield position and mask */ 231 bool update_bf(uint32_t *v, uint8_t pos, uint32_t mask, int32_t delta); 232 233 /* Read Critical Delay Differences from message block and store max values */ 234 void read_cdds(void); 235 236 /* Read trained VrefCA from message block and store average value */ 237 void read_vref_ca(void); 238 239 /* Read trained VrefDQ from message block and store average value */ 240 void read_vref_dq(void); 241 242 /* Calculate DFITMG1.dfi_t_wrdata_delay */ 243 void compute_tphy_wrdata_delay(void); 244 245 #endif /* DDR_UTILS_H */ 246