1 /* 2 * Copyright 2018-2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef PLAT_PSCI_H 9 #define PLAT_PSCI_H 10 11 /* core abort current op */ 12 #define CORE_ABORT_OP 0x1 13 14 /* psci power levels - these are actually affinity levels 15 * in the psci_power_state_t array 16 */ 17 #define PLAT_CORE_LVL PSCI_CPU_PWR_LVL 18 #define PLAT_CLSTR_LVL U(1) 19 #define PLAT_SYS_LVL U(2) 20 #define PLAT_MAX_LVL PLAT_SYS_LVL 21 22 /* core state */ 23 /* OFF states 0x0 - 0xF */ 24 #define CORE_IN_RESET 0x0 25 #define CORE_DISABLED 0x1 26 #define CORE_OFF 0x2 27 #define CORE_STANDBY 0x3 28 #define CORE_PWR_DOWN 0x4 29 #define CORE_WFE 0x6 30 #define CORE_WFI 0x7 31 #define CORE_LAST 0x8 32 #define CORE_OFF_PENDING 0x9 33 #define CORE_WORKING_INIT 0xA 34 #define SYS_OFF_PENDING 0xB 35 #define SYS_OFF 0xC 36 37 /* ON states 0x10 - 0x1F */ 38 #define CORE_PENDING 0x10 39 #define CORE_RELEASED 0x11 40 #define CORE_WAKEUP 0x12 41 /* highest off state */ 42 #define CORE_OFF_MAX 0xF 43 /* lowest on state */ 44 #define CORE_ON_MIN CORE_PENDING 45 46 #define DAIF_SET_MASK 0x3C0 47 #define SCTLR_I_C_M_MASK 0x00001005 48 #define SCTLR_C_MASK 0x00000004 49 #define SCTLR_I_MASK 0x00001000 50 #define CPUACTLR_L1PCTL_MASK 0x0000E000 51 #define DCSR_RCPM2_BASE 0x20170000 52 #define CPUECTLR_SMPEN_MASK 0x40 53 #define CPUECTLR_SMPEN_EN 0x40 54 #define CPUECTLR_RET_MASK 0x7 55 #define CPUECTLR_RET_SET 0x2 56 #define CPUECTLR_TIMER_MASK 0x7 57 #define CPUECTLR_TIMER_8TICKS 0x2 58 #define CPUECTLR_TIMER_2TICKS 0x1 59 #define SCR_IRQ_MASK 0x2 60 #define SCR_FIQ_MASK 0x4 61 62 /* pwr mgmt features supported in the soc-specific code: 63 * value == 0x0, the soc code does not support this feature 64 * value != 0x0, the soc code supports this feature 65 */ 66 #ifndef SOC_CORE_RELEASE 67 #define SOC_CORE_RELEASE 0x1 68 #endif 69 70 #ifndef SOC_CORE_RESTART 71 #define SOC_CORE_RESTART 0x1 72 #endif 73 74 #ifndef SOC_CORE_OFF 75 #define SOC_CORE_OFF 0x1 76 #endif 77 78 #ifndef SOC_CORE_STANDBY 79 #define SOC_CORE_STANDBY 0x1 80 #endif 81 82 #ifndef SOC_CORE_PWR_DWN 83 #define SOC_CORE_PWR_DWN 0x1 84 #endif 85 86 #ifndef SOC_CLUSTER_STANDBY 87 #define SOC_CLUSTER_STANDBY 0x1 88 #endif 89 90 #ifndef SOC_CLUSTER_PWR_DWN 91 #define SOC_CLUSTER_PWR_DWN 0x1 92 #endif 93 94 #ifndef SOC_SYSTEM_STANDBY 95 #define SOC_SYSTEM_STANDBY 0x1 96 #endif 97 98 #ifndef SOC_SYSTEM_PWR_DWN 99 #define SOC_SYSTEM_PWR_DWN 0x1 100 #endif 101 102 #ifndef SOC_SYSTEM_OFF 103 #define SOC_SYSTEM_OFF 0x1 104 #endif 105 106 #ifndef SOC_SYSTEM_RESET 107 #define SOC_SYSTEM_RESET 0x1 108 #endif 109 110 #ifndef SOC_SYSTEM_RESET2 111 #define SOC_SYSTEM_RESET2 0x1 112 #endif 113 114 #ifndef __ASSEMBLER__ 115 116 void __dead2 _psci_system_reset(void); 117 void __dead2 _psci_system_off(void); 118 int _psci_cpu_on(u_register_t core_mask); 119 void _psci_cpu_prep_off(u_register_t core_mask); 120 void __dead2 _psci_cpu_off_wfi(u_register_t core_mask, 121 u_register_t wakeup_address); 122 void __dead2 _psci_cpu_pwrdn_wfi(u_register_t core_mask, 123 u_register_t wakeup_address); 124 void __dead2 _psci_sys_pwrdn_wfi(u_register_t core_mask, 125 u_register_t wakeup_address); 126 void _psci_wakeup(u_register_t core_mask); 127 void _psci_core_entr_stdby(u_register_t core_mask); 128 void _psci_core_prep_stdby(u_register_t core_mask); 129 void _psci_core_exit_stdby(u_register_t core_mask); 130 void _psci_core_prep_pwrdn(u_register_t core_mask); 131 void _psci_core_exit_pwrdn(u_register_t core_mask); 132 void _psci_clstr_prep_stdby(u_register_t core_mask); 133 void _psci_clstr_exit_stdby(u_register_t core_mask); 134 void _psci_clstr_prep_pwrdn(u_register_t core_mask); 135 void _psci_clstr_exit_pwrdn(u_register_t core_mask); 136 void _psci_sys_prep_stdby(u_register_t core_mask); 137 void _psci_sys_exit_stdby(u_register_t core_mask); 138 void _psci_sys_prep_pwrdn(u_register_t core_mask); 139 void _psci_sys_exit_pwrdn(u_register_t core_mask); 140 141 #endif 142 143 #endif /* __PLAT_PSCI_H__ */ 144