1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7 #ifndef _ASM_ARCH_CRU_RK3588_H 8 #define _ASM_ARCH_CRU_RK3588_H 9 10 #define MHz 1000000 11 #define KHz 1000 12 #define OSC_HZ (24 * MHz) 13 14 #define CPU_PVTPLL_HZ (1008 * MHz) 15 #define LPLL_HZ (816 * MHz) 16 #define GPLL_HZ (1188 * MHz) 17 #define CPLL_HZ (1500 * MHz) 18 #define NPLL_HZ (850 * MHz) 19 #define PPLL_HZ (1100 * MHz) 20 21 /* RK3588 pll id */ 22 enum rk3588_pll_id { 23 B0PLL, 24 B1PLL, 25 LPLL, 26 CPLL, 27 GPLL, 28 NPLL, 29 V0PLL, 30 AUPLL, 31 PPLL, 32 PLL_COUNT, 33 }; 34 35 struct rk3588_clk_info { 36 unsigned long id; 37 char *name; 38 bool is_cru; 39 }; 40 41 struct rk3588_clk_priv { 42 struct rk3588_cru *cru; 43 struct rk3588_grf *grf; 44 ulong ppll_hz; 45 ulong gpll_hz; 46 ulong cpll_hz; 47 ulong npll_hz; 48 ulong v0pll_hz; 49 ulong spll_hz; 50 ulong aupll_hz; 51 ulong armclk_hz; 52 ulong armclk_enter_hz; 53 ulong armclk_init_hz; 54 bool sync_kernel; 55 bool set_armclk_rate; 56 }; 57 58 struct rk3588_pll { 59 unsigned int con0; 60 unsigned int con1; 61 unsigned int con2; 62 unsigned int con3; 63 unsigned int con4; 64 unsigned int reserved0[3]; 65 }; 66 67 struct rk3588_cru { 68 struct rk3588_pll pll[18]; 69 unsigned int reserved0[16];/* Address Offset: 0x0240 */ 70 unsigned int mode_con00;/* Address Offset: 0x0280 */ 71 unsigned int reserved1[31];/* Address Offset: 0x0284 */ 72 unsigned int clksel_con[178]; /* Address Offset: 0x0300 */ 73 unsigned int reserved2[142];/* Address Offset: 0x05c8 */ 74 unsigned int clkgate_con[78];/* Address Offset: 0x0800 */ 75 unsigned int reserved3[50];/* Address Offset: 0x0938 */ 76 unsigned int softrst_con[78];/* Address Offset: 0x0400 */ 77 unsigned int reserved4[50];/* Address Offset: 0x0b38 */ 78 unsigned int glb_cnt_th;/* Address Offset: 0x0c00 */ 79 unsigned int glb_rst_st;/* Address Offset: 0x0c04 */ 80 unsigned int glb_srst_fst;/* Address Offset: 0x0c08 */ 81 unsigned int glb_srsr_snd; /* Address Offset: 0x0c0c */ 82 unsigned int glb_rst_con;/* Address Offset: 0x0c10 */ 83 unsigned int reserved5[4];/* Address Offset: 0x0c14 */ 84 unsigned int sdio_con[2];/* Address Offset: 0x0c24 */ 85 unsigned int reserved7;/* Address Offset: 0x0c2c */ 86 unsigned int sdmmc_con[2];/* Address Offset: 0x0c30 */ 87 unsigned int reserved8[48562];/* Address Offset: 0x0c38 */ 88 unsigned int pmuclksel_con[21]; /* Address Offset: 0x0100 */ 89 unsigned int reserved9[299];/* Address Offset: 0x0c38 */ 90 unsigned int pmuclkgate_con[9]; /* Address Offset: 0x0100 */ 91 }; 92 93 check_member(rk3588_cru, mode_con00, 0x280); 94 check_member(rk3588_cru, pmuclksel_con[1], 0x30304); 95 96 struct pll_rate_table { 97 unsigned long rate; 98 unsigned int m; 99 unsigned int p; 100 unsigned int s; 101 unsigned int k; 102 }; 103 104 #define RK3588_PLL_CON(x) ((x) * 0x4) 105 #define RK3588_MODE_CON 0x280 106 107 #define RK3588_PHP_CRU_BASE 0x8000 108 #define RK3588_PMU_CRU_BASE 0x30000 109 #define RK3588_BIGCORE0_CRU_BASE 0x50000 110 #define RK3588_BIGCORE1_CRU_BASE 0x52000 111 #define RK3588_DSU_CRU_BASE 0x58000 112 113 #define RK3588_PLL_CON(x) ((x) * 0x4) 114 #define RK3588_MODE_CON0 0x280 115 #define RK3588_CLKSEL_CON(x) ((x) * 0x4 + 0x300) 116 #define RK3588_CLKGATE_CON(x) ((x) * 0x4 + 0x800) 117 #define RK3588_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) 118 #define RK3588_GLB_CNT_TH 0xc00 119 #define RK3588_GLB_SRST_FST 0xc08 120 #define RK3588_GLB_SRST_SND 0xc0c 121 #define RK3588_GLB_RST_CON 0xc10 122 #define RK3588_GLB_RST_ST 0xc04 123 #define RK3588_SDIO_CON0 0xC24 124 #define RK3588_SDIO_CON1 0xC28 125 #define RK3588_SDMMC_CON0 0xC30 126 #define RK3588_SDMMC_CON1 0xC34 127 128 #define RK3588_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0x800) 129 #define RK3588_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0xa00) 130 131 #define RK3588_PMU_PLL_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE) 132 #define RK3588_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x300) 133 #define RK3588_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x800) 134 #define RK3588_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0xa00) 135 136 #define RK3588_B0_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE) 137 #define RK3588_B0_PLL_MODE_CON (RK3588_BIGCORE0_CRU_BASE + 0x280) 138 #define RK3588_BIGCORE0_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x300) 139 #define RK3588_BIGCORE0_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x800) 140 #define RK3588_BIGCORE0_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0xa00) 141 #define RK3588_B1_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE) 142 #define RK3588_B1_PLL_MODE_CON (RK3588_BIGCORE1_CRU_BASE + 0x280) 143 #define RK3588_BIGCORE1_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x300) 144 #define RK3588_BIGCORE1_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x800) 145 #define RK3588_BIGCORE1_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0xa00) 146 #define RK3588_LPLL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE) 147 #define RK3588_LPLL_MODE_CON (RK3588_DSU_CRU_BASE + 0x280) 148 #define RK3588_DSU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x300) 149 #define RK3588_DSU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800) 150 #define RK3588_DSU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00) 151 152 enum { 153 /* CRU_CLK_SEL8_CON */ 154 ACLK_LOW_TOP_ROOT_SRC_SEL_SHIFT = 14, 155 ACLK_LOW_TOP_ROOT_SRC_SEL_MASK = 1 << ACLK_LOW_TOP_ROOT_SRC_SEL_SHIFT, 156 ACLK_LOW_TOP_ROOT_SRC_SEL_GPLL = 0, 157 ACLK_LOW_TOP_ROOT_SRC_SEL_CPLL, 158 ACLK_LOW_TOP_ROOT_DIV_SHIFT = 9, 159 ACLK_LOW_TOP_ROOT_DIV_MASK = 0x1f << ACLK_LOW_TOP_ROOT_DIV_SHIFT, 160 PCLK_TOP_ROOT_SEL_SHIFT = 7, 161 PCLK_TOP_ROOT_SEL_MASK = 3 << PCLK_TOP_ROOT_SEL_SHIFT, 162 PCLK_TOP_ROOT_SEL_100M = 0, 163 PCLK_TOP_ROOT_SEL_50M, 164 PCLK_TOP_ROOT_SEL_24M, 165 ACLK_TOP_ROOT_SRC_SEL_SHIFT = 5, 166 ACLK_TOP_ROOT_SRC_SEL_MASK = 3 << ACLK_TOP_ROOT_SRC_SEL_SHIFT, 167 ACLK_TOP_ROOT_SRC_SEL_GPLL = 0, 168 ACLK_TOP_ROOT_SRC_SEL_CPLL, 169 ACLK_TOP_ROOT_SRC_SEL_AUPLL, 170 ACLK_TOP_ROOT_DIV_SHIFT = 0, 171 ACLK_TOP_ROOT_DIV_MASK = 0x1f << ACLK_TOP_ROOT_DIV_SHIFT, 172 173 /* CRU_CLK_SEL9_CON */ 174 ACLK_TOP_S400_SEL_SHIFT = 8, 175 ACLK_TOP_S400_SEL_MASK = 3 << ACLK_TOP_S400_SEL_SHIFT, 176 ACLK_TOP_S400_SEL_400M = 0, 177 ACLK_TOP_S400_SEL_200M, 178 ACLK_TOP_S200_SEL_SHIFT = 6, 179 ACLK_TOP_S200_SEL_MASK = 3 << ACLK_TOP_S200_SEL_SHIFT, 180 ACLK_TOP_S200_SEL_200M = 0, 181 ACLK_TOP_S200_SEL_100M, 182 183 /* CRU_CLK_SEL38_CON */ 184 CLK_I2C8_SEL_SHIFT = 13, 185 CLK_I2C8_SEL_MASK = 1 << CLK_I2C8_SEL_SHIFT, 186 CLK_I2C7_SEL_SHIFT = 12, 187 CLK_I2C7_SEL_MASK = 1 << CLK_I2C7_SEL_SHIFT, 188 CLK_I2C6_SEL_SHIFT = 11, 189 CLK_I2C6_SEL_MASK = 1 << CLK_I2C6_SEL_SHIFT, 190 CLK_I2C5_SEL_SHIFT = 10, 191 CLK_I2C5_SEL_MASK = 1 << CLK_I2C5_SEL_SHIFT, 192 CLK_I2C4_SEL_SHIFT = 9, 193 CLK_I2C4_SEL_MASK = 1 << CLK_I2C4_SEL_SHIFT, 194 CLK_I2C3_SEL_SHIFT = 8, 195 CLK_I2C3_SEL_MASK = 1 << CLK_I2C3_SEL_SHIFT, 196 CLK_I2C2_SEL_SHIFT = 7, 197 CLK_I2C2_SEL_MASK = 1 << CLK_I2C2_SEL_SHIFT, 198 CLK_I2C1_SEL_SHIFT = 6, 199 CLK_I2C1_SEL_MASK = 1 << CLK_I2C1_SEL_SHIFT, 200 ACLK_BUS_ROOT_SEL_SHIFT = 5, 201 ACLK_BUS_ROOT_SEL_MASK = 3 << ACLK_BUS_ROOT_SEL_SHIFT, 202 ACLK_BUS_ROOT_SEL_GPLL = 0, 203 ACLK_BUS_ROOT_SEL_CPLL, 204 ACLK_BUS_ROOT_DIV_SHIFT = 0, 205 ACLK_BUS_ROOT_DIV_MASK = 0x1f << ACLK_BUS_ROOT_DIV_SHIFT, 206 207 /* CRU_CLK_SEL40_CON */ 208 CLK_SARADC_SEL_SHIFT = 14, 209 CLK_SARADC_SEL_MASK = 0x1 << CLK_SARADC_SEL_SHIFT, 210 CLK_SARADC_SEL_GPLL = 0, 211 CLK_SARADC_SEL_24M, 212 CLK_SARADC_DIV_SHIFT = 6, 213 CLK_SARADC_DIV_MASK = 0xff << CLK_SARADC_DIV_SHIFT, 214 215 /* CRU_CLK_SEL41_CON */ 216 CLK_UART_SRC_SEL_SHIFT = 14, 217 CLK_UART_SRC_SEL_MASK = 0x1 << CLK_UART_SRC_SEL_SHIFT, 218 CLK_UART_SRC_SEL_GPLL = 0, 219 CLK_UART_SRC_SEL_CPLL, 220 CLK_UART_SRC_DIV_SHIFT = 9, 221 CLK_UART_SRC_DIV_MASK = 0x1f << CLK_UART_SRC_DIV_SHIFT, 222 CLK_TSADC_SEL_SHIFT = 8, 223 CLK_TSADC_SEL_MASK = 0x1 << CLK_TSADC_SEL_SHIFT, 224 CLK_TSADC_SEL_GPLL = 0, 225 CLK_TSADC_SEL_24M, 226 CLK_TSADC_DIV_SHIFT = 0, 227 CLK_TSADC_DIV_MASK = 0xff << CLK_TSADC_DIV_SHIFT, 228 229 /* CRU_CLK_SEL42_CON */ 230 CLK_UART_FRAC_NUMERATOR_SHIFT = 16, 231 CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16, 232 CLK_UART_FRAC_DENOMINATOR_SHIFT = 0, 233 CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff, 234 235 /* CRU_CLK_SEL43_CON */ 236 CLK_UART_SEL_SHIFT = 0, 237 CLK_UART_SEL_MASK = 0x3 << CLK_UART_SEL_SHIFT, 238 CLK_UART_SEL_SRC = 0, 239 CLK_UART_SEL_FRAC, 240 CLK_UART_SEL_XIN24M, 241 242 /* CRU_CLK_SEL59_CON */ 243 CLK_PWM2_SEL_SHIFT = 14, 244 CLK_PWM2_SEL_MASK = 3 << CLK_PWM2_SEL_SHIFT, 245 CLK_PWM1_SEL_SHIFT = 12, 246 CLK_PWM1_SEL_MASK = 3 << CLK_PWM1_SEL_SHIFT, 247 CLK_SPI4_SEL_SHIFT = 10, 248 CLK_SPI4_SEL_MASK = 3 << CLK_SPI4_SEL_SHIFT, 249 CLK_SPI3_SEL_SHIFT = 8, 250 CLK_SPI3_SEL_MASK = 3 << CLK_SPI3_SEL_SHIFT, 251 CLK_SPI2_SEL_SHIFT = 6, 252 CLK_SPI2_SEL_MASK = 3 << CLK_SPI2_SEL_SHIFT, 253 CLK_SPI1_SEL_SHIFT = 4, 254 CLK_SPI1_SEL_MASK = 3 << CLK_SPI1_SEL_SHIFT, 255 CLK_SPI0_SEL_SHIFT = 2, 256 CLK_SPI0_SEL_MASK = 3 << CLK_SPI0_SEL_SHIFT, 257 CLK_SPI_SEL_200M = 0, 258 CLK_SPI_SEL_150M, 259 CLK_SPI_SEL_24M, 260 261 /* CRU_CLK_SEL60_CON */ 262 CLK_PWM3_SEL_SHIFT = 0, 263 CLK_PWM3_SEL_MASK = 3 << CLK_PWM3_SEL_SHIFT, 264 CLK_PWM_SEL_100M = 0, 265 CLK_PWM_SEL_50M, 266 CLK_PWM_SEL_24M, 267 268 /* CRU_CLK_SEL62_CON */ 269 DCLK_DECOM_SEL_SHIFT = 5, 270 DCLK_DECOM_SEL_MASK = 1 << DCLK_DECOM_SEL_SHIFT, 271 DCLK_DECOM_SEL_GPLL = 0, 272 DCLK_DECOM_SEL_SPLL, 273 DCLK_DECOM_DIV_SHIFT = 0, 274 DCLK_DECOM_DIV_MASK = 0x1F << DCLK_DECOM_DIV_SHIFT, 275 276 /* CRU_CLK_SEL77_CON */ 277 CCLK_EMMC_SEL_SHIFT = 14, 278 CCLK_EMMC_SEL_MASK = 3 << CCLK_EMMC_SEL_SHIFT, 279 CCLK_EMMC_SEL_GPLL = 0, 280 CCLK_EMMC_SEL_CPLL, 281 CCLK_EMMC_SEL_24M, 282 CCLK_EMMC_DIV_SHIFT = 8, 283 CCLK_EMMC_DIV_MASK = 0x3f << CCLK_EMMC_DIV_SHIFT, 284 285 /* CRU_CLK_SEL78_CON */ 286 SCLK_SFC_SEL_SHIFT = 12, 287 SCLK_SFC_SEL_MASK = 3 << SCLK_SFC_SEL_SHIFT, 288 SCLK_SFC_SEL_GPLL = 0, 289 SCLK_SFC_SEL_CPLL, 290 SCLK_SFC_SEL_24M, 291 SCLK_SFC_DIV_SHIFT = 6, 292 SCLK_SFC_DIV_MASK = 0x3f << SCLK_SFC_DIV_SHIFT, 293 BCLK_EMMC_SEL_SHIFT = 5, 294 BCLK_EMMC_SEL_MASK = 1 << BCLK_EMMC_SEL_SHIFT, 295 BCLK_EMMC_SEL_GPLL = 0, 296 BCLK_EMMC_SEL_CPLL, 297 BCLK_EMMC_DIV_SHIFT = 0, 298 BCLK_EMMC_DIV_MASK = 0x1f << BCLK_EMMC_DIV_SHIFT, 299 300 /* CRU_CLK_SEL81_CON */ 301 CLK_GMAC1_PTP_SEL_SHIFT = 13, 302 CLK_GMAC1_PTP_SEL_MASK = 1 << CLK_GMAC1_PTP_SEL_SHIFT, 303 CLK_GMAC1_PTP_SEL_CPLL = 0, 304 CLK_GMAC1_PTP_DIV_SHIFT = 7, 305 CLK_GMAC1_PTP_DIV_MASK = 0x3f << CLK_GMAC1_PTP_DIV_SHIFT, 306 CLK_GMAC0_PTP_SEL_SHIFT = 6, 307 CLK_GMAC0_PTP_SEL_MASK = 1 << CLK_GMAC0_PTP_SEL_SHIFT, 308 CLK_GMAC0_PTP_SEL_CPLL = 0, 309 CLK_GMAC0_PTP_DIV_SHIFT = 0, 310 CLK_GMAC0_PTP_DIV_MASK = 0x3f << CLK_GMAC0_PTP_DIV_SHIFT, 311 312 /* CRU_CLK_SEL83_CON */ 313 CLK_GMAC_125M_SEL_SHIFT = 15, 314 CLK_GMAC_125M_SEL_MASK = 1 << CLK_GMAC_125M_SEL_SHIFT, 315 CLK_GMAC_125M_SEL_GPLL = 0, 316 CLK_GMAC_125M_SEL_CPLL, 317 CLK_GMAC_125M_DIV_SHIFT = 8, 318 CLK_GMAC_125M_DIV_MASK = 0x7f << CLK_GMAC_125M_DIV_SHIFT, 319 320 /* CRU_CLK_SEL84_CON */ 321 CLK_GMAC_50M_SEL_SHIFT = 7, 322 CLK_GMAC_50M_SEL_MASK = 1 << CLK_GMAC_50M_SEL_SHIFT, 323 CLK_GMAC_50M_SEL_GPLL = 0, 324 CLK_GMAC_50M_SEL_CPLL, 325 CLK_GMAC_50M_DIV_SHIFT = 0, 326 CLK_GMAC_50M_DIV_MASK = 0x7f << CLK_GMAC_50M_DIV_SHIFT, 327 328 /* CRU_CLK_SEL110_CON */ 329 HCLK_VOP_ROOT_SEL_SHIFT = 10, 330 HCLK_VOP_ROOT_SEL_MASK = 3 << HCLK_VOP_ROOT_SEL_SHIFT, 331 HCLK_VOP_ROOT_SEL_200M = 0, 332 HCLK_VOP_ROOT_SEL_100M, 333 HCLK_VOP_ROOT_SEL_50M, 334 HCLK_VOP_ROOT_SEL_24M, 335 ACLK_VOP_LOW_ROOT_SEL_SHIFT = 8, 336 ACLK_VOP_LOW_ROOT_SEL_MASK = 3 << ACLK_VOP_LOW_ROOT_SEL_SHIFT, 337 ACLK_VOP_LOW_ROOT_SEL_400M = 0, 338 ACLK_VOP_LOW_ROOT_SEL_200M, 339 ACLK_VOP_LOW_ROOT_SEL_100M, 340 ACLK_VOP_LOW_ROOT_SEL_24M, 341 ACLK_VOP_ROOT_SEL_SHIFT = 5, 342 ACLK_VOP_ROOT_SEL_MASK = 7 << ACLK_VOP_ROOT_SEL_SHIFT, 343 ACLK_VOP_ROOT_SEL_GPLL = 0, 344 ACLK_VOP_ROOT_SEL_CPLL, 345 ACLK_VOP_ROOT_SEL_AUPLL, 346 ACLK_VOP_ROOT_SEL_NPLL, 347 ACLK_VOP_ROOT_SEL_SPLL, 348 ACLK_VOP_ROOT_DIV_SHIFT = 0, 349 ACLK_VOP_ROOT_DIV_MASK = 0x1f << ACLK_VOP_ROOT_DIV_SHIFT, 350 351 /* CRU_CLK_SEL111_CON */ 352 DCLK1_VOP_SRC_SEL_SHIFT = 14, 353 DCLK1_VOP_SRC_SEL_MASK = 3 << DCLK1_VOP_SRC_SEL_SHIFT, 354 DCLK1_VOP_SRC_DIV_SHIFT = 9, 355 DCLK1_VOP_SRC_DIV_MASK = 0x1f << DCLK1_VOP_SRC_DIV_SHIFT, 356 DCLK0_VOP_SRC_SEL_SHIFT = 7, 357 DCLK0_VOP_SRC_SEL_MASK = 3 << DCLK0_VOP_SRC_SEL_SHIFT, 358 DCLK_VOP_SRC_SEL_GPLL = 0, 359 DCLK_VOP_SRC_SEL_CPLL, 360 DCLK_VOP_SRC_SEL_V0PLL, 361 DCLK_VOP_SRC_SEL_AUPLL, 362 DCLK0_VOP_SRC_DIV_SHIFT = 0, 363 DCLK0_VOP_SRC_DIV_MASK = 0x7f << DCLK0_VOP_SRC_DIV_SHIFT, 364 365 /* CRU_CLK_SEL112_CON */ 366 DCLK2_VOP_SEL_SHIFT = 11, 367 DCLK2_VOP_SEL_MASK = 3 << DCLK2_VOP_SEL_SHIFT, 368 DCLK1_VOP_SEL_SHIFT = 9, 369 DCLK1_VOP_SEL_MASK = 3 << DCLK1_VOP_SEL_SHIFT, 370 DCLK0_VOP_SEL_SHIFT = 7, 371 DCLK0_VOP_SEL_MASK = 3 << DCLK0_VOP_SEL_SHIFT, 372 DCLK2_VOP_SRC_SEL_SHIFT = 5, 373 DCLK2_VOP_SRC_SEL_MASK = 3 << DCLK2_VOP_SRC_SEL_SHIFT, 374 DCLK2_VOP_SRC_DIV_SHIFT = 0, 375 DCLK2_VOP_SRC_DIV_MASK = 0x1f << DCLK2_VOP_SRC_DIV_SHIFT, 376 377 /* CRU_CLK_SEL113_CON */ 378 DCLK3_VOP_SRC_SEL_SHIFT = 7, 379 DCLK3_VOP_SRC_SEL_MASK = 3 << DCLK3_VOP_SRC_SEL_SHIFT, 380 DCLK3_VOP_SRC_DIV_SHIFT = 0, 381 DCLK3_VOP_SRC_DIV_MASK = 0x7f << DCLK3_VOP_SRC_DIV_SHIFT, 382 383 /* CRU_CLK_SEL114_CON */ 384 CLK_DSIHOST_SEL_SHIFT = 7, 385 CLK_DSIHOST_SEL_MASK = 3 << CLK_DSIHOST_SEL_SHIFT, 386 CLK_DSIHOST_SEL_GPLL = 0, 387 CLK_DSIHOST_SEL_CPLL, 388 CLK_DSIHOST_SEL_V0PLL, 389 CLK_DSIHOST_SEL_SPLL, 390 CLK_DSIHOST_DIV_SHIFT = 0, 391 CLK_DSIHOST_DIV_MASK = 0X7F << CLK_DSIHOST_DIV_SHIFT, 392 393 /* CRU_CLK_SEL117_CON */ 394 CLK_AUX16MHZ_1_DIV_SHIFT = 8, 395 CLK_AUX16MHZ_1_DIV_MASK = 0xff << CLK_AUX16MHZ_1_DIV_SHIFT, 396 CLK_AUX16MHZ_0_DIV_SHIFT = 0, 397 CLK_AUX16MHZ_0_DIV_MASK = 0xff << CLK_AUX16MHZ_0_DIV_SHIFT, 398 399 /* CRU_CLK_SEL165_CON */ 400 PCLK_CENTER_ROOT_SEL_SHIFT = 6, 401 PCLK_CENTER_ROOT_SEL_MASK = 3 << PCLK_CENTER_ROOT_SEL_SHIFT, 402 PCLK_CENTER_ROOT_SEL_200M = 0, 403 PCLK_CENTER_ROOT_SEL_100M, 404 PCLK_CENTER_ROOT_SEL_50M, 405 PCLK_CENTER_ROOT_SEL_24M, 406 HCLK_CENTER_ROOT_SEL_SHIFT = 4, 407 HCLK_CENTER_ROOT_SEL_MASK = 3 << HCLK_CENTER_ROOT_SEL_SHIFT, 408 HCLK_CENTER_ROOT_SEL_400M = 0, 409 HCLK_CENTER_ROOT_SEL_200M, 410 HCLK_CENTER_ROOT_SEL_100M, 411 HCLK_CENTER_ROOT_SEL_24M, 412 ACLK_CENTER_LOW_ROOT_SEL_SHIFT = 2, 413 ACLK_CENTER_LOW_ROOT_SEL_MASK = 3 << ACLK_CENTER_LOW_ROOT_SEL_SHIFT, 414 ACLK_CENTER_LOW_ROOT_SEL_500M = 0, 415 ACLK_CENTER_LOW_ROOT_SEL_250M, 416 ACLK_CENTER_LOW_ROOT_SEL_100M, 417 ACLK_CENTER_LOW_ROOT_SEL_24M, 418 ACLK_CENTER_ROOT_SEL_SHIFT = 0, 419 ACLK_CENTER_ROOT_SEL_MASK = 3 << ACLK_CENTER_ROOT_SEL_SHIFT, 420 ACLK_CENTER_ROOT_SEL_700M = 0, 421 ACLK_CENTER_ROOT_SEL_400M, 422 ACLK_CENTER_ROOT_SEL_200M, 423 ACLK_CENTER_ROOT_SEL_24M, 424 425 /* CRU_CLK_SEL172_CON */ 426 CCLK_SDIO_SRC_SEL_SHIFT = 8, 427 CCLK_SDIO_SRC_SEL_MASK = 3 << CCLK_SDIO_SRC_SEL_SHIFT, 428 CCLK_SDIO_SRC_SEL_GPLL = 0, 429 CCLK_SDIO_SRC_SEL_CPLL, 430 CCLK_SDIO_SRC_SEL_24M, 431 CCLK_SDIO_SRC_DIV_SHIFT = 2, 432 CCLK_SDIO_SRC_DIV_MASK = 0x3f << CCLK_SDIO_SRC_DIV_SHIFT, 433 434 /* CRU_CLK_SEL176_CON */ 435 CLK_PCIE_PHY1_PLL_DIV_SHIFT = 6, 436 CLK_PCIE_PHY1_PLL_DIV_MASK = 0x3f << CLK_PCIE_PHY1_PLL_DIV_SHIFT, 437 CLK_PCIE_PHY0_PLL_DIV_SHIFT = 0, 438 CLK_PCIE_PHY0_PLL_DIV_MASK = 0x3f << CLK_PCIE_PHY0_PLL_DIV_SHIFT, 439 440 /* CRU_CLK_SEL177_CON */ 441 CLK_PCIE_PHY2_REF_SEL_SHIFT = 8, 442 CLK_PCIE_PHY2_REF_SEL_MASK = 1 << CLK_PCIE_PHY2_REF_SEL_SHIFT, 443 CLK_PCIE_PHY1_REF_SEL_SHIFT = 7, 444 CLK_PCIE_PHY1_REF_SEL_MASK = 1 << CLK_PCIE_PHY1_REF_SEL_SHIFT, 445 CLK_PCIE_PHY0_REF_SEL_SHIFT = 6, 446 CLK_PCIE_PHY0_REF_SEL_MASK = 1 << CLK_PCIE_PHY0_REF_SEL_SHIFT, 447 CLK_PCIE_PHY_REF_SEL_24M = 0, 448 CLK_PCIE_PHY_REF_SEL_PPLL, 449 CLK_PCIE_PHY2_PLL_DIV_SHIFT = 0, 450 CLK_PCIE_PHY2_PLL_DIV_MASK = 0x3f << CLK_PCIE_PHY2_PLL_DIV_SHIFT, 451 452 /* PMUCRU_CLK_SEL2_CON */ 453 CLK_PMU1PWM_SEL_SHIFT = 9, 454 CLK_PMU1PWM_SEL_MASK = 3 << CLK_PMU1PWM_SEL_SHIFT, 455 456 /* PMUCRU_CLK_SEL3_CON */ 457 CLK_I2C0_SEL_SHIFT = 6, 458 CLK_I2C0_SEL_MASK = 1 << CLK_I2C0_SEL_SHIFT, 459 CLK_I2C_SEL_200M = 0, 460 CLK_I2C_SEL_100M, 461 }; 462 #endif 463