1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7 #ifndef _ASM_ARCH_CRU_RK3576_H 8 #define _ASM_ARCH_CRU_RK3576_H 9 10 #define MHz 1000000 11 #define KHz 1000 12 #define OSC_HZ (24 * MHz) 13 14 #define CPU_PVTPLL_HZ (1008 * MHz) 15 #define LPLL_HZ (816 * MHz) 16 #define GPLL_HZ (1188 * MHz) 17 #define CPLL_HZ (1000 * MHz) 18 #define PPLL_HZ (1100 * MHz) 19 #define GMAC0_PTP_REFCLK_IN (24 * MHz) 20 #define GMAC1_PTP_REFCLK_IN (24 * MHz) 21 /* RK3576 pll id */ 22 enum rk3576_pll_id { 23 BPLL, 24 LPLL, 25 DPLL, 26 CPLL, 27 GPLL, 28 VPLL, 29 AUPLL, 30 SPLL, 31 PPLL, 32 PLL_COUNT, 33 }; 34 35 struct rk3576_clk_info { 36 unsigned long id; 37 char *name; 38 bool is_cru; 39 }; 40 41 struct rk3576_clk_priv { 42 struct rk3576_cru *cru; 43 struct rk3576_grf *grf; 44 ulong ppll_hz; 45 ulong gpll_hz; 46 ulong cpll_hz; 47 ulong vpll_hz; 48 ulong aupll_hz; 49 ulong spll_hz; 50 ulong lpll_hz; 51 ulong bpll_hz; 52 ulong armclk_hz; 53 ulong armclk_enter_hz; 54 ulong armclk_init_hz; 55 bool sync_kernel; 56 bool set_armclk_rate; 57 }; 58 59 struct rk3576_pll { 60 unsigned int con0; 61 unsigned int con1; 62 unsigned int con2; 63 unsigned int con3; 64 unsigned int con4; 65 unsigned int reserved0[3]; 66 }; 67 68 struct rk3576_cru { 69 struct rk3576_pll pll[18]; 70 unsigned int reserved0[16];/* Address Offset: 0x0240 */ 71 unsigned int mode_con00;/* Address Offset: 0x0280 */ 72 unsigned int reserved1[31];/* Address Offset: 0x0284 */ 73 unsigned int clksel_con[181]; /* Address Offset: 0x0300 */ 74 unsigned int reserved2[139];/* Address Offset: 0x05d4 */ 75 unsigned int clkgate_con[80];/* Address Offset: 0x0800 */ 76 unsigned int reserved3[48];/* Address Offset: 0x0938 */ 77 unsigned int softrst_con[80];/* Address Offset: 0x0400 */ 78 unsigned int reserved4[48];/* Address Offset: 0x0b38 */ 79 unsigned int glb_cnt_th;/* Address Offset: 0x0c00 */ 80 unsigned int glb_rst_st;/* Address Offset: 0x0c04 */ 81 unsigned int glb_srst_fst;/* Address Offset: 0x0c08 */ 82 unsigned int glb_srsr_snd; /* Address Offset: 0x0c0c */ 83 unsigned int glb_rst_con;/* Address Offset: 0x0c10 */ 84 unsigned int reserved5[43];/* Address Offset: 0x0c14 */ 85 unsigned int smoth_divfree_con[3];/* Address Offset: 0x0cc0 */ 86 unsigned int fracdiv_high_con[4];/* Address Offset: 0x0ccc */ 87 unsigned int reserved8[32137];/* Address Offset: 0x0c38 */ 88 unsigned int pmuclksel_con[22]; /* Address Offset: 0x20300 */ 89 unsigned int reserved9[298];/* Address Offset: 0x20358 */ 90 unsigned int pmuclkgate_con[8]; /* Address Offset: 0x20800 */ 91 unsigned int reserved10[32440];/* Address Offset: 0x20820 */ 92 unsigned int litclksel_con[4]; /* Address Offset: 0x40300 */ 93 }; 94 95 check_member(rk3576_cru, mode_con00, 0x280); 96 check_member(rk3576_cru, pmuclksel_con[1], 0x20304); 97 98 struct pll_rate_table { 99 unsigned long rate; 100 unsigned int m; 101 unsigned int p; 102 unsigned int s; 103 unsigned int k; 104 }; 105 106 #define RK3576_PHP_CRU_BASE 0x8000 107 #define RK3576_PMU_CRU_BASE 0x20000 108 #define RK3576_BIGCORE_CRU_BASE 0x38000 109 #define RK3576_LITCORE_CRU_BASE 0x40000 110 #define RK3576_CCI_CRU_BASE 0x48000 111 #define RK3576_CRU_BASE 0x27200000 112 #define RK3576_SCRU_BASE 0x27214000 113 114 #define RK3576_BIGCORE_GRF_BASE 0x2600C000 115 #define RK3576_LITCORE_GRF_BASE 0x2600E000 116 #define RK3576_CCI_GRF_BASE 0x26010000 117 118 #define RK3576_PLL_CON(x) ((x) * 0x4) 119 #define RK3576_MODE_CON0 0x280 120 #define RK3576_BPLL_MODE_CON0 (RK3576_BIGCORE_CRU_BASE + 0x280) 121 #define RK3576_LPLL_MODE_CON0 (RK3576_LITCORE_CRU_BASE + 0x280) 122 #define RK3576_PPLL_MODE_CON0 (RK3576_PHP_CRU_BASE + 0x280) 123 #define RK3576_CLKSEL_CON(x) ((x) * 0x4 + 0x300) 124 #define RK3576_CLKGATE_CON(x) ((x) * 0x4 + 0x800) 125 #define RK3576_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) 126 #define RK3576_GLB_CNT_TH 0xc00 127 #define RK3576_GLB_SRST_FST 0xc08 128 #define RK3576_GLB_SRST_SND 0xc0c 129 #define RK3576_GLB_RST_CON 0xc10 130 #define RK3576_GLB_RST_ST 0xc04 131 #define RK3576_SDIO_CON0 0xC24 132 #define RK3576_SDIO_CON1 0xC28 133 #define RK3576_SDMMC_CON0 0xC30 134 #define RK3576_SDMMC_CON1 0xC34 135 136 #define RK3576_PHP_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x300) 137 #define RK3576_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x800) 138 #define RK3576_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0xa00) 139 140 #define RK3576_PMU_PLL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE) 141 #define RK3576_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x300) 142 #define RK3576_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x800) 143 #define RK3576_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0xa00) 144 145 #define RK3576_CCI_CLKSEL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x300) 146 #define RK3576_CCI_CLKGATE_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x800) 147 #define RK3576_CCI_SOFTRST_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0xa00) 148 149 #define RK3576_BPLL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE) 150 #define RK3576_BIGCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x300) 151 #define RK3576_BIGCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x800) 152 #define RK3576_BIGCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0xa00) 153 #define RK3576_LPLL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE) 154 #define RK3576_LITCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x300) 155 #define RK3576_LITCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x800) 156 #define RK3576_LITCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0xa00) 157 158 enum { 159 /* CRU_CLK_SEL8_CON */ 160 PCLK_TOP_SEL_SHIFT = 7, 161 PCLK_TOP_SEL_MASK = 3 << PCLK_TOP_SEL_SHIFT, 162 PCLK_TOP_SEL_100M = 0, 163 PCLK_TOP_SEL_50M, 164 PCLK_TOP_SEL_OSC, 165 166 /* CRU_CLK_SEL9_CON */ 167 ACLK_TOP_SEL_SHIFT = 5, 168 ACLK_TOP_SEL_MASK = 3 << ACLK_TOP_SEL_SHIFT, 169 ACLK_TOP_SEL_GPLL = 0, 170 ACLK_TOP_SEL_CPLL, 171 ACLK_TOP_SEL_AUPLL, 172 ACLK_TOP_DIV_SHIFT = 0, 173 ACLK_TOP_DIV_MASK = 0x1f << ACLK_TOP_DIV_SHIFT, 174 175 /* CRU_CLK_SEL10_CON */ 176 ACLK_TOP_MID_SEL_SHIFT = 5, 177 ACLK_TOP_MID_SEL_MASK = 1 << ACLK_TOP_MID_SEL_SHIFT, 178 ACLK_TOP_MID_SEL_GPLL = 0, 179 ACLK_TOP_MID_SEL_CPLL, 180 ACLK_TOP_MID_DIV_SHIFT = 0, 181 ACLK_TOP_MID_DIV_MASK = 0x1f << ACLK_TOP_MID_DIV_SHIFT, 182 183 /* CRU_CLK_SEL19_CON */ 184 HCLK_TOP_SEL_SHIFT = 2, 185 HCLK_TOP_SEL_MASK = 3 << HCLK_TOP_SEL_SHIFT, 186 HCLK_TOP_SEL_200M = 0, 187 HCLK_TOP_SEL_100M, 188 HCLK_TOP_SEL_50M, 189 HCLK_TOP_SEL_OSC, 190 191 /* CRU_CLK_SEL25_CON */ 192 CLK_UART_FRAC_NUMERATOR_SHIFT = 16, 193 CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16, 194 CLK_UART_FRAC_DENOMINATOR_SHIFT = 0, 195 CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff, 196 197 /* CRU_CLK_SEL26_CON */ 198 CLK_UART_SRC_SEL_SHIFT = 0, 199 CLK_UART_SRC_SEL_MASK = 0x3 << CLK_UART_SRC_SEL_SHIFT, 200 CLK_UART_SRC_SEL_GPLL = 0, 201 CLK_UART_SRC_SEL_CPLL, 202 CLK_UART_SRC_SEL_AUPLL, 203 CLK_UART_SRC_SEL_OSC, 204 205 /* CRU_CLK_SEL27_CON */ 206 CLK_UART1_SRC_SEL_SHIFT = 13, 207 CLK_UART1_SRC_SEL_MASK = 0x7 << CLK_UART1_SRC_SEL_SHIFT, 208 CLK_UART1_SRC_DIV_SHIFT = 5, 209 CLK_UART1_SRC_DIV_MASK = 0xff << CLK_UART1_SRC_DIV_SHIFT, 210 211 /* CRU_CLK_SEL30_CON */ 212 CLK_GMAC0_125M_DIV_SHIFT = 10, 213 CLK_GMAC0_125M_DIV_MASK = 0x1f << CLK_GMAC0_125M_DIV_SHIFT, 214 215 /* CRU_CLK_SEL31_CON */ 216 CLK_GMAC1_125M_DIV_SHIFT = 0, 217 CLK_GMAC1_125M_DIV_MASK = 0x1f << CLK_GMAC1_125M_DIV_SHIFT, 218 219 /* CRU_CLK_SEL33_CON */ 220 REF_CLK0_OUT_PLL_SEL_SHIFT = 8, 221 REF_CLK0_OUT_PLL_SEL_MASK = 7 << REF_CLK0_OUT_PLL_SEL_SHIFT, 222 REF_CLK0_OUT_PLL_SEL_GPLL = 0, 223 REF_CLK0_OUT_PLL_SEL_CPLL, 224 REF_CLK0_OUT_PLL_SEL_SPLL, 225 REF_CLK0_OUT_PLL_SEL_AUPLL, 226 REF_CLK0_OUT_PLL_SEL_LPLL, 227 REF_CLK0_OUT_PLL_SEL_OSC, 228 REF_CLK0_OUT_PLL_DIV_SHIFT = 0, 229 REF_CLK0_OUT_PLL_DIV_MASK = 0xff << REF_CLK0_OUT_PLL_DIV_SHIFT, 230 231 /* CRU_CLK_SEL55_CON */ 232 ACLK_BUS_ROOT_SEL_SHIFT = 9, 233 ACLK_BUS_ROOT_SEL_MASK = 1 << ACLK_BUS_ROOT_SEL_SHIFT, 234 ACLK_BUS_ROOT_SEL_GPLL = 0, 235 ACLK_BUS_ROOT_SEL_CPLL, 236 ACLK_BUS_ROOT_DIV_SHIFT = 4, 237 ACLK_BUS_ROOT_DIV_MASK = 0x1f << ACLK_BUS_ROOT_DIV_SHIFT, 238 PCLK_BUS_ROOT_SEL_SHIFT = 2, 239 PCLK_BUS_ROOT_SEL_MASK = 3 << PCLK_BUS_ROOT_SEL_SHIFT, 240 PCLK_BUS_ROOT_SEL_100M = 0, 241 PCLK_BUS_ROOT_SEL_50M, 242 PCLK_BUS_ROOT_SEL_OSC, 243 HCLK_BUS_ROOT_SEL_SHIFT = 0, 244 HCLK_BUS_ROOT_SEL_MASK = 3 << HCLK_BUS_ROOT_SEL_SHIFT, 245 HCLK_BUS_ROOT_SEL_200M = 0, 246 HCLK_BUS_ROOT_SEL_100M, 247 HCLK_BUS_ROOT_SEL_50M, 248 HCLK_BUS_ROOT_SEL_OSC, 249 250 /* CRU_CLK_SEL57_CON */ 251 CLK_I2C8_SEL_SHIFT = 14, 252 CLK_I2C8_SEL_MASK = 3 << CLK_I2C8_SEL_SHIFT, 253 CLK_I2C7_SEL_SHIFT = 12, 254 CLK_I2C7_SEL_MASK = 3 << CLK_I2C7_SEL_SHIFT, 255 CLK_I2C6_SEL_SHIFT = 10, 256 CLK_I2C6_SEL_MASK = 3 << CLK_I2C6_SEL_SHIFT, 257 CLK_I2C5_SEL_SHIFT = 8, 258 CLK_I2C5_SEL_MASK = 3 << CLK_I2C5_SEL_SHIFT, 259 CLK_I2C4_SEL_SHIFT = 6, 260 CLK_I2C4_SEL_MASK = 3 << CLK_I2C4_SEL_SHIFT, 261 CLK_I2C3_SEL_SHIFT = 4, 262 CLK_I2C3_SEL_MASK = 3 << CLK_I2C3_SEL_SHIFT, 263 CLK_I2C2_SEL_SHIFT = 2, 264 CLK_I2C2_SEL_MASK = 3 << CLK_I2C2_SEL_SHIFT, 265 CLK_I2C1_SEL_SHIFT = 0, 266 CLK_I2C1_SEL_MASK = 3 << CLK_I2C1_SEL_SHIFT, 267 CLK_I2C_SEL_200M = 0, 268 CLK_I2C_SEL_100M, 269 CLK_I2C_SEL_50M, 270 CLK_I2C_SEL_OSC, 271 272 /* CRU_CLK_SEL58_CON */ 273 CLK_SARADC_SEL_SHIFT = 12, 274 CLK_SARADC_SEL_MASK = 0x1 << CLK_SARADC_SEL_SHIFT, 275 CLK_SARADC_SEL_GPLL = 0, 276 CLK_SARADC_SEL_OSC, 277 CLK_SARADC_DIV_SHIFT = 4, 278 CLK_SARADC_DIV_MASK = 0xff << CLK_SARADC_DIV_SHIFT, 279 CLK_I2C9_SEL_SHIFT = 0, 280 CLK_I2C9_SEL_MASK = 3 << CLK_I2C9_SEL_SHIFT, 281 282 /* CRU_CLK_SEL59_CON */ 283 CLK_TSADC_DIV_SHIFT = 0, 284 CLK_TSADC_DIV_MASK = 0xff << CLK_TSADC_DIV_SHIFT, 285 286 /* CRU_CLK_SEL60_CON */ 287 CLK_UART_SEL_SHIFT = 8, 288 CLK_UART_SEL_MASK = 7 << CLK_UART_SEL_SHIFT, 289 CLK_UART_SEL_GPLL = 0, 290 CLK_UART_SEL_CPLL, 291 CLK_UART_SEL_AUPLL, 292 CLK_UART_SEL_OSC, 293 CLK_UART_SEL_FRAC0, 294 CLK_UART_SEL_FRAC1, 295 CLK_UART_SEL_FRAC2, 296 CLK_UART_DIV_SHIFT = 0, 297 CLK_UART_DIV_MASK = 0xff << CLK_UART_DIV_SHIFT, 298 299 /* CRU_CLK_SEL70_CON */ 300 CLK_SPI0_SEL_SHIFT = 13, 301 CLK_SPI0_SEL_MASK = 3 << CLK_SPI0_SEL_SHIFT, 302 CLK_SPI_SEL_200M = 0, 303 CLK_SPI_SEL_100M, 304 CLK_SPI_SEL_50M, 305 CLK_SPI_SEL_OSC, 306 307 /* CRU_CLK_SEL71_CON */ 308 CLK_PWM1_SEL_SHIFT = 8, 309 CLK_PWM1_SEL_MASK = 3 << CLK_PWM1_SEL_SHIFT, 310 CLK_SPI4_SEL_SHIFT = 6, 311 CLK_SPI4_SEL_MASK = 3 << CLK_SPI4_SEL_SHIFT, 312 CLK_SPI3_SEL_SHIFT = 4, 313 CLK_SPI3_SEL_MASK = 3 << CLK_SPI3_SEL_SHIFT, 314 CLK_SPI2_SEL_SHIFT = 2, 315 CLK_SPI2_SEL_MASK = 3 << CLK_SPI2_SEL_SHIFT, 316 CLK_SPI1_SEL_SHIFT = 0, 317 CLK_SPI1_SEL_MASK = 3 << CLK_SPI1_SEL_SHIFT, 318 CLK_PWM_SEL_100M = 0, 319 CLK_PWM_SEL_50M, 320 CLK_PWM_SEL_OSC, 321 322 /* CRU_CLK_SEL72_CON */ 323 DCLK_DECOM_SEL_SHIFT = 5, 324 DCLK_DECOM_SEL_MASK = 1 << DCLK_DECOM_SEL_SHIFT, 325 DCLK_DECOM_SEL_GPLL = 0, 326 DCLK_DECOM_SEL_SPLL, 327 DCLK_DECOM_DIV_SHIFT = 0, 328 DCLK_DECOM_DIV_MASK = 0x1f << DCLK_DECOM_DIV_SHIFT, 329 330 /* CRU_CLK_SEL74_CON */ 331 CLK_PWM2_SEL_SHIFT = 6, 332 CLK_PWM2_SEL_MASK = 3 << CLK_PWM2_SEL_SHIFT, 333 334 /* CRU_CLK_SEL89_CON */ 335 CCLK_EMMC_SEL_SHIFT = 14, 336 CCLK_EMMC_SEL_MASK = 3 << CCLK_EMMC_SEL_SHIFT, 337 CCLK_EMMC_SEL_GPLL = 0, 338 CCLK_EMMC_SEL_CPLL, 339 CCLK_EMMC_SEL_OSC, 340 CCLK_EMMC_DIV_SHIFT = 8, 341 CCLK_EMMC_DIV_MASK = 0x3f << CCLK_EMMC_DIV_SHIFT, 342 SCLK_FSPI_SEL_SHIFT = 6, 343 SCLK_FSPI_SEL_MASK = 3 << SCLK_FSPI_SEL_SHIFT, 344 SCLK_FSPI_SEL_GPLL = 0, 345 SCLK_FSPI_SEL_CPLL, 346 SCLK_FSPI_SEL_OSC, 347 SCLK_FSPI_DIV_SHIFT = 0, 348 SCLK_FSPI_DIV_MASK = 0x3f << SCLK_FSPI_DIV_SHIFT, 349 350 /* CRU_CLK_SEL90_CON */ 351 BCLK_EMMC_SEL_SHIFT = 0, 352 BCLK_EMMC_SEL_MASK = 3 << BCLK_EMMC_SEL_SHIFT, 353 BCLK_EMMC_SEL_200M = 0, 354 BCLK_EMMC_SEL_100M, 355 BCLK_EMMC_SEL_50M, 356 BCLK_EMMC_SEL_OSC, 357 358 /* CRU_CLK_SEL104_CON */ 359 CLK_GMAC1_PTP_SEL_SHIFT = 13, 360 CLK_GMAC1_PTP_SEL_MASK = 3 << CLK_GMAC1_PTP_SEL_SHIFT, 361 CLK_GMAC1_PTP_SEL_GPLL = 0, 362 CLK_GMAC1_PTP_SEL_CPLL, 363 CLK_GMAC1_PTP_SEL_REFIN, 364 CLK_GMAC1_PTP_DIV_SHIFT = 8, 365 CLK_GMAC1_PTP_DIV_MASK = 0x1f << CLK_GMAC1_PTP_DIV_SHIFT, 366 CCLK_SDIO_SRC_SEL_SHIFT = 6, 367 CCLK_SDIO_SRC_SEL_MASK = 3 << CCLK_SDIO_SRC_SEL_SHIFT, 368 CCLK_SDIO_SRC_SEL_GPLL = 0, 369 CCLK_SDIO_SRC_SEL_CPLL, 370 CCLK_SDIO_SRC_SEL_OSC, 371 CCLK_SDIO_SRC_DIV_SHIFT = 0, 372 CCLK_SDIO_SRC_DIV_MASK = 0x3f << CCLK_SDIO_SRC_DIV_SHIFT, 373 374 /* CRU_CLK_SEL105_CON */ 375 CCLK_SDMMC0_SRC_SEL_SHIFT = 13, 376 CCLK_SDMMC0_SRC_SEL_MASK = 3 << CCLK_SDMMC0_SRC_SEL_SHIFT, 377 CCLK_SDMMC0_SRC_SEL_GPLL = 0, 378 CCLK_SDMMC0_SRC_SEL_CPLL, 379 CCLK_SDMMC0_SRC_SEL_OSC, 380 CCLK_SDMMC0_SRC_DIV_SHIFT = 7, 381 CCLK_SDMMC0_SRC_DIV_MASK = 0x3f << CCLK_SDMMC0_SRC_DIV_SHIFT, 382 CLK_GMAC0_PTP_SEL_SHIFT = 5, 383 CLK_GMAC0_PTP_SEL_MASK = 3 << CLK_GMAC0_PTP_SEL_SHIFT, 384 CLK_GMAC0_PTP_SEL_GPLL = 0, 385 CLK_GMAC0_PTP_SEL_CPLL, 386 CLK_GMAC0_PTP_SEL_REFIN, 387 CLK_GMAC0_PTP_DIV_SHIFT = 0, 388 CLK_GMAC0_PTP_DIV_MASK = 0x1f << CLK_GMAC0_PTP_DIV_SHIFT, 389 390 /* CRU_CLK_SEL123_CON */ 391 DCLK_EBC_SEL_SHIFT = 12, 392 DCLK_EBC_SEL_MASK = 7 << DCLK_EBC_SEL_SHIFT, 393 DCLK_EBC_SEL_GPLL = 0, 394 DCLK_EBC_SEL_CPLL, 395 DCLK_EBC_SEL_VPLL, 396 DCLK_EBC_SEL_AUPLL, 397 DCLK_EBC_SEL_LPLL, 398 DCLK_EBC_SEL_FRAC_SRC, 399 DCLK_EBC_SEL_OSC, 400 DCLK_EBC_DIV_SHIFT = 3, 401 DCLK_EBC_DIV_MASK = 0x1ff << DCLK_EBC_DIV_SHIFT, 402 DCLK_EBC_FRAC_SRC_SEL_SHIFT = 0, 403 DCLK_EBC_FRAC_SRC_SEL_MASK = 7 << DCLK_EBC_FRAC_SRC_SEL_SHIFT, 404 DCLK_EBC_FRAC_SRC_SEL_GPLL = 0, 405 DCLK_EBC_FRAC_SRC_SEL_CPLL, 406 DCLK_EBC_FRAC_SRC_SEL_VPLL, 407 DCLK_EBC_FRAC_SRC_SEL_AUPLL, 408 DCLK_EBC_FRAC_SRC_SEL_OSC, 409 410 /* CRU_CLK_SEL144_CON */ 411 PCLK_VOP_ROOT_SEL_SHIFT = 12, 412 PCLK_VOP_ROOT_SEL_MASK = 3 << PCLK_VOP_ROOT_SEL_SHIFT, 413 PCLK_VOP_ROOT_SEL_100M = 0, 414 PCLK_VOP_ROOT_SEL_50M, 415 PCLK_VOP_ROOT_SEL_OSC, 416 HCLK_VOP_ROOT_SEL_SHIFT = 10, 417 HCLK_VOP_ROOT_SEL_MASK = 3 << HCLK_VOP_ROOT_SEL_SHIFT, 418 HCLK_VOP_ROOT_SEL_200M = 0, 419 HCLK_VOP_ROOT_SEL_100M, 420 HCLK_VOP_ROOT_SEL_50M, 421 HCLK_VOP_ROOT_SEL_OSC, 422 ACLK_VOP_ROOT_SEL_SHIFT = 5, 423 ACLK_VOP_ROOT_SEL_MASK = 7 << ACLK_VOP_ROOT_SEL_SHIFT, 424 ACLK_VOP_ROOT_SEL_GPLL = 0, 425 ACLK_VOP_ROOT_SEL_CPLL, 426 ACLK_VOP_ROOT_SEL_AUPLL, 427 ACLK_VOP_ROOT_SEL_SPLL, 428 ACLK_VOP_ROOT_SEL_LPLL, 429 ACLK_VOP_ROOT_DIV_SHIFT = 0, 430 ACLK_VOP_ROOT_DIV_MASK = 0x1f << ACLK_VOP_ROOT_DIV_SHIFT, 431 432 /* CRU_CLK_SEL145_CON */ 433 DCLK0_VOP_SRC_SEL_SHIFT = 8, 434 DCLK0_VOP_SRC_SEL_MASK = 7 << DCLK0_VOP_SRC_SEL_SHIFT, 435 DCLK_VOP_SRC_SEL_GPLL = 0, 436 DCLK_VOP_SRC_SEL_CPLL, 437 DCLK_VOP_SRC_SEL_VPLL, 438 DCLK_VOP_SRC_SEL_BPLL, 439 DCLK_VOP_SRC_SEL_LPLL, 440 DCLK0_VOP_SRC_DIV_SHIFT = 0, 441 DCLK0_VOP_SRC_DIV_MASK = 0xff << DCLK0_VOP_SRC_DIV_SHIFT, 442 443 /* CRU_CLK_SEL147_CON */ 444 DCLK2_VOP_SEL_SHIFT = 13, 445 DCLK2_VOP_SEL_MASK = 1 << DCLK2_VOP_SEL_SHIFT, 446 DCLK1_VOP_SEL_SHIFT = 12, 447 DCLK1_VOP_SEL_MASK = 1 << DCLK1_VOP_SEL_SHIFT, 448 DCLK0_VOP_SEL_SHIFT = 11, 449 DCLK0_VOP_SEL_MASK = 1 << DCLK0_VOP_SEL_SHIFT, 450 451 /* CRU_CLK_SEL149_CON */ 452 ACLK_VO0_ROOT_SEL_SHIFT = 5, 453 ACLK_VO0_ROOT_SEL_MASK = 3 << ACLK_VO0_ROOT_SEL_SHIFT, 454 ACLK_VO0_ROOT_SEL_GPLL = 0, 455 ACLK_VO0_ROOT_SEL_CPLL, 456 ACLK_VO0_ROOT_SEL_LPLL, 457 ACLK_VO0_ROOT_SEL_BPLL, 458 ACLK_VO0_ROOT_DIV_SHIFT = 0, 459 ACLK_VO0_ROOT_DIV_MASK = 0x1f << ACLK_VO0_ROOT_DIV_SHIFT, 460 461 /* CRU_CLK_SEL151_CON */ 462 CLK_DSIHOST0_SEL_SHIFT = 7, 463 CLK_DSIHOST0_SEL_MASK = 7 << CLK_DSIHOST0_SEL_SHIFT, 464 CLK_DSIHOST0_SEL_GPLL = 0, 465 CLK_DSIHOST0_SEL_CPLL, 466 CLK_DSIHOST0_SEL_SPLL, 467 CLK_DSIHOST0_SEL_VPLL, 468 CLK_DSIHOST0_SEL_BPLL, 469 CLK_DSIHOST0_SEL_LPLL, 470 CLK_DSIHOST0_DIV_SHIFT = 0, 471 CLK_DSIHOST0_DIV_MASK = 0x7f << CLK_DSIHOST0_DIV_SHIFT, 472 473 /* PMUCRU_CLK_SEL5_CON */ 474 CLK_PMU1PWM_SEL_SHIFT = 2, 475 CLK_PMU1PWM_SEL_MASK = 3 << CLK_PMU1PWM_SEL_SHIFT, 476 477 /* PMUCRU_CLK_SEL6_CON */ 478 CLK_I2C0_SEL_SHIFT = 7, 479 CLK_I2C0_SEL_MASK = 3 << CLK_I2C0_SEL_SHIFT, 480 481 /* PMUCRU_CLK_SEL8_CON */ 482 CLK_UART1_SEL_SHIFT = 0, 483 CLK_UART1_SEL_MASK = 1 << CLK_UART1_SEL_SHIFT, 484 CLK_UART1_SEL_TOP = 0, 485 CLK_UART1_SEL_OSC, 486 487 /* LITCRU_CLK_SEL0_CON */ 488 CLK_LITCORE_SEL_SHIFT = 12, 489 CLK_LITCORE_SEL_MASK = 3 << CLK_LITCORE_SEL_SHIFT, 490 CLK_LITCORE_SEL_LPLL = 0, 491 CLK_LITCORE_SEL_GPLL, 492 CLK_LITCORE_SEL_PVTPLL, 493 CLK_LITCORE_DIV_SHIFT = 7, 494 CLK_LITCORE_DIV_MASK = 0x1f << CLK_LITCORE_DIV_SHIFT, 495 496 /* BIGCRU_CLK_SEL1_CON */ 497 CLK_BIGCORE_SEL_SHIFT = 12, 498 CLK_BIGCORE_SEL_MASK = 3 << CLK_BIGCORE_SEL_SHIFT, 499 CLK_BIGCORE_SEL_LPLL = 0, 500 CLK_BIGCORE_SEL_GPLL, 501 CLK_BIGCORE_SEL_PVTPLL, 502 CLK_BIGCORE_DIV_SHIFT = 7, 503 CLK_BIGCORE_DIV_MASK = 0x1f << CLK_BIGCORE_DIV_SHIFT, 504 }; 505 #endif 506