Lines Matching refs:E_FIQH_START
206 #define FIQ_VIVALDI_STR (0x1 << (E_FIQ_VIVALDI_STR - E_FIQH_START) )
207 #define FIQ_VIVALDI_PTS (0x1 << (E_FIQ_VIVALDI_PTS - E_FIQH_START) )
208 #define FIQ_DSP_MIU_PROT (0x1 << (E_FIQ_DSP_MIU_PROT - E_FIQH_START) )
209 #define FIQ_XIU_TIMEOUT (0x1 << (E_FIQ_XIU_TIMEOUT - E_FIQH_START) )
210 #define FIQ_DMDMCU2HK (0x1 << (E_FIQ_DMDMCU2HK - E_FIQH_START) )
211 #define FIQ_VSYNC_VE4VBI (0x1 << (E_FIQ_VSYNC_VE4VBI - E_FIQH_START) )
212 #define FIQ_FIELD_VE4VBI (0x1 << (E_FIQ_FIELD_VE4VBI - E_FIQH_START) )
213 #define FIQ_VDMCU2HK (0x1 << (E_FIQ_VDMCU2HK - E_FIQH_START) )
214 #define FIQ_VE_DONE_TT (0x1 << (E_FIQ_VE_DONE_TT - E_FIQH_START) )
215 #define FIQ_INT_CCFL (0x1 << (E_FIQ_INT_CCFL - E_FIQH_START) )
216 #define FIQ_INT (0x1 << (E_FIQ_INT - E_FIQH_START) )
217 #define FIQ_IR (0x1 << (E_FIQ_IR - E_FIQH_START) )
218 #define FIQ_AFEC_VSYNC (0x1 << (E_FIQ_AFEC_VSYNC - E_FIQH_START) )
219 #define FIQ_DEC_DSP2UP (0x1 << (E_FIQ_DEC_DSP2UP - E_FIQH_START) )
220 #define FIQ_FRC_R2_TO_MIPS (0x1 << (E_FIQ_FRC_R2_TO_MIPS - E_FIQH_START) )
221 #define FIQ_DSP2MIPS (0x1 << (E_FIQ_DSP2MIPS - E_FIQH_START) )