Lines Matching refs:E_IRQEXPH_START
329 #define IRQEXPH_BDMA0 (0x01 << (E_IRQ_48 - E_IRQEXPH_START))
330 #define IRQEXPH_BDMA1 (0x01 << (E_IRQ_49 - E_IRQEXPH_START))
331 #define IRQEXPH_UART2MCU (0x01 << (E_IRQ_50 - E_IRQEXPH_START))
332 #define IRQEXPH_URDMA2MCU (0x01 << (E_IRQ_51 - E_IRQEXPH_START))
333 #define IRQEXPH_DVI_HDMI_HDCP (0x01 << (E_IRQ_52 - E_IRQEXPH_START))
334 #define IRQEXPH_G3D2MCU (0x01 << (E_IRQ_53 - E_IRQEXPH_START))
335 #define IRQEXPH_CEC (0x01 << (E_IRQ_54 - E_IRQEXPH_START))
336 #define IRQEXPH_HDCP_IIC (0x01 << (E_IRQ_55 - E_IRQEXPH_START))
337 #define IRQEXPH_HDCP_X74 (0x01 << (E_IRQ_56 - E_IRQEXPH_START))
338 #define IRQEXPH_WADR_ERR (0x01 << (E_IRQ_57 - E_IRQEXPH_START))
339 #define IRQEXPH_DCSUB (0x01 << (E_IRQ_58 - E_IRQEXPH_START))
340 #define IRQEXPH_GE (0x01 << (E_IRQ_59 - E_IRQEXPH_START))
341 #define IRQEXPH_MIIC_DMA1 (0x01 << (E_IRQ_60 - E_IRQEXPH_START))
342 #define IRQEXPH_MIIC_INT1 (0x01 << (E_IRQ_61 - E_IRQEXPH_START))
343 #define IRQEXPH_MIIC_DMA0 (0x01 << (E_IRQ_62 - E_IRQEXPH_START))
344 #define IRQEXPH_MIIC_INT0 (0x01 << (E_IRQ_63 - E_IRQEXPH_START))