Lines Matching refs:HAL_UpdateIrqTable
451 static void HAL_UpdateIrqTable(MS_U32 byHardwareIndex, MS_U32 bySoftwareIndex) in HAL_UpdateIrqTable() function
480 HAL_UpdateIrqTable(E_IRQ_00, E_INT_IRQ_UART0); //int_uart0 in HAL_InitIrqTable()
481 HAL_UpdateIrqTable(E_IRQ_01, E_INT_IRQ_MIIC_INT1); //miic1_int in HAL_InitIrqTable()
482 HAL_UpdateIrqTable(E_IRQ_02, E_INT_IRQ_MVD2MIPS); //mvd2mips_int in HAL_InitIrqTable()
483 HAL_UpdateIrqTable(E_IRQ_03, E_INT_IRQ_MVD); //mvd_int in HAL_InitIrqTable()
484 HAL_UpdateIrqTable(E_IRQ_04, E_INT_IRQ_FIQ_NONE); //~reg_top_gpio_in[2] in HAL_InitIrqTable()
485 HAL_UpdateIrqTable(E_IRQ_05, E_INT_IRQ_CA_NSK_INT); //ca_nsk_int in HAL_InitIrqTable()
486 HAL_UpdateIrqTable(E_IRQ_06, E_INT_IRQ_USB); //usb_int in HAL_InitIrqTable()
487 HAL_UpdateIrqTable(E_IRQ_07, E_INT_IRQ_UHC); //uhc_int in HAL_InitIrqTable()
488 HAL_UpdateIrqTable(E_IRQ_08, E_INT_IRQ_ZDEC); //zdec_irq in HAL_InitIrqTable()
489 HAL_UpdateIrqTable(E_IRQ_09, E_INT_IRQ_GMAC); //gmac_int in HAL_InitIrqTable()
490 HAL_UpdateIrqTable(E_IRQ_10, E_INT_IRQ_DISP); //disp_int in HAL_InitIrqTable()
491 HAL_UpdateIrqTable(E_IRQ_11, E_INT_IRQ_DHC); //dhc_int in HAL_InitIrqTable()
492 HAL_UpdateIrqTable(E_IRQ_12, E_INT_IRQ_MSPI0); //mspi_int in HAL_InitIrqTable()
493 HAL_UpdateIrqTable(E_IRQ_13, E_INT_IRQ_EVD); //evd_int in HAL_InitIrqTable()
494 HAL_UpdateIrqTable(E_IRQ_14, E_INT_IRQ_EVD_LITE); //evd_lite_int in HAL_InitIrqTable()
495 HAL_UpdateIrqTable(E_IRQ_15, E_INT_IRQ_FIQ_NONE); //Reserved. in HAL_InitIrqTable()
497 HAL_UpdateIrqTable(E_IRQ_16, E_INT_IRQ_TSP2HK); //tsp2hk_int in HAL_InitIrqTable()
498 HAL_UpdateIrqTable(E_IRQ_17, E_INT_IRQ_VE); //ve_int in HAL_InitIrqTable()
499 HAL_UpdateIrqTable(E_IRQ_18, E_INT_IRQ_AEON2HI); //irq_aeon2hi in HAL_InitIrqTable()
500 HAL_UpdateIrqTable(E_IRQ_19, E_INT_IRQ_DC); //dc_int in HAL_InitIrqTable()
501 HAL_UpdateIrqTable(E_IRQ_20, E_INT_IRQ_GOP); //gop_int in HAL_InitIrqTable()
502 HAL_UpdateIrqTable(E_IRQ_21, E_INT_IRQ_FIQ_NONE); //Reserved. in HAL_InitIrqTable()
503 HAL_UpdateIrqTable(E_IRQ_22, E_INT_IRQ_MIIC_INT0); //miic0_int in HAL_InitIrqTable()
504 HAL_UpdateIrqTable(E_IRQ_23, E_INT_IRQ_RTC); //rtc0_int in HAL_InitIrqTable()
505 HAL_UpdateIrqTable(E_IRQ_24, E_INT_IRQ_KEYPAD); //keypad_int in HAL_InitIrqTable()
506 HAL_UpdateIrqTable(E_IRQ_25, E_INT_IRQ_PM); //pm_int in HAL_InitIrqTable()
507 HAL_UpdateIrqTable(E_IRQ_26, E_INT_IRQ_MFE); //mfe_int in HAL_InitIrqTable()
508 HAL_UpdateIrqTable(E_IRQ_27, E_INT_FIQ_UP_IRQ_EMM_ECM); //up_irq_emm_ecm in HAL_InitIrqTable()
509 HAL_UpdateIrqTable(E_IRQ_28, E_INT_IRQ_UP_IRQ_UART_CA); //up_irq_uart_ca in HAL_InitIrqTable()
510 HAL_UpdateIrqTable(E_IRQ_29, E_INT_IRQ_RTC1); //rtc1_int in HAL_InitIrqTable()
511 HAL_UpdateIrqTable(E_IRQ_30, E_INT_IRQ_CA_IP_INT); //ca_ip_int in HAL_InitIrqTable()
512 HAL_UpdateIrqTable(E_IRQ_31, E_INT_IRQ_ADCDVI2RIU); //adcdvi2riu_int in HAL_InitIrqTable()
514 HAL_UpdateIrqTable(E_IRQ_32, E_INT_IRQ_TSP_TSO0); //tsp_tso0_int in HAL_InitIrqTable()
515 HAL_UpdateIrqTable(E_IRQ_33, E_INT_IRQ_USB1); //usb_int1 in HAL_InitIrqTable()
516 HAL_UpdateIrqTable(E_IRQ_34, E_INT_IRQ_UHC1); //uhc_int1 in HAL_InitIrqTable()
517 HAL_UpdateIrqTable(E_IRQ_35, E_INT_IRQ_MIU); //miu_int in HAL_InitIrqTable()
518 HAL_UpdateIrqTable(E_IRQ_36, E_INT_IRQ_ERROR_RESP); //error_resp_int in HAL_InitIrqTable()
519 HAL_UpdateIrqTable(E_IRQ_37, E_INT_IRQ_OTG); //otg_int in HAL_InitIrqTable()
520 HAL_UpdateIrqTable(E_IRQ_38, E_INT_IRQ_FIQ_NONE); //Reserved. in HAL_InitIrqTable()
521 HAL_UpdateIrqTable(E_IRQ_39, E_INT_IRQ_UART1); //int_uart1 in HAL_InitIrqTable()
522 HAL_UpdateIrqTable(E_IRQ_40, E_INT_IRQ_SVD_HVD); //hvd_int in HAL_InitIrqTable()
523 HAL_UpdateIrqTable(E_IRQ_41, E_INT_IRQ_FIQ_NONE); //reg_top_gpio_in[4] in HAL_InitIrqTable()
524 HAL_UpdateIrqTable(E_IRQ_42, E_INT_IRQ_FIQ_NONE); //~reg_top_gpio_in[4] in HAL_InitIrqTable()
525 HAL_UpdateIrqTable(E_IRQ_43, E_INT_IRQ_EMMC_OSP_INT); //emmc_osp_int in HAL_InitIrqTable()
526 HAL_UpdateIrqTable(E_IRQ_44, E_INT_IRQ_CA_RSA_INT0); //ca_crypto_dma_int in HAL_InitIrqTable()
527 HAL_UpdateIrqTable(E_IRQ_45, E_INT_IRQ_JPD); //jpd_int in HAL_InitIrqTable()
528 HAL_UpdateIrqTable(E_IRQ_46, E_INT_IRQ_DISP1); //disp1_int in HAL_InitIrqTable()
529 HAL_UpdateIrqTable(E_IRQ_47, E_INT_IRQ_AKL_INT); //akl_intrrupt in HAL_InitIrqTable()
531 HAL_UpdateIrqTable(E_IRQ_48, E_INT_IRQ_BDMA0); //int_bdma[0] in HAL_InitIrqTable()
532 HAL_UpdateIrqTable(E_IRQ_49, E_INT_IRQ_BDMA1); //int_bdma[1] in HAL_InitIrqTable()
533 HAL_UpdateIrqTable(E_IRQ_50, E_INT_IRQ_UART2MCU); //uart2mcu_intr in HAL_InitIrqTable()
534 HAL_UpdateIrqTable(E_IRQ_51, E_INT_IRQ_URDMA2MCU); //urdma2mcu_intr in HAL_InitIrqTable()
535 HAL_UpdateIrqTable(E_IRQ_52, E_INT_IRQ_FIQ_NONE); //Reserved. in HAL_InitIrqTable()
536 HAL_UpdateIrqTable(E_IRQ_53, E_INT_IRQ_CEC); //cec_irq_out in HAL_InitIrqTable()
537 HAL_UpdateIrqTable(E_IRQ_54, E_INT_IRQ_HDMI_LEVEL); //HDMITX_IRQ_LEVEL in HAL_InitIrqTable()
538 HAL_UpdateIrqTable(E_IRQ_55, E_INT_IRQ_FCIE2RIU); //fcie_int in HAL_InitIrqTable()
539 HAL_UpdateIrqTable(E_IRQ_56, E_INT_IRQ_HDCP_X74); //hdcp_x74_int in HAL_InitIrqTable()
540 HAL_UpdateIrqTable(E_IRQ_57, E_INT_IRQ_GPD); //gpd_int in HAL_InitIrqTable()
541 HAL_UpdateIrqTable(E_IRQ_58, E_INT_IRQ_SAR1); //SAR1_int in HAL_InitIrqTable()
542 HAL_UpdateIrqTable(E_IRQ_59, E_INT_IRQ_IDAC_PLUG_DET); //irq_dac_plug_det in HAL_InitIrqTable()
543 HAL_UpdateIrqTable(E_IRQ_60, E_INT_IRQ_FIQ_NONE); //reg_top_gpio_in[2] in HAL_InitIrqTable()
544 HAL_UpdateIrqTable(E_IRQ_61, E_INT_IRQ_RASP); //rasp0_int in HAL_InitIrqTable()
545 HAL_UpdateIrqTable(E_IRQ_62, E_INT_IRQ_TSP_FI_QUEUE_INT); //fi_queue_int in HAL_InitIrqTable()
546 HAL_UpdateIrqTable(E_IRQ_63, E_INT_IRQ_FRM_PM); //irq_frm_pm in HAL_InitIrqTable()
547 HAL_UpdateIrqTable(E_IRQ_64, E_INT_IRQ_MIIC_INT2); //miic2_int in HAL_InitIrqTable()
548 HAL_UpdateIrqTable(E_IRQ_65, E_INT_IRQ_MIIC_INT3); //miic3_int in HAL_InitIrqTable()
549 HAL_UpdateIrqTable(E_IRQ_66, E_INT_IRQ_MIIC_INT4); //miic4_int in HAL_InitIrqTable()
550 HAL_UpdateIrqTable(E_IRQ_67, E_INT_IRQ_MIIC_INT5); //miic5_int in HAL_InitIrqTable()
551 HAL_UpdateIrqTable(E_IRQ_68, E_INT_IRQ_HDMITX); //hdmitx_phy_int in HAL_InitIrqTable()
552 HAL_UpdateIrqTable(E_IRQ_69, E_INT_IRQ_GE); //ge_int in HAL_InitIrqTable()
553 HAL_UpdateIrqTable(E_IRQ_70, E_INT_IRQ_MIU_SECURE); //miu_security_int in HAL_InitIrqTable()
554 HAL_UpdateIrqTable(E_IRQ_71, E_INT_IRQ_FIQ_NONE); //Reserved. in HAL_InitIrqTable()
555 HAL_UpdateIrqTable(E_IRQ_72, E_INT_IRQ_G3D2MCU); //g3d2mcu_irq_dft in HAL_InitIrqTable()
556 HAL_UpdateIrqTable(E_IRQ_73, E_INT_FIQEXPH_CMDQ); //cmdq_int in HAL_InitIrqTable()
557 HAL_UpdateIrqTable(E_IRQ_74, E_INT_IRQ_AUDMA_V2_INT); //AUDMA_V2_INTR in HAL_InitIrqTable()
558 HAL_UpdateIrqTable(E_IRQ_75, E_INT_IRQ_SCDC_PM_INT); //scdc_int_pm in HAL_InitIrqTable()
559 HAL_UpdateIrqTable(E_IRQ_76, E_FRCINT_IRQ_MSPI2); //mspi2_int in HAL_InitIrqTable()
560 HAL_UpdateIrqTable(E_IRQ_77, E_INT_IRQ_SMART); //smart_int0 in HAL_InitIrqTable()
561 HAL_UpdateIrqTable(E_IRQ_78, E_INT_IRQ_FIQ_NONE); //Reserved.. in HAL_InitIrqTable()
562 HAL_UpdateIrqTable(E_IRQ_79, E_INT_IRQ_DCSUB); //dc_sub_int in HAL_InitIrqTable()
563 HAL_UpdateIrqTable(E_IRQ_80, E_INT_IRQ_SDIO); //sdio_int in HAL_InitIrqTable()
564 HAL_UpdateIrqTable(E_IRQ_81, E_INT_IRQ_EMAC); //emac in HAL_InitIrqTable()
565 HAL_UpdateIrqTable(E_IRQ_82, E_INT_IRQ_FIQ_NONE); //Reserved. in HAL_InitIrqTable()
566 HAL_UpdateIrqTable(E_IRQ_83, E_INT_IRQ_FIQ_NONE); //Reserved. in HAL_InitIrqTable()
567 HAL_UpdateIrqTable(E_IRQ_84, E_INT_IRQ_FIQ_NONE); //Reserved. in HAL_InitIrqTable()
568 HAL_UpdateIrqTable(E_IRQ_85, E_INT_IRQ_FIQ_NONE); //Reserved in HAL_InitIrqTable()
569 HAL_UpdateIrqTable(E_IRQ_86, E_INT_IRQ_USB2); //ubb_int_p2 in HAL_InitIrqTable()
570 HAL_UpdateIrqTable(E_IRQ_87, E_INT_IRQ_UHC2); //uhc_int_p2 in HAL_InitIrqTable()
571 HAL_UpdateIrqTable(E_IRQ_88, E_INT_IRQ_FIQ_NONE); //miu_ns_int in HAL_InitIrqTable()
572 HAL_UpdateIrqTable(E_IRQ_89, E_INT_IRQ_FIQ_NONE); //Reserved. in HAL_InitIrqTable()
573 HAL_UpdateIrqTable(E_IRQ_90, E_INT_IRQ_VIVALDI_V9_MIU_AL); //INT_v9_mui_al in HAL_InitIrqTable()
574 HAL_UpdateIrqTable(E_IRQ_91, E_INT_IRQ_SDIO_OSP_INT); //sdio_osp_int in HAL_InitIrqTable()
575 HAL_UpdateIrqTable(E_IRQ_92, E_INT_IRQ_MIU_TLB_INT); //miu_tlb_int in HAL_InitIrqTable()
576 HAL_UpdateIrqTable(E_IRQ_93, E_INT_IRQ_DIPW); //dipw_INT in HAL_InitIrqTable()
577 …HAL_UpdateIrqTable(E_IRQ_94, E_INT_IRQ_FIQ_NONE); //diamond_reg_rxiu_timeout_nodefin… in HAL_InitIrqTable()
578 HAL_UpdateIrqTable(E_IRQ_95, E_INT_IRQ_PAS_PTS_COMBINE_INT); //PAS_PTS_INTRL_COMBINE in HAL_InitIrqTable()
580 HAL_UpdateIrqTable(E_FIQ_00, E_INT_FIQ_EXTIMER0); //int_timer0 in HAL_InitIrqTable()
581 HAL_UpdateIrqTable(E_FIQ_01, E_INT_FIQ_EXTIMER1); //int_timer1 in HAL_InitIrqTable()
582 HAL_UpdateIrqTable(E_FIQ_02, E_INT_FIQ_WDT); //int_wdt in HAL_InitIrqTable()
583 HAL_UpdateIrqTable(E_FIQ_03, E_INT_FIQ_SEC_TIMER0); //int_sec_timer0 in HAL_InitIrqTable()
584 HAL_UpdateIrqTable(E_FIQ_04, E_INT_FIQ_SEC_TIMER1); //int_sec_timer1 in HAL_InitIrqTable()
585 HAL_UpdateIrqTable(E_FIQ_05, E_INT_FIQ_R2TOMCU_INT0); //MB_auR2to_MCU_INT[0] in HAL_InitIrqTable()
586 HAL_UpdateIrqTable(E_FIQ_06, E_INT_FIQ_DSPTOMCU_INT0); //MB_DSP2toMCU_INT[0] in HAL_InitIrqTable()
587 HAL_UpdateIrqTable(E_FIQ_07, E_INT_FIQ_DSPTOMCU_INT1); //MB_DSP2toMCU_INT[1] in HAL_InitIrqTable()
588 HAL_UpdateIrqTable(E_FIQ_08, E_INT_FIQ_R2TOMCU_INT1); //MB_auR2to_MCU_INT[1] in HAL_InitIrqTable()
589 HAL_UpdateIrqTable(E_FIQ_09, E_INT_FIQ_UP_IRQ_UART_CA); //up_irq_uart_ca in HAL_InitIrqTable()
590 HAL_UpdateIrqTable(E_FIQ_10, E_INT_FIQ_R2TOMCU_INT2); //MB_auR2to_MCU_INT[2] in HAL_InitIrqTable()
591 HAL_UpdateIrqTable(E_FIQ_11, E_INT_FIQ_HDMI_NON_PCM); //HDMI_NON_PCM_MODE_INT_OUT in HAL_InitIrqTable()
592 HAL_UpdateIrqTable(E_FIQ_12, E_INT_FIQ_SPDIF_IN_NON_PCM); //SPDIF_IN_NON_PCM_INT_OUT in HAL_InitIrqTable()
593 HAL_UpdateIrqTable(E_FIQ_13, E_INT_FIQ_LAN_ESD_INT); //lan_esd_int in HAL_InitIrqTable()
594 HAL_UpdateIrqTable(E_FIQ_14, E_INT_FIQ_SE_DSP2UP); //SE_DSP2UP_intr in HAL_InitIrqTable()
595 HAL_UpdateIrqTable(E_FIQ_15, E_INT_FIQ_TSP2AEON); //tsp2aeon_int in HAL_InitIrqTable()
597 HAL_UpdateIrqTable(E_FIQ_16, E_INT_FIQ_VIVALDI_STR); //vivaldi_str_intr in HAL_InitIrqTable()
598 HAL_UpdateIrqTable(E_FIQ_17, E_INT_FIQ_VIVALDI_PTS); //vivaldi_pts_intr in HAL_InitIrqTable()
599 HAL_UpdateIrqTable(E_FIQ_18, E_INT_FIQ_DSP_MIU_PROT); //DSP_MIU_PROT_intr in HAL_InitIrqTable()
600 HAL_UpdateIrqTable(E_FIQ_19, E_INT_FIQ_XIU_TIMEOUT); //xiu_timeout_int in HAL_InitIrqTable()
601 HAL_UpdateIrqTable(E_FIQ_20, E_INT_IRQ_FIQ_NONE); //Reserved. in HAL_InitIrqTable()
602 HAL_UpdateIrqTable(E_FIQ_21, E_INT_FIQ_VSYNC_VE4VBI); //ve_vbi_f0_int in HAL_InitIrqTable()
603 HAL_UpdateIrqTable(E_FIQ_22, E_INT_FIQ_FIELD_VE4VBI); //ve_vbi_f1_int in HAL_InitIrqTable()
604 HAL_UpdateIrqTable(E_FIQ_23, E_INT_FIQ_R2TOMCU_INT3); //MB_auR2to_MCU_INT[3] in HAL_InitIrqTable()
605 HAL_UpdateIrqTable(E_FIQ_24, E_INT_FIQ_VE_DONE_TT); //ve_done_TT_irq in HAL_InitIrqTable()
606 HAL_UpdateIrqTable(E_FIQ_25, E_INT_FIQ_INT_CCFL); //INT_CCFL in HAL_InitIrqTable()
607 HAL_UpdateIrqTable(E_FIQ_26, E_INT_IRQ_FIQ_NONE); //int_in in HAL_InitIrqTable()
608 HAL_UpdateIrqTable(E_FIQ_27, E_INT_FIQ_IR); //ir_int in HAL_InitIrqTable()
609 HAL_UpdateIrqTable(E_FIQ_28, E_INT_FIQ_AU_SPDIF_TX_CS0); //AU_SPDIF_TX_CS_INT[0] in HAL_InitIrqTable()
610 HAL_UpdateIrqTable(E_FIQ_29, E_INT_IRQ_FIQ_NONE); //Reserved in HAL_InitIrqTable()
611 HAL_UpdateIrqTable(E_FIQ_30, E_INT_FIQ_AU_SPDIF_TX_CS1); //AU_SPDIF_TX_CS_INT[1] in HAL_InitIrqTable()
612 HAL_UpdateIrqTable(E_FIQ_31, E_INT_FIQ_DEC_DSP2MIPS); //DSP2MIPS_INT in HAL_InitIrqTable()
614 HAL_UpdateIrqTable(E_FIQ_32, E_INT_FIQ_IR_INT_RC); //ir_int_rc in HAL_InitIrqTable()
615 HAL_UpdateIrqTable(E_FIQ_33, E_INT_FIQ_AU_DMA_BUF_INT); //AU_DMA_BUFFER_INT_EDGE in HAL_InitIrqTable()
616 HAL_UpdateIrqTable(E_FIQ_34, E_INT_FIQ_VE_SW_WR2BUF); //ve_sw_wr2buf_int in HAL_InitIrqTable()
617 HAL_UpdateIrqTable(E_FIQ_35, E_INT_IRQ_UP_IRQ_EMM_ECM); //up_irq_emm_ecm in HAL_InitIrqTable()
618 …HAL_UpdateIrqTable(E_FIQ_36, E_INT_IRQ_FIQ_NONE); //reg_hst0to3_int # HOST 0 - PM … in HAL_InitIrqTable()
619 …HAL_UpdateIrqTable(E_FIQ_37, E_INT_FIQ_8051_TO_BEON); //reg_hst0to2_int # HOST 1 - Sec… in HAL_InitIrqTable()
620 …HAL_UpdateIrqTable(E_FIQ_38, E_INT_FIQ_8051_TO_SECURER2); //reg_hst0to1_int # HOST 2 - ACP… in HAL_InitIrqTable()
621 …HAL_UpdateIrqTable(E_FIQ_39, E_INT_IRQ_FIQ_NONE); //Reserved # HOST 3 - Se… in HAL_InitIrqTable()
622 HAL_UpdateIrqTable(E_FIQ_40, E_INT_IRQ_FIQ_NONE); //reg_hst1to3_int in HAL_InitIrqTable()
623 HAL_UpdateIrqTable(E_FIQ_41, E_INT_FIQ_SECURER2_TO_BEON); //reg_hst1to2_int in HAL_InitIrqTable()
624 HAL_UpdateIrqTable(E_FIQ_42, E_INT_FIQ_SECURER2_TO_8051); //reg_hst1to0_int in HAL_InitIrqTable()
625 HAL_UpdateIrqTable(E_FIQ_43, E_INT_IRQ_FIQ_NONE); //Reserved. in HAL_InitIrqTable()
626 HAL_UpdateIrqTable(E_FIQ_44, E_INT_IRQ_FIQ_NONE); //reg_hst2to3_int in HAL_InitIrqTable()
627 HAL_UpdateIrqTable(E_FIQ_45, E_INT_FIQ_BEON_TO_SECURER2); //reg_hst2to1_int in HAL_InitIrqTable()
628 HAL_UpdateIrqTable(E_FIQ_46, E_INT_FIQ_BEON_TO_8051); //reg_hst2to0_int in HAL_InitIrqTable()
629 HAL_UpdateIrqTable(E_FIQ_47, E_INT_IRQ_FIQ_NONE); //Reserved. in HAL_InitIrqTable()
631 HAL_UpdateIrqTable(E_FIQ_48, E_INT_IRQ_FIQ_NONE); //reg_hst3to2_int in HAL_InitIrqTable()
632 HAL_UpdateIrqTable(E_FIQ_49, E_INT_IRQ_FIQ_NONE); //reg_hst3to1_int in HAL_InitIrqTable()
633 HAL_UpdateIrqTable(E_FIQ_50, E_INT_IRQ_FIQ_NONE); //reg_hst3to0_int in HAL_InitIrqTable()
634 HAL_UpdateIrqTable(E_FIQ_51, E_INT_IRQ_FIQ_NONE); //Reserved. in HAL_InitIrqTable()
635 HAL_UpdateIrqTable(E_FIQ_52, E_INT_IRQ_FIQ_NONE); //Reserved. in HAL_InitIrqTable()
636 HAL_UpdateIrqTable(E_FIQ_53, E_INT_IRQ_FIQ_NONE); //Reserved. in HAL_InitIrqTable()
637 HAL_UpdateIrqTable(E_FIQ_54, E_INT_FIQ_HDMITX_IRQ_EDGE); //HDMITX_IRQ_EDGE in HAL_InitIrqTable()
638 HAL_UpdateIrqTable(E_FIQ_55, E_INT_IRQ_FIQ_NONE); //Reserved. in HAL_InitIrqTable()
639 HAL_UpdateIrqTable(E_FIQ_56, E_INT_FIQ_CA_CRYPTO_DMA); //crypto_dma_int in HAL_InitIrqTable()
640 HAL_UpdateIrqTable(E_FIQ_57, E_INT_IRQ_FIQ_NONE); //Reserved in HAL_InitIrqTable()
641 HAL_UpdateIrqTable(E_FIQ_58, E_INT_IRQ_FIQ_NONE); //Reserved in HAL_InitIrqTable()
642 HAL_UpdateIrqTable(E_FIQ_59, E_INT_IRQ_FIQ_NONE); //Reserved in HAL_InitIrqTable()
643 HAL_UpdateIrqTable(E_FIQ_60, E_INT_IRQ_FIQ_NONE); //Reserved in HAL_InitIrqTable()
644 HAL_UpdateIrqTable(E_FIQ_61, E_INT_IRQ_FIQ_NONE); //Reserved in HAL_InitIrqTable()
645 HAL_UpdateIrqTable(E_FIQ_62, E_INT_IRQ_FIQ_NONE); //Reserved in HAL_InitIrqTable()
646 HAL_UpdateIrqTable(E_FIQ_63, E_INT_FIQ_FRM_PM); //fiq_frm_pm in HAL_InitIrqTable()
648 HAL_UpdateIrqTable(E_FIQ_64, E_INT_FIQ_SEC_GUARD_INT); //sec_guard_int in HAL_InitIrqTable()
649 HAL_UpdateIrqTable(E_FIQ_65, E_INT_FIQ_PM_SD_CDZ0); //SD_CDZ_IN in HAL_InitIrqTable()