Lines Matching refs:MOD_A_W2BYTEMSK
195 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, 0x00, BIT(8)); in MHal_MOD_PowerOn()
204 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, BIT(0) , BIT(0)); in MHal_MOD_PowerOn()
208 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0x00 , BIT(0)); in MHal_MOD_PowerOn()
210 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, BIT(8) , BIT(8)); in MHal_MOD_PowerOn()
218 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, (BIT(1) | BIT(0)), (BIT(1) | BIT(0))); in MHal_MOD_PowerOn()
271 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, BIT(8), BIT(8)); in MHal_MOD_PowerOn()
274 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, BIT(0), BIT(0)); //analog MOD po… in MHal_MOD_PowerOn()
275 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0x00, BIT(8)); in MHal_MOD_PowerOn()
278 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0, (BIT(1) | BIT(0) )); //enable ib… in MHal_MOD_PowerOn()
286 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0020,0x0020); in MHal_MOD_PowerOn()
290 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0000,0x0020); in MHal_MOD_PowerOn()
329 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x5550, 0xFFF0); in MHal_Output_LVDS_Pair_Setting()
334 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x5550, 0xFFF0); in MHal_Output_LVDS_Pair_Setting()
344 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x5550, 0xFFF0); in MHal_Output_LVDS_Pair_Setting()
504 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x1F, 0x1F); //open all clk
597 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, u8Clk, 0x1F);
607 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x0F, 0x1F);
611 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x0F, 0x1F);
616 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x1F, 0x1F);
621 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x03, 0x1F);
626 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x03, 0x1F);
630 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x1F, 0x1F);
1868 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, 0, BIT(15)); in MHal_PNL_PreSetModeOn()
1872 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, BIT(15), BIT(15)); in MHal_PNL_PreSetModeOn()
2131 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0, BIT(15)); in MHal_PNL_MOD_Control_Out_Swing()
2218 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_18_L, in MHal_PNL_MOD_PECurrent_Setting()
2228 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_19_L, in MHal_PNL_MOD_PECurrent_Setting()
2238 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_1A_L, in MHal_PNL_MOD_PECurrent_Setting()
2248 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_1B_L, in MHal_PNL_MOD_PECurrent_Setting()
2267 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_34_L, 0xFFFF, 0xFFFF); //Enable TTL low-power mode in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2270 … MOD_A_W2BYTEMSK(REG_MOD_A_BK00_32_L, 0xFFFF, 0xFFFF); //GCR_EN_RINT (internal termination open) in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2273 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3C_L, 0xFFFF, 0xFFFF); //Disable DRIVER BIAS OP in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2278 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_34_L, 0x0000, 0xFFFF); //Disable TTL low-power mode in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2281 … MOD_A_W2BYTEMSK(REG_MOD_A_BK00_32_L, 0x0000, 0xFFFF); //GCR_EN_RINT (internal termination close) in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2284 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3C_L, 0x0000, 0xFFFF); //Enable DRIVER BIAS OP in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2349 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0, BIT(15)); in msSetVBY1RconValue()
2390 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0020,0x0020); in MHal_PNL_SetOutputType()
2394 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0000,0x0020); in MHal_PNL_SetOutputType()
2405 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, 0x3FF, 0x3FF); // TTL skew in MHal_PNL_SetOutputType()
2460 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0020,0x0020); in MHal_PNL_SetOutputType()
2464 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0000,0x0020); in MHal_PNL_SetOutputType()
2561 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0xC01F , 0xFFFF); // enable clk_dot_mini_pre_osd & clk_dot_mi… in MHal_PNL_SetOutputType()
2563 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, BIT(15), BIT(15)); //[15]sw_rst in MHal_PNL_SetOutputType()
2564 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0xC000 , 0xF000); // enable clk_dot_mini_pre_osd & clk_dot_mi… in MHal_PNL_SetOutputType()
2573 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0020,0x0020); in MHal_PNL_SetOutputType()
2577 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0000,0x0020); in MHal_PNL_SetOutputType()
2588 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_40_L, 0x0FFF, 0x0FFF); in MHal_PNL_SetOutputType()
2590 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_48_L, 0x0FFF, 0x0FFF); in MHal_PNL_SetOutputType()
2592 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_44_L, 0x0000, 0x0FFF); in MHal_PNL_SetOutputType()
2594 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_42_L, 0x0000, 0x0FFF); in MHal_PNL_SetOutputType()
2597 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_40_L, 0xF000, 0xF000); in MHal_PNL_SetOutputType()
2600 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_48_L, 0xF000, 0xF000); in MHal_PNL_SetOutputType()
2603 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_44_L, 0x0000, 0xF000); in MHal_PNL_SetOutputType()
2606 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_42_L, 0x0000, 0xF000); in MHal_PNL_SetOutputType()
2621 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0, 0xF000); in MHal_PNL_SetOutputType()
2632 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_48_L, 0x0000, 0xF000); in MHal_PNL_SetOutputType()
2637 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0x00, BIT(0)); in MHal_PNL_SetOutputType()
2667 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_40_L, 0x0000, 0xF000); in MHal_PNL_SetOutputType()
2671 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, 0x000, 0x3FF); // TTL skew in MHal_PNL_SetOutputType()
2959 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_30_L, 0xFFFF, 0xFFFF); //reg_gcr_pe_en_ch in MHal_PNL_Init_MOD()
2960 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_32_L, 0x0000, 0xFFFF); //reg_gcr_en_rint_ch in MHal_PNL_Init_MOD()
2961 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3C_L, 0xFFFF, 0xFFFF); //reg_gcr_test_ch in MHal_PNL_Init_MOD()
3019 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0xC000, 0xF000); //bank selection for skew clock in MHal_PNL_Init_MOD()
3032 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_31_L, 0x0FFF, 0x3FFF); in MHal_PNL_Init_MOD()
3097 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, u16ChannelClk_En, 0x1F); //[4]ck_pd[3]ck_pc[2]ck_pb[1]ck_pa[0… in MHal_PNL_Init_MOD()
3102 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x1F, 0x1F); //[4]ck_pd[3]ck_pc[2]ck_pb[1]ck_pa[0]en_ck … in MHal_PNL_Init_MOD()
3250 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, BIT(15), BIT(15)); in msModCurrentCalibration()
3254 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0x0000, 0x00FF); in msModCurrentCalibration()
3257 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0x0500, 0x0F00); in msModCurrentCalibration()
3260 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_70_L, pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET, BIT(2)|BIT(… in msModCurrentCalibration()
3263 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_70_L, BIT(7), BIT(7)); // Enable calibration function in msModCurrentCalibration()
3273 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_73_L, BIT(15), BIT(15)); in msModCurrentCalibration()
3279 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_73_L, 0x00, BIT(15)); in msModCurrentCalibration()
3298 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0x00, BIT(15)); in msModCurrentCalibration()
3842 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, BIT(15), BIT(15)); //[15]sw_rst in MHal_PNL_SetOSDCOutputType()
3844 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0x4000, 0xF000); //bank selection for skew clock in MHal_PNL_SetOSDCOutputType()
3866 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, BIT(14),BIT(14)|BIT(15)); //[15]enskew_path2[14]enclk_path2[4… in MHal_PNL_SetOSDCOutputType()
3871 … MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x001F, 0x001F); //[4]ck_pd[3]ck_pc[2]ck_pb[1]ck_pa[0]en_ck in MHal_PNL_SetOSDCOutputType()
3910 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, BIT(14) ,BIT(14)|BIT(15)); in MHal_PNL_SetOSDCOutputType()
3913 … MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x001B, 0x001F); //[4]ck_pd[3]ck_pc[2]ck_pb[1]ck_pa[0]en_ck in MHal_PNL_SetOSDCOutputType()
4070 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(0)); in MHal_PNL_ChannelFIFOPointerADjust()
4071 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(0), BIT(0)); in MHal_PNL_ChannelFIFOPointerADjust()
4077 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_79_L, 0, BIT(14)); in MHal_PNL_ChannelFIFOPointerADjust()
4078 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_79_L, BIT(14), BIT(14)); in MHal_PNL_ChannelFIFOPointerADjust()
4081 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0 , BIT(1)); in MHal_PNL_ChannelFIFOPointerADjust()
4082 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(1), BIT(1)); in MHal_PNL_ChannelFIFOPointerADjust()
4084 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(2)|BIT(3)); in MHal_PNL_ChannelFIFOPointerADjust()
4090 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(2)|BIT(3), BIT(2)|BIT(3)); in MHal_PNL_ChannelFIFOPointerADjust()
4099 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(0)); in MHal_PNL_ChannelFIFOPointerADjust()
4100 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(0), BIT(0)); in MHal_PNL_ChannelFIFOPointerADjust()
4106 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_79_L, 0, BIT(14)); in MHal_PNL_ChannelFIFOPointerADjust()
4107 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_79_L, BIT(14), BIT(14)); in MHal_PNL_ChannelFIFOPointerADjust()
4110 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0 , BIT(1)); in MHal_PNL_ChannelFIFOPointerADjust()
4111 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(1), BIT(1)); in MHal_PNL_ChannelFIFOPointerADjust()
4113 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(2)|BIT(3)); in MHal_PNL_ChannelFIFOPointerADjust()
4118 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(2)|BIT(3), BIT(2)|BIT(3)); in MHal_PNL_ChannelFIFOPointerADjust()