Lines Matching refs:MOD_A_W2BYTEMSK
196 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, 0x00, BIT(8)); in MHal_MOD_PowerOn()
205 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, BIT(0) , BIT(0)); in MHal_MOD_PowerOn()
209 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0x00 , BIT(0)); in MHal_MOD_PowerOn()
211 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, BIT(8) , BIT(8)); in MHal_MOD_PowerOn()
219 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, (BIT(1) | BIT(0)), (BIT(1) | BIT(0))); in MHal_MOD_PowerOn()
272 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, BIT(8), BIT(8)); in MHal_MOD_PowerOn()
275 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, BIT(0), BIT(0)); //analog MOD po… in MHal_MOD_PowerOn()
276 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0x00, BIT(8)); in MHal_MOD_PowerOn()
279 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0, (BIT(1) | BIT(0) )); //enable ib… in MHal_MOD_PowerOn()
287 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0020,0x0020); in MHal_MOD_PowerOn()
291 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0000,0x0020); in MHal_MOD_PowerOn()
330 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x5550, 0xFFF0); in MHal_Output_LVDS_Pair_Setting()
335 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x5550, 0xFFF0); in MHal_Output_LVDS_Pair_Setting()
345 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x5550, 0xFFF0); in MHal_Output_LVDS_Pair_Setting()
505 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x1F, 0x1F); //open all clk
598 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, u8Clk, 0x1F);
608 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x0F, 0x1F);
612 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x0F, 0x1F);
617 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x1F, 0x1F);
622 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x03, 0x1F);
627 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x03, 0x1F);
631 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x1F, 0x1F);
1810 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, 0, BIT(15)); in MHal_PNL_PreSetModeOn()
1814 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, BIT(15), BIT(15)); in MHal_PNL_PreSetModeOn()
2124 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0, BIT(15)); in MHal_PNL_MOD_Control_Out_Swing()
2211 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_18_L, in MHal_PNL_MOD_PECurrent_Setting()
2221 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_19_L, in MHal_PNL_MOD_PECurrent_Setting()
2231 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_1A_L, in MHal_PNL_MOD_PECurrent_Setting()
2241 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_1B_L, in MHal_PNL_MOD_PECurrent_Setting()
2260 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_34_L, 0xFFFF, 0xFFFF); //Enable TTL low-power mode in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2263 … MOD_A_W2BYTEMSK(REG_MOD_A_BK00_32_L, 0xFFFF, 0xFFFF); //GCR_EN_RINT (internal termination open) in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2266 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3C_L, 0xFFFF, 0xFFFF); //Disable DRIVER BIAS OP in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2271 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_34_L, 0x0000, 0xFFFF); //Disable TTL low-power mode in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2274 … MOD_A_W2BYTEMSK(REG_MOD_A_BK00_32_L, 0x0000, 0xFFFF); //GCR_EN_RINT (internal termination close) in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2277 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3C_L, 0x0000, 0xFFFF); //Enable DRIVER BIAS OP in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2342 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0, BIT(15)); in msSetVBY1RconValue()
2383 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0020,0x0020); in MHal_PNL_SetOutputType()
2387 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0000,0x0020); in MHal_PNL_SetOutputType()
2398 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, 0x3FF, 0x3FF); // TTL skew in MHal_PNL_SetOutputType()
2453 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0020,0x0020); in MHal_PNL_SetOutputType()
2457 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0000,0x0020); in MHal_PNL_SetOutputType()
2550 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0xC01F , 0xFFFF); // enable clk_dot_mini_pre_osd & clk_dot_mi… in MHal_PNL_SetOutputType()
2552 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, BIT(15), BIT(15)); //[15]sw_rst in MHal_PNL_SetOutputType()
2553 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0xC000 , 0xF000); // enable clk_dot_mini_pre_osd & clk_dot_mi… in MHal_PNL_SetOutputType()
2562 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0020,0x0020); in MHal_PNL_SetOutputType()
2566 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0000,0x0020); in MHal_PNL_SetOutputType()
2577 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_40_L, 0x0FFF, 0x0FFF); in MHal_PNL_SetOutputType()
2579 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_48_L, 0x0FFF, 0x0FFF); in MHal_PNL_SetOutputType()
2581 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_44_L, 0x0000, 0x0FFF); in MHal_PNL_SetOutputType()
2583 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_42_L, 0x0000, 0x0FFF); in MHal_PNL_SetOutputType()
2586 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_40_L, 0xF000, 0xF000); in MHal_PNL_SetOutputType()
2589 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_48_L, 0xF000, 0xF000); in MHal_PNL_SetOutputType()
2592 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_44_L, 0x0000, 0xF000); in MHal_PNL_SetOutputType()
2595 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_42_L, 0x0000, 0xF000); in MHal_PNL_SetOutputType()
2610 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0, 0xF000); in MHal_PNL_SetOutputType()
2621 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_48_L, 0x0000, 0xF000); in MHal_PNL_SetOutputType()
2626 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0x00, BIT(0)); in MHal_PNL_SetOutputType()
2656 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_40_L, 0x0000, 0xF000); in MHal_PNL_SetOutputType()
2660 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, 0x000, 0x3FF); // TTL skew in MHal_PNL_SetOutputType()
2961 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_30_L, 0xFFFF, 0xFFFF); //reg_gcr_pe_en_ch in MHal_PNL_Init_MOD()
2962 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_32_L, 0x0000, 0xFFFF); //reg_gcr_en_rint_ch in MHal_PNL_Init_MOD()
2963 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3C_L, 0xFFFF, 0xFFFF); //reg_gcr_test_ch in MHal_PNL_Init_MOD()
3015 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0xC000, 0xF000); //bank selection for skew clock in MHal_PNL_Init_MOD()
3028 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_31_L, 0x0FFF, 0x3FFF); in MHal_PNL_Init_MOD()
3145 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, u16ChannelClk_En, 0x1F); //[4]ck_pd[3]ck_pc[2]ck_pb[1]ck_pa[0… in MHal_PNL_Init_MOD()
3150 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x1F, 0x1F); //[4]ck_pd[3]ck_pc[2]ck_pb[1]ck_pa[0]en_ck … in MHal_PNL_Init_MOD()
3298 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, BIT(15), BIT(15)); in msModCurrentCalibration()
3302 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0x0000, 0x00FF); in msModCurrentCalibration()
3305 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0x0500, 0x0F00); in msModCurrentCalibration()
3308 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_70_L, pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET, BIT(2)|BIT(… in msModCurrentCalibration()
3311 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_70_L, BIT(7), BIT(7)); // Enable calibration function in msModCurrentCalibration()
3321 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_73_L, BIT(15), BIT(15)); in msModCurrentCalibration()
3327 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_73_L, 0x00, BIT(15)); in msModCurrentCalibration()
3346 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0x00, BIT(15)); in msModCurrentCalibration()
3888 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, BIT(15), BIT(15)); //[15]sw_rst in MHal_PNL_SetOSDCOutputType()
3890 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0x4000, 0xF000); //bank selection for skew clock in MHal_PNL_SetOSDCOutputType()
3912 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, BIT(14),BIT(14)|BIT(15)); //[15]enskew_path2[14]enclk_path2[4… in MHal_PNL_SetOSDCOutputType()
3917 … MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x001F, 0x001F); //[4]ck_pd[3]ck_pc[2]ck_pb[1]ck_pa[0]en_ck in MHal_PNL_SetOSDCOutputType()
3956 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, BIT(14) ,BIT(14)|BIT(15)); in MHal_PNL_SetOSDCOutputType()
3959 … MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x001B, 0x001F); //[4]ck_pd[3]ck_pc[2]ck_pb[1]ck_pa[0]en_ck in MHal_PNL_SetOSDCOutputType()
4121 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(0)); in MHal_PNL_ChannelFIFOPointerADjust()
4122 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(0), BIT(0)); in MHal_PNL_ChannelFIFOPointerADjust()
4128 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_79_L, 0, BIT(14)); in MHal_PNL_ChannelFIFOPointerADjust()
4129 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_79_L, BIT(14), BIT(14)); in MHal_PNL_ChannelFIFOPointerADjust()
4132 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0 , BIT(1)); in MHal_PNL_ChannelFIFOPointerADjust()
4133 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(1), BIT(1)); in MHal_PNL_ChannelFIFOPointerADjust()
4135 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(2)|BIT(3)); in MHal_PNL_ChannelFIFOPointerADjust()
4141 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(2)|BIT(3), BIT(2)|BIT(3)); in MHal_PNL_ChannelFIFOPointerADjust()
4150 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(0)); in MHal_PNL_ChannelFIFOPointerADjust()
4151 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(0), BIT(0)); in MHal_PNL_ChannelFIFOPointerADjust()
4157 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_79_L, 0, BIT(14)); in MHal_PNL_ChannelFIFOPointerADjust()
4158 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_79_L, BIT(14), BIT(14)); in MHal_PNL_ChannelFIFOPointerADjust()
4161 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0 , BIT(1)); in MHal_PNL_ChannelFIFOPointerADjust()
4162 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(1), BIT(1)); in MHal_PNL_ChannelFIFOPointerADjust()
4164 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(2)|BIT(3)); in MHal_PNL_ChannelFIFOPointerADjust()
4169 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(2)|BIT(3), BIT(2)|BIT(3)); in MHal_PNL_ChannelFIFOPointerADjust()