Lines Matching refs:MOD_W2BYTEMSK
261 …MOD_W2BYTEMSK(REG_MOD_BK00_42_L, (BIT(7) | BIT(6)), (BIT(7) | BIT(6))); // shift_lvds_pair, set LV… in MHal_Shift_LVDS_Pair()
263 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0x0000, (BIT(7) | BIT(6))); in MHal_Shift_LVDS_Pair()
1401 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(15), BIT(15)); in MHal_PNL_HWLVDSReservedtoLRFlag()
1405 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(14), BIT(14)); in MHal_PNL_HWLVDSReservedtoLRFlag()
1412 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(13), BIT(13)); in MHal_PNL_HWLVDSReservedtoLRFlag()
1416 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(12), BIT(12)); in MHal_PNL_HWLVDSReservedtoLRFlag()
1423 MOD_W2BYTEMSK(REG_MOD_BK00_30_L, BIT(14), BIT(14)); in MHal_PNL_HWLVDSReservedtoLRFlag()
1428 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, 0x0000, (BIT(15) | BIT(14) | BIT(13) | BIT(12))); in MHal_PNL_HWLVDSReservedtoLRFlag()
1433 MOD_W2BYTEMSK(REG_MOD_BK00_30_L, 0x00, BIT(14)); in MHal_PNL_HWLVDSReservedtoLRFlag()
1783 MOD_W2BYTEMSK(REG_MOD_BK00_76_L, 0x003F, 0x003F); in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
1786 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x003F, 0x003F); in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
1794 MOD_W2BYTEMSK(REG_MOD_BK00_76_L, 0x0000, 0x003F); in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
1797 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x0000, 0x003F); in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
1903 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0x0000, (BIT(7) | BIT(6))); // shift_lvds_pair in MHal_PNL_SetOutputType()
1910 MOD_W2BYTEMSK(REG_MOD_BK00_7E_L, 0x0000, 0xE000); in MHal_PNL_SetOutputType()
1915 MOD_W2BYTEMSK(REG_MOD_BK00_4A_L, BIT(8), BIT(8)); // GPO gating in MHal_PNL_SetOutputType()
1921 MOD_W2BYTEMSK(REG_MOD_BK00_34_L, 0xF000, 0xF000); //[15:14]datax[13:12]data_format3,2 in MHal_PNL_SetOutputType()
2025 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(3), 0xFFFF ); // enable osd lvds path in MHal_PNL_SetOutputType()
2075 MOD_W2BYTEMSK(REG_MOD_BK00_7C_L, 0x3F3F, 0x3F3F); in MHal_PNL_SetOutputType()
2077 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x0000, 0x3F00); in MHal_PNL_SetOutputType()
2079 MOD_W2BYTEMSK(REG_MOD_BK00_7F_L, 0x0000, 0xFC00); in MHal_PNL_SetOutputType()
2128 MOD_W2BYTEMSK(REG_MOD_BK00_7E_L, 0x0000, 0x000F); in MHal_PNL_SetOutputType()
2133 MOD_W2BYTEMSK(REG_MOD_BK00_4A_L, 0x0, BIT(8)); // GPO gating in MHal_PNL_SetOutputType()
2151 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(7), BIT(7)); // shift LVDS pair in MHal_PNL_MISC_Control()
2220 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, pstPanelInitData->u16MOD_CTRL0, LBMASK); in MHal_PNL_Init_MOD()
2230 …MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0xAC40, 0xFDCF); //[15]proc_st[13:12]byte_mode 4 byte mode[6]4ch_… in MHal_PNL_Init_MOD()
2232 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, (pstPanelInitData->u16MOD_CTRL9 & BIT(6))<<3, BIT(9)); in MHal_PNL_Init_MOD()
2233 …MOD_W2BYTEMSK(REG_MOD_BK00_62_L, (pstPanelInitData->u16MOD_CTRL9 & (BIT(12)|BIT(11)))>>7, BIT(5)|B… in MHal_PNL_Init_MOD()
2241 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0002, 0x0007);//[2:0]reg_mft_mode in MHal_PNL_Init_MOD()
2243 MOD_W2BYTEMSK(REG_MOD_BK00_21_L, 0x1002, 0xFFFF); //[11:0]reg_dly_value in MHal_PNL_Init_MOD()
2244 MOD_W2BYTEMSK(REG_MOD_BK00_22_L, 0x0F00, 0xFFFF); //[12:0]reg_hsize in MHal_PNL_Init_MOD()
2245 MOD_W2BYTEMSK(REG_MOD_BK00_26_L, 0x0780, 0xFFFF); //[12:0]reg_div_len in MHal_PNL_Init_MOD()
2246 MOD_W2BYTEMSK(REG_MOD_BK00_7F_L, 0x0002, 0xFFFF); //[2:0]reg_sram_usage in MHal_PNL_Init_MOD()
2247 MOD_W2BYTEMSK(REG_MOD_BK00_53_L, 0x4000, 0xFFFF); //[14]reg_vfde_mask in MHal_PNL_Init_MOD()
2251 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0000, 0x0007);//[2:0]reg_mft_mode in MHal_PNL_Init_MOD()
2257 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0000, 0x0007); in MHal_PNL_Init_MOD()
2258 MOD_W2BYTEMSK(REG_MOD_BK00_53_L, 0x0000, 0xFFFF); //[14]reg_vfde_mask in MHal_PNL_Init_MOD()
2262 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x00, BIT(6)); //[6]4ch_vby1 in MHal_PNL_Init_MOD()
2264 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, BIT(6), BIT(6)); //[6]4ch_vby1 in MHal_PNL_Init_MOD()
2269 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, (pstPanelInitData->u16MOD_CTRL9 & BIT(7))<<6, BIT(13)); in MHal_PNL_Init_MOD()
2270 …MOD_W2BYTEMSK(REG_MOD_BK00_63_L, (pstPanelInitData->u16MOD_CTRL9 & (BIT(14)|BIT(13)))>>3, BIT(11)|… in MHal_PNL_Init_MOD()
2274 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, BIT(12), BIT(12)); // [12] enable 8ch vx1 mode : 1 in MHal_PNL_Init_MOD()
2279 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, BIT(11), BIT(11)); // [11:10]reg_vby1_pair_mirror2 in MHal_PNL_Init_MOD()
2284 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, 0x00, BIT(11)); // [11:10]reg_vby1_pair_mirror2 in MHal_PNL_Init_MOD()
2289 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, 0x00, BIT(12)); // [12] enable 8ch vx1 mode : 0 in MHal_PNL_Init_MOD()
2320 …MOD_W2BYTEMSK(REG_MOD_BK00_67_L, BIT(0)|BIT(3), BIT(0)|BIT(3)); // [0] reg_vby1_8v4o_mode, [3]reg… in MHal_PNL_Init_MOD()
2321 MOD_W2BYTEMSK(REG_MOD_BK00_67_L, BIT(15), BIT(15)); in MHal_PNL_Init_MOD()
2330 MOD_W2BYTEMSK(REG_MOD_BK00_5C_L,0x8142,0xFFFF); in MHal_PNL_Init_MOD()
2331 MOD_W2BYTEMSK(REG_MOD_BK00_5E_L,0x8142,0xFFFF); in MHal_PNL_Init_MOD()
2366 MOD_W2BYTEMSK(REG_MOD_A_BK00_70_L, 0x7, 0x07); in MHal_PNL_Init_MOD()
2382 MOD_W2BYTEMSK(REG_MOD_BK00_53_L, BIT(0), BIT(0)); in MHal_PNL_Init_MOD()
2429 MOD_W2BYTEMSK(u32Addr, (u16Value << 8), (u16Mask << 8)); in MHal_PNL_DumpMODReg()
2433 MOD_W2BYTEMSK(u32Addr, u16Value, u16Mask); in MHal_PNL_DumpMODReg()
2571 …MOD_W2BYTEMSK(REG_MOD_A_BK00_70_L, pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET, BIT(2)|BIT(1)… in msModCurrentCalibration()
2574 MOD_W2BYTEMSK(REG_MOD_A_BK00_70_L, BIT(7), BIT(7)); // Enable calibration function in msModCurrentCalibration()
2584 MOD_W2BYTEMSK(REG_MOD_BK00_3D_L, BIT(15), BIT(15)); in msModCurrentCalibration()
2590 MOD_W2BYTEMSK(REG_MOD_BK00_3D_L, 0x00, BIT(15)); in msModCurrentCalibration()
2632 MOD_W2BYTEMSK(REG_MOD_A_BK00_70_L, 0x00, BIT(7)); // Disable calibration function in msModCurrentCalibration()
2665 MOD_W2BYTEMSK(REG_MOD_A_BK00_70_L, u8Cab, 0x07); in MHal_PNL_MOD_Calibration()
2801 MOD_W2BYTEMSK(REG_MOD_BK00_02_L, u16Red , 0x03FF); in MHal_PNL_SetOutputPattern()
2802 MOD_W2BYTEMSK(REG_MOD_BK00_03_L, u16Green , 0x03FF); in MHal_PNL_SetOutputPattern()
2803 MOD_W2BYTEMSK(REG_MOD_BK00_04_L, u16Blue , 0x03FF); in MHal_PNL_SetOutputPattern()
2805 MOD_W2BYTEMSK(REG_MOD_BK00_01_L, BIT(15) , BIT(15)); in MHal_PNL_SetOutputPattern()
2809 MOD_W2BYTEMSK(REG_MOD_BK00_01_L, DISABLE , BIT(15)); in MHal_PNL_SetOutputPattern()
2863 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x00, BIT(11)); in MHal_PNL_VBY1_Handshake()
2864 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, BIT(11), BIT(11)); in MHal_PNL_VBY1_Handshake()
2867 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_Handshake()
2868 … MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_Handshake()
2869 …MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_Handshake()
2870 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_Handshake()
2951 MOD_W2BYTEMSK(REG_MOD_BK00_66_L, 0x00, BIT(11)); in MHal_PNL_VBY1_OC_Handshake()
2952 MOD_W2BYTEMSK(REG_MOD_BK00_66_L, BIT(11), BIT(11)); in MHal_PNL_VBY1_OC_Handshake()
2956 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_OC_Handshake()
2957 … MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_OC_Handshake()
2958 …MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_OC_Handshake()
2959 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_OC_Handshake()
3019 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, BIT(4) | BIT(7), BIT(4) | BIT(7)); in MHal_PNL_SetOutputInterlaceTiming()
3021 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(10)|BIT(11), BIT(10)|BIT(11)); in MHal_PNL_SetOutputInterlaceTiming()
3026 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, 0, BIT(4) | BIT(7)); in MHal_PNL_SetOutputInterlaceTiming()
3027 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0, BIT(10)|BIT(11)); in MHal_PNL_SetOutputInterlaceTiming()
3202 MOD_W2BYTEMSK(REG_MOD_BK00_6A_L, 0, BIT(1)); in MHal_PNL_SetOSDCOutputType()
3206 MOD_W2BYTEMSK(REG_MOD_BK00_6A_L, BIT(1), BIT(1)); in MHal_PNL_SetOSDCOutputType()
3211 MOD_W2BYTEMSK(REG_MOD_BK00_6A_L, 0, BIT(1)); in MHal_PNL_SetOSDCOutputType()