Lines Matching refs:MOD_W2BYTEMSK
301 …MOD_W2BYTEMSK(REG_MOD_BK00_42_L, (BIT(7) | BIT(6)), (BIT(7) | BIT(6))); // shift_lvds_pair, set LV… in MHal_Shift_LVDS_Pair()
303 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0x0000, (BIT(7) | BIT(6))); in MHal_Shift_LVDS_Pair()
1629 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(15), BIT(15)); in MHal_PNL_HWLVDSReservedtoLRFlag()
1633 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(14), BIT(14)); in MHal_PNL_HWLVDSReservedtoLRFlag()
1640 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(13), BIT(13)); in MHal_PNL_HWLVDSReservedtoLRFlag()
1644 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(12), BIT(12)); in MHal_PNL_HWLVDSReservedtoLRFlag()
1651 MOD_W2BYTEMSK(REG_MOD_BK00_30_L, BIT(14), BIT(14)); in MHal_PNL_HWLVDSReservedtoLRFlag()
1656 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, 0x0000, (BIT(15) | BIT(14) | BIT(13) | BIT(12))); in MHal_PNL_HWLVDSReservedtoLRFlag()
1661 MOD_W2BYTEMSK(REG_MOD_BK00_30_L, 0x00, BIT(14)); in MHal_PNL_HWLVDSReservedtoLRFlag()
2011 MOD_W2BYTEMSK(REG_MOD_BK00_76_L, 0x003F, 0x003F); in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2014 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x003F, 0x003F); in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2022 MOD_W2BYTEMSK(REG_MOD_BK00_76_L, 0x0000, 0x003F); in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2025 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x0000, 0x003F); in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2135 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0x0000, (BIT(7) | BIT(6))); // shift_lvds_pair in MHal_PNL_SetOutputType()
2142 MOD_W2BYTEMSK(REG_MOD_BK00_7E_L, 0x0000, 0xE000); in MHal_PNL_SetOutputType()
2147 MOD_W2BYTEMSK(REG_MOD_BK00_4A_L, BIT(8), BIT(8)); // GPO gating in MHal_PNL_SetOutputType()
2153 MOD_W2BYTEMSK(REG_MOD_BK00_34_L, 0xF000, 0xF000); //[15:14]datax[13:12]data_format3,2 in MHal_PNL_SetOutputType()
2296 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(3), 0xFFFF ); // enable osd lvds path in MHal_PNL_SetOutputType()
2347 MOD_W2BYTEMSK(REG_MOD_BK00_7C_L, 0x3F3F, 0x3F3F); in MHal_PNL_SetOutputType()
2349 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x0000, 0x3F00); in MHal_PNL_SetOutputType()
2351 MOD_W2BYTEMSK(REG_MOD_BK00_7F_L, 0x0000, 0xFC00); in MHal_PNL_SetOutputType()
2404 MOD_W2BYTEMSK(REG_MOD_BK00_7E_L, 0x0000, 0x000F); in MHal_PNL_SetOutputType()
2409 MOD_W2BYTEMSK(REG_MOD_BK00_4A_L, 0x0, BIT(8)); // GPO gating in MHal_PNL_SetOutputType()
2427 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(7), BIT(7)); // shift LVDS pair in MHal_PNL_MISC_Control()
2547 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, pstPanelInitData->u16MOD_CTRL0, LBMASK); in MHal_PNL_Init_MOD()
2557 …MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0xA000, 0xFD8F); //[15]proc_st[13:12]byte_mode 4 byte mode[6]4ch_… in MHal_PNL_Init_MOD()
2561 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x00, BIT(6)); //[6]4ch_vby1 in MHal_PNL_Init_MOD()
2563 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, BIT(6), BIT(6)); //[6]4ch_vby1 in MHal_PNL_Init_MOD()
2565 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, (pstPanelInitData->u16MOD_CTRL9 & BIT(6))<<3, BIT(9)); in MHal_PNL_Init_MOD()
2566 …MOD_W2BYTEMSK(REG_MOD_BK00_62_L, (pstPanelInitData->u16MOD_CTRL9 & (BIT(12)|BIT(11)))>>7, BIT(5)|B… in MHal_PNL_Init_MOD()
2574 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0002, 0x0007);//[2:0]reg_mft_mode in MHal_PNL_Init_MOD()
2576 MOD_W2BYTEMSK(REG_MOD_BK00_21_L, 0x1002, 0xFFFF); //[11:0]reg_dly_value in MHal_PNL_Init_MOD()
2577 MOD_W2BYTEMSK(REG_MOD_BK00_22_L, 0x0F00, 0xFFFF); //[12:0]reg_hsize in MHal_PNL_Init_MOD()
2578 MOD_W2BYTEMSK(REG_MOD_BK00_26_L, 0x0780, 0xFFFF); //[12:0]reg_div_len in MHal_PNL_Init_MOD()
2579 MOD_W2BYTEMSK(REG_MOD_BK00_7F_L, 0x0002, 0xFFFF); //[2:0]reg_sram_usage in MHal_PNL_Init_MOD()
2580 MOD_W2BYTEMSK(REG_MOD_BK00_53_L, 0x4000, 0xFFFF); //[14]reg_vfde_mask in MHal_PNL_Init_MOD()
2584 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0000, 0x0007);//[2:0]reg_mft_mode in MHal_PNL_Init_MOD()
2593 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0001, 0x0007); in MHal_PNL_Init_MOD()
2597 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0000, 0x0007); in MHal_PNL_Init_MOD()
2600 MOD_W2BYTEMSK(REG_MOD_BK00_53_L, 0x0000, 0xFFFF); //[14]reg_vfde_mask in MHal_PNL_Init_MOD()
2608 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, (pstPanelInitData->u16MOD_CTRL9 & BIT(7))<<6, BIT(13)); in MHal_PNL_Init_MOD()
2609 …MOD_W2BYTEMSK(REG_MOD_BK00_63_L, (pstPanelInitData->u16MOD_CTRL9 & (BIT(14)|BIT(13)))>>3, BIT(11)|… in MHal_PNL_Init_MOD()
2613 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, BIT(12), BIT(12)); // [12] enable 8ch vx1 mode : 1 in MHal_PNL_Init_MOD()
2618 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, BIT(11), BIT(11)); // [11:10]reg_vby1_pair_mirror2 in MHal_PNL_Init_MOD()
2623 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, 0x00, BIT(11)); // [11:10]reg_vby1_pair_mirror2 in MHal_PNL_Init_MOD()
2628 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, 0x0000, BIT(12)); // [12] enable 8ch vx1 mode : 0 in MHal_PNL_Init_MOD()
2666 MOD_W2BYTEMSK(REG_MOD_BK00_67_L, BIT(3), BIT(0)|BIT(3)); in MHal_PNL_Init_MOD()
2667 MOD_W2BYTEMSK(REG_MOD_BK00_67_L, (BIT(5)|BIT(6)|BIT(7)), (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ); in MHal_PNL_Init_MOD()
2668 MOD_W2BYTEMSK(REG_MOD_BK00_67_L, 0x0000, BIT(8) ); in MHal_PNL_Init_MOD()
2669 MOD_W2BYTEMSK(REG_MOD_BK00_67_L, BIT(15), BIT(15)); in MHal_PNL_Init_MOD()
2678 MOD_W2BYTEMSK(REG_MOD_BK00_5C_L,0x8142,0xFFFF); in MHal_PNL_Init_MOD()
2679 MOD_W2BYTEMSK(REG_MOD_BK00_5E_L,0x8142,0xFFFF); in MHal_PNL_Init_MOD()
2690 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0001, 0x0007);//[2:0]reg_mft_mode, 2p to 1p mode in MHal_PNL_Init_MOD()
2694 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0000, 0x0007);//[2:0]reg_mft_mode in MHal_PNL_Init_MOD()
2744 MOD_W2BYTEMSK(REG_MOD_BK00_53_L, BIT(0), BIT(0)); in MHal_PNL_Init_MOD()
2791 MOD_W2BYTEMSK(u32Addr, (u16Value << 8), (u16Mask << 8)); in MHal_PNL_DumpMODReg()
2795 MOD_W2BYTEMSK(u32Addr, u16Value, u16Mask); in MHal_PNL_DumpMODReg()
2946 MOD_W2BYTEMSK(REG_MOD_BK00_3D_L, BIT(15), BIT(15)); in msModCurrentCalibration()
2952 MOD_W2BYTEMSK(REG_MOD_BK00_3D_L, 0x00, BIT(15)); in msModCurrentCalibration()
3199 MOD_W2BYTEMSK(REG_MOD_BK00_02_L, u16Red , 0x03FF); in MHal_PNL_SetOutputPattern()
3200 MOD_W2BYTEMSK(REG_MOD_BK00_03_L, u16Green , 0x03FF); in MHal_PNL_SetOutputPattern()
3201 MOD_W2BYTEMSK(REG_MOD_BK00_04_L, u16Blue , 0x03FF); in MHal_PNL_SetOutputPattern()
3203 MOD_W2BYTEMSK(REG_MOD_BK00_01_L, BIT(15) , BIT(15)); in MHal_PNL_SetOutputPattern()
3207 MOD_W2BYTEMSK(REG_MOD_BK00_01_L, DISABLE , BIT(15)); in MHal_PNL_SetOutputPattern()
3261 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x00, BIT(11)); in MHal_PNL_VBY1_Handshake()
3262 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, BIT(11), BIT(11)); in MHal_PNL_VBY1_Handshake()
3265 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_Handshake()
3266 … MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_Handshake()
3267 …MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_Handshake()
3268 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_Handshake()
3349 MOD_W2BYTEMSK(REG_MOD_BK00_66_L, 0x00, BIT(11)); in MHal_PNL_VBY1_OC_Handshake()
3350 MOD_W2BYTEMSK(REG_MOD_BK00_66_L, BIT(11), BIT(11)); in MHal_PNL_VBY1_OC_Handshake()
3354 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_OC_Handshake()
3355 … MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_OC_Handshake()
3356 …MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_OC_Handshake()
3357 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_OC_Handshake()
3417 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, BIT(4) | BIT(7), BIT(4) | BIT(7)); in MHal_PNL_SetOutputInterlaceTiming()
3419 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(10)|BIT(11), BIT(10)|BIT(11)); in MHal_PNL_SetOutputInterlaceTiming()
3424 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, 0, BIT(4) | BIT(7)); in MHal_PNL_SetOutputInterlaceTiming()
3425 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0, BIT(10)|BIT(11)); in MHal_PNL_SetOutputInterlaceTiming()
3600 MOD_W2BYTEMSK(REG_MOD_BK00_6A_L, 0, BIT(1)); in MHal_PNL_SetOSDCOutputType()
3604 MOD_W2BYTEMSK(REG_MOD_BK00_6A_L, BIT(1), BIT(1)); in MHal_PNL_SetOSDCOutputType()
3609 MOD_W2BYTEMSK(REG_MOD_BK00_6A_L, 0, BIT(1)); in MHal_PNL_SetOSDCOutputType()