72 #define REG32_R(Addr)    _REG32_R((MS_VIRT)Addr)  macro
193     return REG32_R(u32Reg) & 0x0000FFFFUL;  in _REG16_R()
198     MS_U32 u32Value = (REG32_R(u32Reg) & 0xFFFF0000UL) | (u16Value & 0x0000FFFFUL);  in _REG16_W()
651     MS_U32 u32DMACtrl = REG32_R(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]);  in HAL_CIPHER_ResetException()
678     MS_U32 DMA_CTRL = REG32_R(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]);  in HAL_CIPHER_SWReset()
1103     tmp = REG32_R(&_AESDMACtrl->Dma_Out[0]);  in HAL_CIPHER_DMA_GetData()
1109     tmp = REG32_R(&_AESDMACtrl->Dma_Out[1]);  in HAL_CIPHER_DMA_GetData()
1115     tmp = REG32_R(&_AESDMACtrl->Dma_Out[2]);  in HAL_CIPHER_DMA_GetData()
1121     tmp = REG32_R(&_AESDMACtrl->Dma_Out[3]);  in HAL_CIPHER_DMA_GetData()
1135         DmaRpt[i] = REG32_R(&_AESDMACtrl->Dma_Reportp[i]);  in HAL_CIPHER_DMA_GetRpt()
1170         MS_U32 u32DMACtrl = REG32_R(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]);  in HAL_CIPHER_DMA_Start()
1178     MS_U32 MIUCrossBar = REG32_R(_u32RegBase + REG_MIU_CROSSBAR);  //MIU CrossBar Bank 0x1613  in HAL_CIPHER_DMA_Start()
1204     u32SpareCnt = REG32_R(&_AESDMACtrl->SpareCnt) ;  in HAL_CIPHER_DMA_Start()
1342     MS_U32 MIUCrossBar = REG32_R(_u32RegBase + REG_MIU_CROSSBAR);  //MIU CrossBar Bank 0x1613  in HAL_CIPHER_OTPHash_Start()
1347     u32SpareCnt = REG32_R(&_AESDMACtrl->SpareCnt) ;  in HAL_CIPHER_OTPHash_Start()
1400     MS_U32 u32Rpt   = REG32_R(&_AESDMACtrl->Dma_Reportp[0]) ;  in HAL_CIPHER_DMA_CmdDone()
1405         u32ExcTmp = (MS_U32) REG32_R(&_AESDMACtrl->Dma_Ctrl[REG_EXCEPT_FLAG]);  in HAL_CIPHER_DMA_CmdDone()
1421     MS_U32 u32ExcTmp = (MS_U32) REG32_R(&_AESDMACtrl->Dma_Ctrl[REG_EXCEPT_FLAG]);  in HAL_CIPHER_GetException()
1605         HashRpt[i] = REG32_R(&_AESDMACtrl->Hash_Reportp[i]);  in HAL_CIPHER_Hash_GetRpt()
1986         MS_U32 MIUCrossBar = REG32_R(_u32RegBase + REG_MIU_CROSSBAR);  //MIU CrossBar Bank 0x1613  in HAL_CIPHER_Hash_Start()
1991         u32SpareCnt = REG32_R(&_AESDMACtrl->SpareCnt) ;  in HAL_CIPHER_Hash_Start()
2097     MS_U32 u32Tmp = REG32_R(&_AESDMACtrl->Hash_Reportp[0]) ;  in HAL_CIPHER_Hash_CmdDone()
2102     	u32ExcTmp = (MS_U32)REG32_R(&_AESDMACtrl->Dma_Ctrl[REG_EXCEPT_FLAG]);  in HAL_CIPHER_Hash_CmdDone()
2487                 MS_U32 u32Tmp=REG32_R(_u32RegBase+REG_RNG_TRNG_SCPU);  in HAL_CIPHER_Misc_Random()
2491             while( !(REG32_R(_u32RegBase+REG_RNG_TRNG_SCPU) & REG_RNG_TRNG_VALID_SCPU_MASK) );  in HAL_CIPHER_Misc_Random()
2493 …while( (u16TRN = (REG32_R(_u32RegBase+REG_RNG_TRNG_SCPU) & REG_RNG_TRNG_OUT_SCPU_MASK))==u16PreTRN…  in HAL_CIPHER_Misc_Random()
2516                 MS_U32 u32Tmp=REG32_R(_u32RegBase+REG_RNG_TRNG_ACPU);  in HAL_CIPHER_Misc_Random()
2520             while( !(REG32_R(_u32RegBase+REG_RNG_TRNG_ACPU) & REG_RNG_TRNG_VALID_ACPU_MASK) );  in HAL_CIPHER_Misc_Random()
2522 …while( (u16TRN = (REG32_R(_u32RegBase+REG_RNG_TRNG_ACPU) & REG_RNG_TRNG_OUT_ACPU_MASK))==u16PreTRN…  in HAL_CIPHER_Misc_Random()