Lines Matching refs:TSP_CLKGEN0_REG

181 #define TSP_CLKGEN0_REG(addr)       (*((volatile MS_U16*)(_virtRegBase + 0x1600UL + ((addr)<<2UL))))  macro
1374 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_C…  in HAL_TSP_SelPad_ClkInv()
1645 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0_T…  in HAL_TSP_GetTSIF_Status()
1652 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0_T…  in HAL_TSP_GetTSIF_Status()
2138     TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL;  in HAL_TSP_Stc_ctrl()
2142     TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = (u32Sync & 0xFFFF);  in HAL_TSP_Stc_ctrl()
2143     TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = (u32Sync >> 16) & 0xFFFF;  in HAL_TSP_Stc_ctrl()
2146     TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);  in HAL_TSP_Stc_ctrl()
2147     TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN;  in HAL_TSP_Stc_ctrl()
2148     TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);  in HAL_TSP_Stc_ctrl()
2152     TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL;  in HAL_TSP_Stc_ctrl()