Lines Matching refs:_RegCtrl
48 static REG_Ctrl *_RegCtrl = NULL; // TSP 0/1 variable
167 REG32_W(&_RegCtrl->Idr_Addr, (MS_VIRT)preg); in TSP32_IdrW()
168 REG32_W(&_RegCtrl->Idr_Write, value); in TSP32_IdrW()
169 REG16_W(&_RegCtrl->Idr_Ctrl, TSP_IDR_START | TSP_IDR_WRITE); in TSP32_IdrW()
180 REG32_W(&_RegCtrl->Idr_Addr, (MS_VIRT)preg); in TSP32_IdrR()
181 REG16_W(&_RegCtrl->Idr_Ctrl, TSP_IDR_START | TSP_IDR_READ); in TSP32_IdrR()
183 return REG32_R(&_RegCtrl->Idr_Read); in TSP32_IdrR()
190 …_RegCtrl = (REG_Ctrl*) (u32BankAddr + 0x2A00UL); // TSP0/1 … in HAL_TSP_SetBank()
273 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_HW_STANDBY_MODE); in HAL_TSP_HwPatch()
278 …REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_BYTE_ADDR_DMA|TSP_HW_CFG4_ALT_TS_SIZE|TSP_HW_CFG4_WST… in HAL_TSP_HwPatch()
284 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_STANDBY); in HAL_TSP_HwPatch()
323 …REG16_SET(&_RegCtrl->HW2_Config3, TSP_VQ2PINGPONG_EN | TSP_RM_PKT_DEMUX_PIPE /*| TSP_PVR1_ALIGN_EN… in HAL_TSP_HwPatch()
328 REG16_SET(&_RegCtrl->reg160C, TSP_DOUBLE_BUF_DESC); in HAL_TSP_HwPatch()
331 REG16_SET(&_RegCtrl->reg160E, TSP_RM_DMA_GLITCH); in HAL_TSP_HwPatch()
333 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE); in HAL_TSP_HwPatch()
335 REG16_SET(&_RegCtrl->PVRConfig, TSP_MATCH_PID_LD); in HAL_TSP_HwPatch()
350 REG16_SET(&_RegCtrl->reg15b8, TSP_SERIAL_EXT_SYNC_1T); in HAL_TSP_HwPatch()
351 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_SYNC_RISING_DETECT); in HAL_TSP_HwPatch()
352 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_VALID_FALLING_DETECT) in HAL_TSP_HwPatch()
355 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_DATA_CHK_2T); in HAL_TSP_HwPatch()
419 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_WB_DMA_RESET); in HAL_TSP_Reset()
420 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_SW_RST); in HAL_TSP_Reset()
424 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_SW_RST); in HAL_TSP_Reset()
425 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_WB_DMA_RESET); in HAL_TSP_Reset()
639 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN); in HAL_TSP_CPU()
643 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN); in HAL_TSP_CPU()
658 REG32_W(&_RegCtrl->Cpu_Base, 0); // 16 bytes address unit in HAL_TSP_LoadFW()
673 … REG16_W(&_RegCtrl->Dnld_Ctrl_Addr, (MS_U16)(u32DnldCtrl & TSP_DNLD_ADDR_MASK)); // oneway register in HAL_TSP_LoadFW()
674 REG16_MSK_W(&_RegCtrl->Dnld_AddrH, TSP_DMA_RADDR_MSB_MASK, (MS_U16)u32DnldCtrl1); in HAL_TSP_LoadFW()
675 REG16_W(&_RegCtrl->Dnld_Ctrl_Size, _TSP_QMEM_SIZE); in HAL_TSP_LoadFW()
676 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START| TSP_CTRL_DNLD_DONE); in HAL_TSP_LoadFW()
677 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START); in HAL_TSP_LoadFW()
681 while (!(REG16_R(&_RegCtrl->TSP_Ctrl) & TSP_CTRL_DNLD_DONE)) in HAL_TSP_LoadFW()
686 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START| TSP_CTRL_DNLD_DONE); in HAL_TSP_LoadFW()
688 REG32_W(&_RegCtrl->Qmem_Imask, _TSP_QMEM_I_MASK); in HAL_TSP_LoadFW()
689 REG32_W(&_RegCtrl->Qmem_Ibase, _TSP_QMEM_I_ADDR_HIT); in HAL_TSP_LoadFW()
690 REG32_W(&_RegCtrl->Qmem_Dmask, _TSP_QMEM_D_MASK); in HAL_TSP_LoadFW()
691 REG32_W(&_RegCtrl->Qmem_Dbase, _TSP_QMEM_D_ADDR_HIT); in HAL_TSP_LoadFW()
1842 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SEC_DMA_BURST_EN); in HAL_TSP_SecFlt_BurstLen()
1843 REG16_MSK_W(&_RegCtrl->Hw_Config4, TSP_HW_DMA_MODE_MASK, (burstMode << TSP_HW_DMA_MODE_SHIFT)); in HAL_TSP_SecFlt_BurstLen()
2232 REG16_SET(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR0_UPDATE_END); in HAL_TSP_PcrFlt_ClearInt()
2233 REG16_CLR(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR0_UPDATE_END); in HAL_TSP_PcrFlt_ClearInt()
2236 REG16_SET(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR1_UPDATE_END); in HAL_TSP_PcrFlt_ClearInt()
2237 REG16_CLR(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR1_UPDATE_END); in HAL_TSP_PcrFlt_ClearInt()
2240 REG16_SET(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR2_UPDATE_END); in HAL_TSP_PcrFlt_ClearInt()
2241 REG16_CLR(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR2_UPDATE_END); in HAL_TSP_PcrFlt_ClearInt()
2244 REG16_SET(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR3_UPDATE_END); in HAL_TSP_PcrFlt_ClearInt()
2245 REG16_CLR(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR3_UPDATE_END); in HAL_TSP_PcrFlt_ClearInt()
2248 REG16_SET(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR4_UPDATE_END); in HAL_TSP_PcrFlt_ClearInt()
2249 REG16_CLR(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR4_UPDATE_END); in HAL_TSP_PcrFlt_ClearInt()
2252 REG16_SET(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR5_UPDATE_END); in HAL_TSP_PcrFlt_ClearInt()
2253 REG16_CLR(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR5_UPDATE_END); in HAL_TSP_PcrFlt_ClearInt()
2256 REG16_SET(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR6_UPDATE_END); in HAL_TSP_PcrFlt_ClearInt()
2257 REG16_CLR(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR6_UPDATE_END); in HAL_TSP_PcrFlt_ClearInt()
2260 REG16_SET(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR7_UPDATE_END); in HAL_TSP_PcrFlt_ClearInt()
2261 REG16_CLR(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR7_UPDATE_END); in HAL_TSP_PcrFlt_ClearInt()
2519 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE); in HAL_TSP_STC64_Mode_En()
2523 REG16_CLR(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE); in HAL_TSP_STC64_Mode_En()
2532 REG32_W(&_RegCtrl->Pcr_L, stcL); in HAL_TSP_STC64_Set()
2533 REG32_W(&_RegCtrl->Pcr_H, stcH); in HAL_TSP_STC64_Set()
2536 REG32_W(&_RegCtrl->PCR64_2_L, stcL); in HAL_TSP_STC64_Set()
2537 REG32_W(&_RegCtrl->PCR64_2_H, stcH); in HAL_TSP_STC64_Set()
2561 REG16_CLR(&_RegCtrl->reg15b8, TSP_cnt_33b_ld); in HAL_TSP_STC64_Get()
2562 *pStcH = REG32_R(&_RegCtrl->Pcr_H); in HAL_TSP_STC64_Get()
2563 *pStcL = REG32_R(&_RegCtrl->Pcr_L); in HAL_TSP_STC64_Get()
2564 REG16_SET(&_RegCtrl->reg15b8, TSP_cnt_33b_ld); in HAL_TSP_STC64_Get()
2567 REG16_CLR(&_RegCtrl->reg15b8, TSP_64bit_PCR2_ld); in HAL_TSP_STC64_Get()
2568 *pStcH = REG32_R(&_RegCtrl->PCR64_2_H); in HAL_TSP_STC64_Get()
2569 *pStcL = REG32_R(&_RegCtrl->PCR64_2_L); in HAL_TSP_STC64_Get()
2570 REG16_SET(&_RegCtrl->reg15b8, TSP_64bit_PCR2_ld); in HAL_TSP_STC64_Get()
2595 REG16_W(&_RegCtrl->Pcr_H_CmdQ, stcH & TSP_REG_PCR_CMDQ_H); in HAL_TSP_STC33_CmdQSet()
2596 REG32_W(&_RegCtrl->Pcr_L_CmdQ, stcL); in HAL_TSP_STC33_CmdQSet()
2601 REG16_CLR(&_RegCtrl->reg15b8, TSP_cnt_33b_ld); in HAL_TSP_STC33_CmdQGet()
2602 *pStcH = REG16_R(&_RegCtrl->Pcr_H_CmdQ) & TSP_REG_PCR_CMDQ_H; in HAL_TSP_STC33_CmdQGet()
2603 *pStcL = REG32_R(&_RegCtrl->Pcr_L_CmdQ); in HAL_TSP_STC33_CmdQGet()
2604 REG16_SET(&_RegCtrl->reg15b8, TSP_cnt_33b_ld); in HAL_TSP_STC33_CmdQGet()
3268 REG16_SET(&_RegCtrl->HW2_Config3, TSP_VQ_EN|TSP_VQ2PINGPONG_EN); in HAL_TSP_VQ_Enable()
3272 REG16_CLR(&_RegCtrl->HW2_Config3, TSP_VQ_EN|TSP_VQ2PINGPONG_EN); in HAL_TSP_VQ_Enable()
4197 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_VERSION); in HAL_TSP_HCMD_GetInfo()
4200 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_DATE); in HAL_TSP_HCMD_GetInfo()
4203 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_VERSION); in HAL_TSP_HCMD_GetInfo()
4208 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_INFO); in HAL_TSP_HCMD_GetInfo()
4211 u32Data = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_GetInfo()
4212 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_HCMD_GetInfo()
4221 REG32_W(&_RegCtrl->MCU_Data0 , u32Value); in HAL_TSP_HCMD_BufRst()
4222 REG32_W(&_RegCtrl->MCU_Cmd , TSP_MCU_CMD_BUFRST); in HAL_TSP_HCMD_BufRst()
4232 REG32_W(&_RegCtrl->MCU_Data0, u32Addr); in HAL_TSP_HCMD_Read()
4233 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_READ); in HAL_TSP_HCMD_Read()
4236 u32Data = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_Read()
4237 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_HCMD_Read()
4247 REG32_W(&_RegCtrl->MCU_Data0, u32Addr); in HAL_TSP_HCMD_Write()
4248 REG32_W(&_RegCtrl->MCU_Data1, u32Value); in HAL_TSP_HCMD_Write()
4249 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_WRITE); in HAL_TSP_HCMD_Write()
4252 u32Data = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_Write()
4253 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_HCMD_Write()
4263 REG32_W(&_RegCtrl->MCU_Data1, 0); in HAL_TSP_HCMD_Alive()
4264 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_ALIVE); //@TODO check FW HCMD in HAL_TSP_HCMD_Alive()
4266 u32Data = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_Alive()
4267 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_HCMD_Alive()
4274 REG32_W(&_RegCtrl->MCU_Data0, mcu_data0); in HAL_TSP_HCMD_SET()
4275 REG32_W(&_RegCtrl->MCU_Data1, mcu_data1); in HAL_TSP_HCMD_SET()
4276 REG32_W(&_RegCtrl->MCU_Cmd, mcu_cmd); in HAL_TSP_HCMD_SET()
4281 *pmcu_cmd = REG32_R(&_RegCtrl->MCU_Cmd); in HAL_TSP_HCMD_GET()
4282 *pmcu_data0 = REG32_R(&_RegCtrl->MCU_Data0); in HAL_TSP_HCMD_GET()
4283 *pmcu_data1 = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_GET()
4290 REG32_W(&_RegCtrl->MCU_Data0, FltId); in HAL_TSP_HCMD_SecRdyInt_Disable()
4291 REG32_W(&_RegCtrl->MCU_Data1,u32Data); in HAL_TSP_HCMD_SecRdyInt_Disable()
4292 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_SECRDYINT_DISABLE); // @TODO add HCMD list here in HAL_TSP_HCMD_SecRdyInt_Disable()
4294 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_HCMD_SecRdyInt_Disable()
4303 REG32_W(&_RegCtrl->MCU_Data0, u32Enable); in HAL_TSP_HCMD_Dbg()
4304 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_DBG); in HAL_TSP_HCMD_Dbg()
4307 u32Data = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_Dbg()
4308 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_HCMD_Dbg()
4310 return REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_Dbg()
4315 REG16_CLR(&_RegCtrl->DBG_SEL, TSP_DBG_SEL_MASK); in HAL_TSP_GetDBGStatus()
4316 REG16_SET(&_RegCtrl->DBG_SEL, ((u16Sel << TSP_DBG_SEL_SHIFT) & TSP_DBG_SEL_MASK)); in HAL_TSP_GetDBGStatus()
4318 return REG32_R(&_RegCtrl->TSP_Debug); in HAL_TSP_GetDBGStatus()
4334 REG16_SET(&_RegCtrl->HwInt_Stat, (TSP_HWINT_EN_MASK & u32Mask)); in HAL_TSP_INT_Enable()
4345 REG16_SET(&_RegCtrl->HwInt2_Stat, (TSP_HWINT2_EN_MASK & (u32Mask >> 8))); in HAL_TSP_INT_Enable()
4358 REG16_SET(&_RegCtrl->HwInt3_Stat, (TSP_HWINT3_EN_MASK & (u32Mask >> 16))); in HAL_TSP_INT_Enable()
4365 REG16_W(&_RegCtrl->HwInt_Stat, in HAL_TSP_INT_Disable()
4366 (REG16_R(&_RegCtrl->HwInt_Stat) & ~(TSP_HWINT_EN_MASK & (u32Mask)))); in HAL_TSP_INT_Disable()
4368 REG16_W(&_RegCtrl->HwInt2_Stat, in HAL_TSP_INT_Disable()
4369 (REG16_R(&_RegCtrl->HwInt2_Stat) & ~(TSP_HWINT2_EN_MASK & (u32Mask >> 8)))); in HAL_TSP_INT_Disable()
4371 REG16_W(&_RegCtrl->HwInt3_Stat, in HAL_TSP_INT_Disable()
4372 (REG16_R(&_RegCtrl->HwInt3_Stat) & ~(TSP_HWINT3_EN_MASK & (u32Mask >> 16)))); in HAL_TSP_INT_Disable()
4379 REG16_SET(&_RegCtrl->HwInt_Stat, ((u32Mask << TSP_HWINT_STATUS_SHIFT) & TSP_HWINT_STATUS_MASK)); in HAL_TSP_INT_ClrHW()
4380 REG16_CLR(&_RegCtrl->HwInt_Stat, ((u32Mask << TSP_HWINT_STATUS_SHIFT) & TSP_HWINT_STATUS_MASK)); in HAL_TSP_INT_ClrHW()
4382 …REG16_SET(&_RegCtrl->HwInt2_Stat, (((u32Mask >> 8) << TSP_HWINT2_STATUS_SHIFT) & TSP_HWINT2_STATUS… in HAL_TSP_INT_ClrHW()
4383 …REG16_CLR(&_RegCtrl->HwInt2_Stat, (((u32Mask >> 8) << TSP_HWINT2_STATUS_SHIFT) & TSP_HWINT2_STATUS… in HAL_TSP_INT_ClrHW()
4385 …REG16_SET(&_RegCtrl->HwInt3_Stat, (((u32Mask >> 16) << TSP_HWINT3_STATUS_SHIFT) & TSP_HWINT3_STATU… in HAL_TSP_INT_ClrHW()
4386 …REG16_CLR(&_RegCtrl->HwInt3_Stat, (((u32Mask >> 16) << TSP_HWINT3_STATUS_SHIFT) & TSP_HWINT3_STATU… in HAL_TSP_INT_ClrHW()
4394 …status = (MS_U32)(((REG16_R(&_RegCtrl->HwInt3_Stat) & TSP_HWINT3_STATUS_MASK) >> TSP_HWINT3_STATUS… in HAL_TSP_INT_GetHW()
4397 …status |= ((MS_U32)(((REG16_R(&_RegCtrl->HwInt2_Stat) & TSP_HWINT2_STATUS_MASK) >> TSP_HWINT2_STAT… in HAL_TSP_INT_GetHW()
4400 …status |= ((MS_U32)((REG16_R(&_RegCtrl->HwInt_Stat) & TSP_HWINT_STATUS_MASK) >> TSP_HWINT_STATUS_S… in HAL_TSP_INT_GetHW()
4407 REG32_W(&_RegCtrl->SwInt_Stat, 0); in HAL_TSP_INT_ClrSW()
4412 return REG32_R(&_RegCtrl->SwInt_Stat); in HAL_TSP_INT_GetSW()
4713 REG16_SET(&_RegCtrl->reg160C, TSP_ORZ_DMAW_PROT_EN); in HAL_TSP_OR_Address_Protect_En()
4717 REG16_CLR(&_RegCtrl->reg160C, TSP_ORZ_DMAW_PROT_EN); in HAL_TSP_OR_Address_Protect_En()
4731 … REG32_W(&_RegCtrl->ORZ_DMAW_LBND,(MS_U32)((phyMiuOffsetLB >> MIU_BUS) & TSP_ORZ_DMAW_LBND_MASK)); in HAL_TSP_OR_Address_Protect()
4732 … REG32_W(&_RegCtrl->ORZ_DMAW_UBND,(MS_U32)((phyMiuOffsetUB >> MIU_BUS) & TSP_ORZ_DMAW_UBND_MASK)); in HAL_TSP_OR_Address_Protect()
4740 REG16_SET(&_RegCtrl->reg15b4, TSP_SEC_CB_PVR2_DAMW_PROTECT_EN); in HAL_TSP_SEC_Address_Protect_En()
4744 REG16_CLR(&_RegCtrl->reg15b4, TSP_SEC_CB_PVR2_DAMW_PROTECT_EN); in HAL_TSP_SEC_Address_Protect_En()
4764 REG32_W(&_RegCtrl->DMAW_LBND0, u32LBnd); in HAL_TSP_SEC_Address_Protect()
4765 REG32_W(&_RegCtrl->DMAW_UBND0, u32UBnd); in HAL_TSP_SEC_Address_Protect()
4768 REG32_W(&_RegCtrl->DMAW_LBND1, u32LBnd); in HAL_TSP_SEC_Address_Protect()
4769 REG32_W(&_RegCtrl->DMAW_UBND1, u32UBnd); in HAL_TSP_SEC_Address_Protect()
4903 REG32_W(&_RegCtrl->MCU_Data1, u32Config0); in HAL_TSP_CMD_Run()
4904 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_SEC_CC_CHECK_DISABLE); in HAL_TSP_CMD_Run()
4906 u32Data = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_CMD_Run()
4907 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_CMD_Run()
5020 u16PktDmxSrc = _CLR_(REG16_R(&_RegCtrl->reg15b8), TSP_MATCH_PID_SRC_MASK); in HAL_DSCMB_GetStatus()
5049 REG16_W(&_RegCtrl->reg15b8, u16PktDmxSrc); in HAL_DSCMB_GetStatus()
5051 …REG16_W(&_RegCtrl->PVRConfig, _SET_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // Set 1 to… in HAL_DSCMB_GetStatus()
5054 REG16_W(&_RegCtrl->PVRConfig, _CLR_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // freeze in HAL_DSCMB_GetStatus()
5056 u16WordId = _CLR_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_SEL_MASK); in HAL_DSCMB_GetStatus()
5061 REG16_MSK_W(&_RegCtrl->PVRConfig,TSP_MATCH_PID_SEL_MASK, u16WordId); in HAL_DSCMB_GetStatus()
5068 *pu32ScmbSts = _AND_(REG32_R(&_RegCtrl->TsPidScmbStatTsin), u32PIDFltMask); in HAL_DSCMB_GetStatus()
5070 …REG16_W(&_RegCtrl->PVRConfig, _SET_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // re-enable in HAL_DSCMB_GetStatus()