Lines Matching refs:REG32_TSO
184 } REG32_TSO; typedef
476 REG32_TSO PIDFLTS[16]; //20~3e PID00~0F
563 REG32_TSO CFG_TSO_60_63[2]; //60~63
565 REG32_TSO CFG_TSO_65_68[2]; //65~68
586 REG32_TSO LPCR2_BUF; //6c~6d
587 REG32_TSO LPCR2_BUF1; //6e~6f
589 REG32_TSO TIMESTAMP; //70~71
590 REG32_TSO TIMESTAMP1; //72~73
592 REG32_TSO TSO2MI_RADDR; //74~75
593 REG32_TSO TSO2MI_RADDR1; //76~77
671 REG32_TSO TSO_DEBUG; //7d~7e
733 REG32_TSO SVQ1_BASE; //18~19
752 REG32_TSO SVQ2_BASE; //1C~1D
755 REG32_TSO SVQ3_BASE; //20~21
758 REG32_TSO SVQ4_BASE; //24~25
761 REG32_TSO SVQ5_BASE; //28~29
764 REG32_TSO SVQ6_BASE; //2C~2D
810 REG32_TSO SVQ_STATUS; //34~35
831 REG32_TSO SVQ_STATUS2; //36~37
869 REG32_TSO DELTA; //38~39
919 REG32_TSO REG_TSO1_REG_AVG_PKT_TIME; //72~73
920 REG32_TSO REG_TSO1_MIN_PKT_TIME; //74~75
921 REG32_TSO REG_TSO1_MAX_PKT_TIME; //76~77
951 REG32_TSO REG_TSO2_PVR1_STR2MI_HEAD; //01~02
952 REG32_TSO REG_TSO2_PVR1_STR2MI_MID; //03~04
953 REG32_TSO REG_TSO2_PVR1_STR2MI_TAIL; //05~06
954 REG32_TSO REG_TSO2_PVR1_STR2MI_HEAD2; //07~08
955 REG32_TSO REG_TSO2_PVR1_STR2MI_MID2; //09~0A
956 REG32_TSO REG_TSO2_PVR1_STR2MI_TAIL2; //0B~0C
972 REG32_TSO REG_TSO2_PVR1_DMAW_LBUD; //0E~0F
973 REG32_TSO REG_TSO2_PVR1_DMAW_UBUD; //10~11
974 REG32_TSO REG_TSO2_PVR1_LPCR1; //12~13
999 REG32_TSO REG_TSO2_PVR1_DMAW_WADDR_ERR; //22~23
1001 REG32_TSO REG_TSO2_STR2MI_WADR_R; //25~26
1035 REG32_TSO REG_TSO2_PCR1_LOW32_CFG38_39; //38~39
1041 REG32_TSO REG_TSO2_PCR2_LOW32_CFG3B_3C; //3B~3C
1047 REG32_TSO REG_TSO2_PCR3_LOW32_CFG3E_3F; //3E~3F
1053 REG32_TSO REG_TSO2_PCR4_LOW32_CFG41_42; //41~42
1059 REG32_TSO REG_TSO2_PCR5_LOW32_CFG44_45; //44~45
1065 REG32_TSO REG_TSO2_PCR6_LOW32_CFG47_48; //47~48
1080 REG32_TSO REG_TSO2_SG_PDFLT_SVID_EN[2]; //51~54