k7u/tso/halTSO.c

49 static MS_VIRT   _u32TSORegBase = 0;  variable
102 #define TSO_CLKGEN0_REG(addr)       (*((volatile MS_U16*)(_u32TSORegBase + 0x1600UL + ((addr)<<2))))
148 …#define TSO_CLKGEN1_REG(addr)       (*((volatile MS_U16*)(_u32TSORegBase + 0x6600UL + ((addr)<<2))…
157 #define TSO_CLKGEN2_REG(addr)       (*((volatile MS_U16*)(_u32TSORegBase + 0x1400UL + ((addr)<<2))))
164 #define TSP_TOP_REG(addr)           (*((volatile MS_U16*)(_u32TSORegBase + 0x3c00UL + ((addr)<<2))))
201 #define TSO_MIUDIG0_REG(addr)       (*((volatile MS_U16*)(_u32TSORegBase + 0x0C00UL + ((addr)<<2))))
202 #define TSO_MIUDIG1_REG(addr)       (*((volatile MS_U16*)(_u32TSORegBase + 0x2400UL + ((addr)<<2))))
226     _u32TSORegBase = u32BankAddr;  in HAL_TSO_SetBank()
227     _TSOCtrl  = (REG_Ctrl_TSO*)(_u32TSORegBase+ REG_CTRL_BASE_TSO);      // 0x1706  in HAL_TSO_SetBank()
228     _TSOCtrl1 = (REG_Ctrl_TSO1*)(_u32TSORegBase+ REG_CTRL_BASE_TSO1);   // 0x1612  in HAL_TSO_SetBank()
229     _TSOCtrl2 = (REG_Ctrl_TSO2*)(_u32TSORegBase+ REG_CTRL_BASE_TSO2);   // 0x1539  in HAL_TSO_SetBank()
231     _TSOCtrl4 = (REG_Ctrl_TSO4*)(_u32TSORegBase+ REG_CTRL_BASE_TSO4);   // 0x1215  in HAL_TSO_SetBank()
606     u32Speed = (MS_U32)((volatile MS_U16*)(_u32TSORegBase))[NPM_REG_MIPS_PLLCLK];