Lines Matching refs:TSO_CONFIG5
247 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5), TSO_CONFIG5_FIXED_MIU_REG_FLUSH); in HAL_TSO_Init()
1744 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_1); in HAL_TSO_Livein_3Wire()
1747 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_2); in HAL_TSO_Livein_3Wire()
1750 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_3); in HAL_TSO_Livein_3Wire()
1753 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_4); in HAL_TSO_Livein_3Wire()
1756 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_5); in HAL_TSO_Livein_3Wire()
1759 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_6); in HAL_TSO_Livein_3Wire()
1771 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_1); in HAL_TSO_Livein_3Wire()
1774 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_2); in HAL_TSO_Livein_3Wire()
1777 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_3); in HAL_TSO_Livein_3Wire()
1780 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_4); in HAL_TSO_Livein_3Wire()
1783 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_5); in HAL_TSO_Livein_3Wire()
1786 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_6); in HAL_TSO_Livein_3Wire()
1800 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_REG_TSIO_MODE); in HAL_TSO_TsioMode_En()
1804 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_REG_TSIO_MODE); in HAL_TSO_TsioMode_En()
1812 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_REG_TSIO2OPIF); in HAL_TSO_Tsio2Opif_En()
1816 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_REG_TSIO2OPIF); in HAL_TSO_Tsio2Opif_En()
2311 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_BYPASS_SVQ_FOR_CH1); in HAL_TSO_Set_SvqBypass()
2315 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_BYPASS_SVQ_FOR_CH1); in HAL_TSO_Set_SvqBypass()