156 #define TSO_CLKGEN2_REG(addr)       (*((volatile MS_U16*)(_u32TSORegBase + 0x1400UL + ((addr)<<2))))  macro
426             u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO1_IN) & REG_CLKGEN0_TSO_IN_MASK;  in HAL_TSO_GetInputTSIF_Status()
430             u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO2_IN) & REG_CLKGEN0_TSO_IN_MASK;  in HAL_TSO_GetInputTSIF_Status()
434             u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO3_IN) & REG_CLKGEN0_TSO_IN_MASK;  in HAL_TSO_GetInputTSIF_Status()
438             u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO4_IN) & REG_CLKGEN0_TSO_IN_MASK;  in HAL_TSO_GetInputTSIF_Status()
442             u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO5_IN) & REG_CLKGEN0_TSO_IN_MASK;  in HAL_TSO_GetInputTSIF_Status()
500         u16value = TSO_CLKGEN2_REG(u16Reg) & ~REG_CLKGEN0_TSO_IN_MASK;  in HAL_TSO_Set_InClk()
525         TSO_CLKGEN2_REG(u16Reg) = u16value;  in HAL_TSO_Set_InClk()
2162         TSO_CLKGEN2_REG(REG_CLKGEN2_TSO1_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;  in HAL_TSO_PowerCtrl()
2163         TSO_CLKGEN2_REG(REG_CLKGEN2_TSO2_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;  in HAL_TSO_PowerCtrl()
2164         TSO_CLKGEN2_REG(REG_CLKGEN2_TSO3_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;  in HAL_TSO_PowerCtrl()
2165         TSO_CLKGEN2_REG(REG_CLKGEN2_TSO4_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;  in HAL_TSO_PowerCtrl()
2166         TSO_CLKGEN2_REG(REG_CLKGEN2_TSO5_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;  in HAL_TSO_PowerCtrl()
2178         TSO_CLKGEN2_REG(REG_CLKGEN2_TSO1_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;  in HAL_TSO_PowerCtrl()
2179         TSO_CLKGEN2_REG(REG_CLKGEN2_TSO2_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;  in HAL_TSO_PowerCtrl()
2180         TSO_CLKGEN2_REG(REG_CLKGEN2_TSO3_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;  in HAL_TSO_PowerCtrl()
2181         TSO_CLKGEN2_REG(REG_CLKGEN2_TSO4_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;  in HAL_TSO_PowerCtrl()
2182         TSO_CLKGEN2_REG(REG_CLKGEN2_TSO5_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;  in HAL_TSO_PowerCtrl()