48 static MS_VIRT   _u32TSIORegBase = 0;  variable
472     _u32TSIORegBase = u32BankAddr;  in HAL_TSIO_SetBank()
473     _TSIOCtrl0 = (REG_Ctrl_TSIO0*)(_u32TSIORegBase+ REG_CTRL_BASE_TSIO0);   // 0x171A  in HAL_TSIO_SetBank()
474     _TSIOCtrl1 = (REG_Ctrl_TSIO1*)(_u32TSIORegBase+ REG_CTRL_BASE_TSIO1);   // 0x171B  in HAL_TSIO_SetBank()
475     _TSIOCtrl2 = (REG_Ctrl_TSIO2*)(_u32TSIORegBase+ REG_CTRL_BASE_TSIO2);   // 0x171C  in HAL_TSIO_SetBank()
476     _TSIOCtrl3 = (REG_Ctrl_TSIO3*)(_u32TSIORegBase+ REG_CTRL_BASE_TSIO3);   // 0x1739  in HAL_TSIO_SetBank()
477 …  _TSIOCtrlLOCDEC = (REG_Ctrl_TSIO_LOCDEC*)(_u32TSIORegBase+ REG_CTRL_BASE_TSIO_LOCDEC);  // 0x171E  in HAL_TSIO_SetBank()
478     _TSOCtrl0 = (REG_Ctrl_TSO0*)(_u32TSIORegBase+ REG_CTRL_BASE_TSO0);   //0x1706  in HAL_TSIO_SetBank()
479     _TSOCtrl2 = (REG_Ctrl_TSO2*)(_u32TSIORegBase+ REG_CTRL_BASE_TSO2);   // 0x1539  in HAL_TSIO_SetBank()
480     _TSOCtrl3 = (REG_Ctrl_TSO3*)(_u32TSIORegBase+ REG_CTRL_BASE_TSO3);   // 0x171D  in HAL_TSIO_SetBank()
481     _TSIOCHIPTOP = (REG_Ctrl_CHIPTOP*)(_u32TSIORegBase+ REG_CTRL_BASE_CHIPTOP);   // 0x101E  in HAL_TSIO_SetBank()
482     _TSIO_CLKGEN0 = (REG_Ctrl_CLOCKGEN0*)(_u32TSIORegBase+ REG_CTRL_BASE_CLOCKGEN0);   // 0x100B  in HAL_TSIO_SetBank()
483     _TSIOCtrlPHY = (REG_Ctrl_TSIO_PHY*)(_u32TSIORegBase+ REG_CTRL_BASE_TSIO_PHY);   // 0x171F  in HAL_TSIO_SetBank()
484     _TSPCtrl8 = (REG_Ctrl_TSP8 *)(_u32TSIORegBase+ 0xC4E00UL);     // TSP8  0x1627  in HAL_TSIO_SetBank()
485     _TSIO_STRLD = (REG_Ctrl_STRLD*)(_u32TSIORegBase+ REG_CTRL_BASE_STRLD); //STRLD 0x1029  in HAL_TSIO_SetBank()