Lines Matching refs:phyMiuOffsetPvrBuf0

5408     MS_PHY phyMiuOffsetPvrBuf0, phyMiuOffsetPvrBuf1;  in HAL_PVR_SetBuf()  local
5409     _phy_to_miu_offset(u8MiuSel, phyMiuOffsetPvrBuf0, u32StartAddr0);  in HAL_PVR_SetBuf()
5412     MS_U32 u32EndAddr0 = phyMiuOffsetPvrBuf0 + u32BufSize0;  in HAL_PVR_SetBuf()
5422 …          REG32_W(&_RegCtrl->TsRec_Head, (phyMiuOffsetPvrBuf0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);  in HAL_PVR_SetBuf()
5426 …REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (phyMiuOffsetPvrBuf0 >>MIU_BUS) & TSP_STR2MI2_ADDR_MASK);  in HAL_PVR_SetBuf()
5440 …   REG32_W(&_RegCtrl->Str2mi_head1_pvr2, (phyMiuOffsetPvrBuf0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);  in HAL_PVR_SetBuf()
5444 …REG32_W(&(_RegCtrl->Str2mi_mid1_wptr_pvr2), (phyMiuOffsetPvrBuf0 >>MIU_BUS) & TSP_STR2MI2_ADDR_MAS…  in HAL_PVR_SetBuf()
5458 …   REG32_W(&(_RegCtrl2->CFG_17_18), (phyMiuOffsetPvrBuf0 >> MIU_BUS) & CFG_17_18_PVR3_STR2MI_HEAD);  in HAL_PVR_SetBuf()
5462 …    REG32_W(&(_RegCtrl2->CFG_19_1A), (phyMiuOffsetPvrBuf0 >> MIU_BUS) & CFG_19_1A_PVR3_STR2MI_MID);  in HAL_PVR_SetBuf()
5476 …     REG32_W(&(_RegCtrl2->CFG_24_25), (phyMiuOffsetPvrBuf0>>MIU_BUS) & CFG_24_25_PVR4_STR2MI_HEAD);  in HAL_PVR_SetBuf()
5480 …      REG32_W(&(_RegCtrl2->CFG_26_27), (phyMiuOffsetPvrBuf0>>MIU_BUS) & CFG_26_27_PVR4_STR2MI_MID);  in HAL_PVR_SetBuf()