Lines Matching refs:_RegCtrl2
50 static REG_Ctrl2* _RegCtrl2 = NULL; // TSP3 variable
207 _RegCtrl2 = (REG_Ctrl2*)(u32BankAddr + 0xE0400UL); // TSP3 0x1702, in HAL_TSP_SetBank()
350 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PID_BYPASS3_REC); in HAL_TSP_HwPatch()
351 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PID_BYPASS4_REC); in HAL_TSP_HwPatch()
356 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_LPCR1_RLD); in HAL_TSP_HwPatch()
357 REG16_SET((&_RegCtrl2->CFG_23), CFG_23_PVR4_LPCR1_RLD); in HAL_TSP_HwPatch()
414 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_MIU_FIXED_LAST_DONE_Z_ABT_ALL); in HAL_TSP_HwPatch()
415 REG16_SET(&_RegCtrl2->CFG_10, CFG_10_MIU_CHECK_MI2RDY_ABT_ALL); in HAL_TSP_HwPatch()
457 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Reset()
462 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Reset()
463 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2); in HAL_TSP_Reset()
464 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3); in HAL_TSP_Reset()
475 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Reset()
476 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2); in HAL_TSP_Reset()
477 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3); in HAL_TSP_Reset()
489 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT0); in HAL_TSP_Path_Reset()
490 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF0 | CFG_12_REG_REST_PDBF0); in HAL_TSP_Path_Reset()
494 REG16_CLR(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF0 | CFG_12_REG_REST_PDBF0); in HAL_TSP_Path_Reset()
495 REG16_CLR(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT0); in HAL_TSP_Path_Reset()
501 REG16_SET(&_RegCtrl2->CFG_00,CFG_00_RST_TS_FIN1); in HAL_TSP_Path_Reset()
502 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT1); in HAL_TSP_Path_Reset()
503 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF1 | CFG_12_REG_REST_PDBF1); in HAL_TSP_Path_Reset()
507 REG16_CLR(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF1 | CFG_12_REG_REST_PDBF1); in HAL_TSP_Path_Reset()
508 REG16_CLR(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT1); in HAL_TSP_Path_Reset()
509 REG16_CLR(&_RegCtrl2->CFG_00,CFG_00_RST_TS_FIN1); in HAL_TSP_Path_Reset()
514 REG16_SET(&_RegCtrl2->CFG_05,CFG_05_RST_TS_FIN2); in HAL_TSP_Path_Reset()
515 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT2); in HAL_TSP_Path_Reset()
516 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF2 | CFG_12_REG_REST_PDBF2); in HAL_TSP_Path_Reset()
520 REG16_CLR(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF2 | CFG_12_REG_REST_PDBF2); in HAL_TSP_Path_Reset()
521 REG16_CLR(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT2); in HAL_TSP_Path_Reset()
522 REG16_CLR(&_RegCtrl2->CFG_05,CFG_05_RST_TS_FIN2); in HAL_TSP_Path_Reset()
527 REG16_SET(&_RegCtrl2->CFG_0A,CFG_0A_RST_TS_FIN3); in HAL_TSP_Path_Reset()
528 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT3); in HAL_TSP_Path_Reset()
529 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF3 | CFG_12_REG_REST_PDBF3); in HAL_TSP_Path_Reset()
533 REG16_CLR(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF3 | CFG_12_REG_REST_PDBF3); in HAL_TSP_Path_Reset()
534 REG16_CLR(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT3); in HAL_TSP_Path_Reset()
535 REG16_CLR(&_RegCtrl2->CFG_0A,CFG_0A_RST_TS_FIN3); in HAL_TSP_Path_Reset()
860 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF0); in HAL_TSP_PktBuf_Reset()
863 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF1); in HAL_TSP_PktBuf_Reset()
866 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF2); in HAL_TSP_PktBuf_Reset()
869 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF3); in HAL_TSP_PktBuf_Reset()
880 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF0); in HAL_TSP_PktBuf_Reset()
883 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF1); in HAL_TSP_PktBuf_Reset()
886 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF2); in HAL_TSP_PktBuf_Reset()
889 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF3); in HAL_TSP_PktBuf_Reset()
904 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF0); in HAL_TSP_RecvBuf_Reset()
907 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF1); in HAL_TSP_RecvBuf_Reset()
910 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF2); in HAL_TSP_RecvBuf_Reset()
913 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF3); in HAL_TSP_RecvBuf_Reset()
924 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF0); in HAL_TSP_RecvBuf_Reset()
927 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF1); in HAL_TSP_RecvBuf_Reset()
930 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF2); in HAL_TSP_RecvBuf_Reset()
933 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF3); in HAL_TSP_RecvBuf_Reset()
981 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TS_IF3_EN); in HAL_TSP_TSIF_LiveEn()
1001 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_TS_IF3_EN); in HAL_TSP_TSIF_LiveEn()
1666 …REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TSP_FILE_SEGMENT1); // for wishbone DMA (load firm… in HAL_TSP_TSIF_FileEn()
1667 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_SEGMENT_TSIF1); in HAL_TSP_TSIF_FileEn()
1668 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TS_DATA_PORT_SEL1); in HAL_TSP_TSIF_FileEn()
1669 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_IN_TSIF1_EN); //filein enable in HAL_TSP_TSIF_FileEn()
1672 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_FILE_SEGMENT2); in HAL_TSP_TSIF_FileEn()
1673 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_TSP_FILE_SEGMENT_TSIF2); in HAL_TSP_TSIF_FileEn()
1674 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TS_DATA_PORT_SEL2); in HAL_TSP_TSIF_FileEn()
1675 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_TSP_FILEIN_TSIF2); in HAL_TSP_TSIF_FileEn()
1678 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TSP_FILE_SEGMENT3); in HAL_TSP_TSIF_FileEn()
1679 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_TSP_FILE_SEGMENT_TSIF3); in HAL_TSP_TSIF_FileEn()
1680 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TS_DATA_PORT_SEL3); in HAL_TSP_TSIF_FileEn()
1681 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_TSP_FILE_IN_TSIF3); in HAL_TSP_TSIF_FileEn()
1697 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_TSP_FILE_SEGMENT1); in HAL_TSP_TSIF_FileEn()
1698 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_SEGMENT_TSIF1); in HAL_TSP_TSIF_FileEn()
1699 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_TS_DATA_PORT_SEL1); in HAL_TSP_TSIF_FileEn()
1700 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_IN_TSIF1_EN); in HAL_TSP_TSIF_FileEn()
1703 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_FILE_SEGMENT2); in HAL_TSP_TSIF_FileEn()
1704 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_TSP_FILE_SEGMENT_TSIF2); in HAL_TSP_TSIF_FileEn()
1705 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_TSP_FILEIN_TSIF2); in HAL_TSP_TSIF_FileEn()
1706 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TS_DATA_PORT_SEL2); in HAL_TSP_TSIF_FileEn()
1709 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_TSP_FILE_SEGMENT3); in HAL_TSP_TSIF_FileEn()
1710 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_TSP_FILE_SEGMENT_TSIF3); in HAL_TSP_TSIF_FileEn()
1711 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_TS_DATA_PORT_SEL3); in HAL_TSP_TSIF_FileEn()
1712 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_TSP_FILE_IN_TSIF3); in HAL_TSP_TSIF_FileEn()
1738 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TS_DATA3_SWAP); in HAL_TSP_TSIF_BitSwap()
1758 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_TS_DATA3_SWAP); in HAL_TSP_TSIF_BitSwap()
1784 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_EXT_SYNC_SEL3); in HAL_TSP_TSIF_ExtSync()
1806 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_EXT_SYNC_SEL3); in HAL_TSP_TSIF_ExtSync()
1878 REG16_SET(&(_RegCtrl2->CFG_0B), CFG_0B_P_SEL3); in HAL_TSP_TSIF_Parl()
1898 REG16_CLR(&(_RegCtrl2->CFG_0B), CFG_0B_P_SEL3); in HAL_TSP_TSIF_Parl()
2024 REG16_MSK_W(&_RegCtrl2->CFG_01, CFG_01_PDFLT2_FILE_SRC, u16Src); in HAL_TSP_ReDirect_File()
2480 …REG16_W(&_RegCtrl2->CFG_02, (REG16_R(&_RegCtrl2->CFG_02) & ~CFG_02_PKT_CHK_SIZE_FIN1) | (CFG_02_PK… in HAL_TSP_Filein_PktSize()
2483 …REG16_W(&_RegCtrl2->CFG_07, (REG16_R(&_RegCtrl2->CFG_07) & ~CFG_07_PKT_CHK_SIZE_FIN2) | (CFG_07_PK… in HAL_TSP_Filein_PktSize()
2486 …REG16_W(&_RegCtrl2->CFG_0C, (REG16_R(&_RegCtrl2->CFG_0C) & ~CFG_0C_PKT_CHK_SIZE_FIN3) | (CFG_0C_PK… in HAL_TSP_Filein_PktSize()
2508 REG32_W(&_RegCtrl2->CFG_30_31, phyMiuOffsetFileinAddr); in HAL_TSP_Filein_Addr()
2512 REG32_W(&_RegCtrl2->CFG_35_36, phyMiuOffsetFileinAddr); in HAL_TSP_Filein_Addr()
2516 REG32_W(&_RegCtrl2->CFG_3A_3B, phyMiuOffsetFileinAddr); in HAL_TSP_Filein_Addr()
2531 REG32_W(&_RegCtrl2->CFG_32_33, size); in HAL_TSP_Filein_Size()
2534 REG32_W(&_RegCtrl2->CFG_37_38, size); in HAL_TSP_Filein_Size()
2537 REG32_W(&_RegCtrl2->CFG_3C_3D, size); in HAL_TSP_Filein_Size()
2552 REG16_SET(&_RegCtrl2->CFG_34, CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_START); in HAL_TSP_Filein_Start()
2555 REG16_SET(&_RegCtrl2->CFG_39, CFG_39_FILEIN_CTRL_TSIF2_START); in HAL_TSP_Filein_Start()
2558 REG16_SET(&_RegCtrl2->CFG_3E, CFG_3E_FILEIN_CTRL_TSIF3_START); in HAL_TSP_Filein_Start()
2615 …REG16_SET(&_RegCtrl2->CFG_34, (CFG_34_REG_TSP_FILEIN_INIT_TRUST_TSIF1 | CFG_34_REG_TSP_FILEIN_CTRL… in HAL_TSP_Filein_Init_Trust_Start()
2618 … REG16_SET(&_RegCtrl2->CFG_39, (CFG_39_FILEIN_INIT_TRUST_TSIF2 | CFG_39_FILEIN_CTRL_TSIF2_START)); in HAL_TSP_Filein_Init_Trust_Start()
2621 … REG16_SET(&_RegCtrl2->CFG_3E, (CFG_3E_FILEIN_INIT_TRUST_TSIF3 | CFG_3E_FILEIN_CTRL_TSIF3_START)); in HAL_TSP_Filein_Init_Trust_Start()
2635 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF0); in HAL_TSP_Filein_Abort()
2638 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF1); in HAL_TSP_Filein_Abort()
2641 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF2); in HAL_TSP_Filein_Abort()
2644 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF3); in HAL_TSP_Filein_Abort()
2655 REG16_CLR(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF0); in HAL_TSP_Filein_Abort()
2658 REG16_CLR(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF1); in HAL_TSP_Filein_Abort()
2661 REG16_CLR(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF2); in HAL_TSP_Filein_Abort()
2664 REG16_CLR(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF3); in HAL_TSP_Filein_Abort()
2682 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Filein_CmdQRst()
2685 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2); in HAL_TSP_Filein_CmdQRst()
2688 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3); in HAL_TSP_Filein_CmdQRst()
2702 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Filein_CmdQRst()
2705 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2); in HAL_TSP_Filein_CmdQRst()
2708 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3); in HAL_TSP_Filein_CmdQRst()
2723 …return (CFG_3F_REG_TSIF1_CMD_QUEUE_SIZE - (REG16_R(&_RegCtrl2->CFG_3F) & CFG_3F_REG_TSIF1_CMD_QUEU… in HAL_TSP_Filein_CmdQSlot()
2725 …return (CFG_40_REG_TSIF2_CMD_QUEUE_SIZE - (REG16_R(&_RegCtrl2->CFG_40) & CFG_40_REG_TSIF2_CMD_QUEU… in HAL_TSP_Filein_CmdQSlot()
2727 …return (CFG_41_REG_TSIF3_CMD_QUEUE_SIZE - (REG16_R(&_RegCtrl2->CFG_41) & CFG_41_REG_TSIF3_CMD_QUEU… in HAL_TSP_Filein_CmdQSlot()
2741 return (REG16_R(&_RegCtrl2->CFG_3F) & CFG_3F_REG_TSIF1_CMD_QUEUE_WR_CNT); in HAL_TSP_Filein_CmdQCnt()
2743 return (REG16_R(&_RegCtrl2->CFG_40) & CFG_40_REG_TSIF2_CMD_QUEUE_WR_CNT); in HAL_TSP_Filein_CmdQCnt()
2745 return (REG16_R(&_RegCtrl2->CFG_41) & CFG_41_REG_TSIF3_CMD_QUEUE_WR_CNT); in HAL_TSP_Filein_CmdQCnt()
2758 …return ((REG16_R(&_RegCtrl2->CFG_3F) & CFG_3F_REG_TSIF1_CMD_QUEUE_WR_LEVEL) >> CFG_3F_REG_TSIF1_CM… in HAL_TSP_Filein_CmdQLv()
2760 …return ((REG16_R(&_RegCtrl2->CFG_40) & CFG_40_REG_TSIF2_CMD_QUEUE_WR_LEVEL) >> CFG_3F_REG_TSIF1_CM… in HAL_TSP_Filein_CmdQLv()
2762 …return ((REG16_R(&_RegCtrl2->CFG_41) & CFG_41_REG_TSIF3_CMD_QUEUE_WR_LEVEL) >> CFG_3F_REG_TSIF1_CM… in HAL_TSP_Filein_CmdQLv()
2779 REG16_W(&_RegCtrl2->CFG_03, delay & CFG_03_TSP_FILE_TIMER1); in HAL_TSP_Filein_ByteDelay()
2780 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TIMER_EN1); in HAL_TSP_Filein_ByteDelay()
2783 REG16_W(&_RegCtrl2->CFG_08, delay & CFG_08_TSP_FILE_TIMER2); in HAL_TSP_Filein_ByteDelay()
2784 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_TIMER_EN2); in HAL_TSP_Filein_ByteDelay()
2787 REG16_W(&_RegCtrl2->CFG_0D, delay & CFG_0D_TSP_FILE_TIMER3); in HAL_TSP_Filein_ByteDelay()
2788 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TIMER_EN3); in HAL_TSP_Filein_ByteDelay()
2803 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_TIMER_EN1); in HAL_TSP_Filein_ByteDelay()
2804 REG16_W(&_RegCtrl2->CFG_03, 0x0000); in HAL_TSP_Filein_ByteDelay()
2807 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_TIMER_EN2); in HAL_TSP_Filein_ByteDelay()
2808 REG16_W(&_RegCtrl2->CFG_08, 0x0000); in HAL_TSP_Filein_ByteDelay()
2811 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_TIMER_EN3); in HAL_TSP_Filein_ByteDelay()
2812 REG16_W(&_RegCtrl2->CFG_0D, 0x0000); in HAL_TSP_Filein_ByteDelay()
2827 return !(REG16_R(&_RegCtrl2->CFG_34) & CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_DONE); in HAL_TSP_Filein_Status()
2829 return !(REG16_R(&_RegCtrl2->CFG_39) & CFG_39_FILEIN_CTRL_TSIF2_DONE); in HAL_TSP_Filein_Status()
2831 return !(REG16_R(&_RegCtrl2->CFG_3E) & CFG_3E_FILEIN_CTRL_TSIF3_DONE); in HAL_TSP_Filein_Status()
2927 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_PKT192_EN1); in HAL_TSP_Filein_PacketMode()
2930 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_EN2); in HAL_TSP_Filein_PacketMode()
2933 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_PKT192_EN3); in HAL_TSP_Filein_PacketMode()
2947 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_PKT192_EN1); in HAL_TSP_Filein_PacketMode()
2950 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_EN2); in HAL_TSP_Filein_PacketMode()
2953 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_PKT192_EN3); in HAL_TSP_Filein_PacketMode()
2972 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_PKT192_BLK_DISABLE1); in HAL_TSP_Filein_BlockTimeStamp()
2975 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_BLK_DISABLE2); in HAL_TSP_Filein_BlockTimeStamp()
2978 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_PKT192_BLK_DISABLE3); in HAL_TSP_Filein_BlockTimeStamp()
2991 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_PKT192_BLK_DISABLE1); in HAL_TSP_Filein_BlockTimeStamp()
2994 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_BLK_DISABLE2); in HAL_TSP_Filein_BlockTimeStamp()
2997 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_PKT192_BLK_DISABLE3); in HAL_TSP_Filein_BlockTimeStamp()
3046 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_LPCR2_WLD1); in HAL_TSP_Filein_SetTimeStamp()
3047 REG32_W(&_RegCtrl2->CFG_50_51, u32Stamp); in HAL_TSP_Filein_SetTimeStamp()
3048 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_LPCR2_WLD1); in HAL_TSP_Filein_SetTimeStamp()
3051 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_LPCR2_WLD2); in HAL_TSP_Filein_SetTimeStamp()
3052 REG32_W(&_RegCtrl2->CFG_52_53, u32Stamp); in HAL_TSP_Filein_SetTimeStamp()
3053 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_LPCR2_WLD2); in HAL_TSP_Filein_SetTimeStamp()
3056 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_LPCR2_WLD3); in HAL_TSP_Filein_SetTimeStamp()
3057 REG32_W(&_RegCtrl2->CFG_54_55, u32Stamp); in HAL_TSP_Filein_SetTimeStamp()
3058 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_LPCR2_WLD3); in HAL_TSP_Filein_SetTimeStamp()
3128 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_LPCR2_LOAD_TSIF1); in HAL_TSP_Filein_GetTimeStamp()
3129 u32Stamp = REG32_R(&_RegCtrl2->CFG_50_51); in HAL_TSP_Filein_GetTimeStamp()
3130 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_LPCR2_LOAD_TSIF1); in HAL_TSP_Filein_GetTimeStamp()
3133 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_LPCR2_LOAD_TSIF2); in HAL_TSP_Filein_GetTimeStamp()
3134 u32Stamp = REG32_R(&_RegCtrl2->CFG_52_53); in HAL_TSP_Filein_GetTimeStamp()
3135 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_LPCR2_LOAD_TSIF2); in HAL_TSP_Filein_GetTimeStamp()
3138 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_LPCR2_LOAD_TSIF3); in HAL_TSP_Filein_GetTimeStamp()
3139 u32Stamp = REG32_R(&_RegCtrl2->CFG_54_55); in HAL_TSP_Filein_GetTimeStamp()
3140 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_LPCR2_LOAD_TSIF3); in HAL_TSP_Filein_GetTimeStamp()
3156 return REG32_R(&_RegCtrl2->CFG_42_43); in HAL_TSP_Filein_PktTimeStamp()
3158 return REG32_R(&_RegCtrl2->CFG_44_45); in HAL_TSP_Filein_PktTimeStamp()
3160 return REG32_R(&_RegCtrl2->CFG_46_47); in HAL_TSP_Filein_PktTimeStamp()
3175 *pu32Addr = (MS_PHY)(REG32_R(&_RegCtrl2->CFG_6A_6B) & CFG_6A_6B_TSP2MI_RADDR_S_TSIF1); in HAL_TSP_Filein_GetCurAddr()
3178 *pu32Addr = (MS_PHY)(REG32_R(&_RegCtrl2->CFG_6C_6D) & CFG_6C_6D_TSP2MI_RADDR_S_TSIF2); in HAL_TSP_Filein_GetCurAddr()
3181 *pu32Addr = (MS_PHY)(REG32_R(&_RegCtrl2->CFG_6E_6F) & CFG_6E_6F_TSP2MI_RADDR_S_TSIF3); in HAL_TSP_Filein_GetCurAddr()
3245 REG16_W(&_RegCtrl2->CFG_75, (u32Key & CFG_75_FI_MOBF_INDEC_TSIF1_MASK)); in HAL_TSP_Filein_MOBF_Enable()
3248 REG16_W(&_RegCtrl2->CFG_76, (u32Key & CFG_76_FI_MOBF_INDEC_TSIF2_MASK)); in HAL_TSP_Filein_MOBF_Enable()
3251 REG16_W(&_RegCtrl2->CFG_77, (u32Key & CFG_77_FI_MOBF_INDEC_TSIF3_MASK)); in HAL_TSP_Filein_MOBF_Enable()
3265 REG16_W(&_RegCtrl2->CFG_75, 0); in HAL_TSP_Filein_MOBF_Enable()
3268 REG16_W(&_RegCtrl2->CFG_76, 0); in HAL_TSP_Filein_MOBF_Enable()
3271 REG16_W(&_RegCtrl2->CFG_77, 0); in HAL_TSP_Filein_MOBF_Enable()
3729 REG16_MSK_W(&_RegCtrl2->CFG_01, CFG_01_PCR0_SRC_MASK, src << CFG_01_PCR0_SRC_SHIFT); in HAL_TSP_PcrFlt_SetSrc()
3733 REG16_MSK_W(&_RegCtrl2->CFG_01, CFG_01_PCR1_SRC_MASK, src << CFG_01_PCR1_SRC_SHIFT); in HAL_TSP_PcrFlt_SetSrc()
3776 … *pPcrSrc = (REG16_R(&_RegCtrl2->CFG_01) & CFG_01_PCR0_SRC_MASK) >> CFG_01_PCR0_SRC_SHIFT; in HAL_TSP_PcrFlt_GetSrc()
3780 … *pPcrSrc = (REG16_R(&_RegCtrl2->CFG_01) & CFG_01_PCR1_SRC_MASK) >> CFG_01_PCR1_SRC_SHIFT; in HAL_TSP_PcrFlt_GetSrc()
4492 return REG16_R(&_RegCtrl2->CFG_70) & CFG_70_MATCHECED_VPID_3D_MASK; in HAL_TSP_FIFO_PidHit()
4494 return REG16_R(&_RegCtrl2->CFG_7D) & CFG_7D_MATCHECED_VPID_3_MASK; in HAL_TSP_FIFO_PidHit()
4496 return REG16_R(&_RegCtrl2->CFG_7E) & CFG_7E_MATCHECED_VPID_4_MASK; in HAL_TSP_FIFO_PidHit()
4500 return REG16_R(&_RegCtrl2->CFG_71) & CFG_71_MATCHECED_APID_B_MASK; in HAL_TSP_FIFO_PidHit()
4502 return REG16_R(&_RegCtrl2->CFG_74) & CFG_74_MATCHECED_APID_C_MASK; in HAL_TSP_FIFO_PidHit()
4504 return REG16_R(&_RegCtrl2->CFG_7C) & CFG_7C_MATCHECED_APID_D_MASK; in HAL_TSP_FIFO_PidHit()
5157 REG16_MSK_W(&(_RegCtrl2->CFG_15), CFG_15_PVR3_SRC, pktDmxId << CFG_15_PVR3_SRC_SHIFT); in HAL_PVR_Init()
5158 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_REG_PINGPONG_EN); in HAL_PVR_Init()
5162 REG16_MSK_W(&(_RegCtrl2->CFG_15), CFG_15_PVR4_SRC, pktDmxId << CFG_15_PVR4_SRC_SHIFT); in HAL_PVR_Init()
5163 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_REG_PINGPONG_EN); in HAL_PVR_Init()
5195 REG16_CLR(&(_RegCtrl2->CFG_15), CFG_15_PVR3_SRC); in HAL_PVR_Exit()
5196 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_REG_PINGPONG_EN); in HAL_PVR_Exit()
5199 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR); in HAL_PVR_Exit()
5200 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR); in HAL_PVR_Exit()
5204 REG16_CLR(&(_RegCtrl2->CFG_15), CFG_15_PVR4_SRC); in HAL_PVR_Exit()
5205 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_REG_PINGPONG_EN); in HAL_PVR_Exit()
5208 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_RST_WADR); in HAL_PVR_Exit()
5209 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_RST_WADR); in HAL_PVR_Exit()
5247 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR); in HAL_PVR_Start()
5248 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR); in HAL_PVR_Start()
5251 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_EN); in HAL_PVR_Start()
5255 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_RST_WADR); in HAL_PVR_Start()
5256 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_RST_WADR); in HAL_PVR_Start()
5259 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_EN); in HAL_PVR_Start()
5285 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_EN); in HAL_PVR_Stop()
5289 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_EN); in HAL_PVR_Stop()
5309 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_PAUSE); in HAL_PVR_Pause()
5312 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_PAUSE); in HAL_PVR_Pause()
5329 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_PAUSE); in HAL_PVR_Pause()
5332 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_PAUSE); in HAL_PVR_Pause()
5355 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PID_BYPASS3_REC); in HAL_PVR_RecPid()
5356 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_REC_ALL3); in HAL_PVR_RecPid()
5359 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PID_BYPASS4_REC); in HAL_PVR_RecPid()
5360 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_REC_ALL4); in HAL_PVR_RecPid()
5379 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PID_BYPASS3_REC); in HAL_PVR_RecPid()
5380 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_REC_ALL3); in HAL_PVR_RecPid()
5383 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PID_BYPASS4_REC); in HAL_PVR_RecPid()
5384 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_REC_ALL4); in HAL_PVR_RecPid()
5458 … REG32_W(&(_RegCtrl2->CFG_17_18), (phyMiuOffsetPvrBuf0 >> MIU_BUS) & CFG_17_18_PVR3_STR2MI_HEAD); in HAL_PVR_SetBuf()
5460 REG32_W(&(_RegCtrl2->CFG_1B_1C), (u32EndAddr0 >> MIU_BUS) & CFG_1B_1C_PVR3_STR2MI_TAIL); in HAL_PVR_SetBuf()
5462 … REG32_W(&(_RegCtrl2->CFG_19_1A), (phyMiuOffsetPvrBuf0 >> MIU_BUS) & CFG_19_1A_PVR3_STR2MI_MID); in HAL_PVR_SetBuf()
5465 … REG32_W(&(_RegCtrl2->CFG_1D_1E), (phyMiuOffsetPvrBuf1 >> MIU_BUS) & CFG_1D_1E_PVR3_STR2MI_HEAD2); in HAL_PVR_SetBuf()
5467 … REG32_W(&(_RegCtrl2->CFG_21_22), (u32EndAddr1 >> MIU_BUS) & CFG_21_22_PVR3_STR2MI_TAIL2); in HAL_PVR_SetBuf()
5469 … REG32_W(&(_RegCtrl2->CFG_1F_20), (phyMiuOffsetPvrBuf1 >> MIU_BUS) & CFG_1F_20_PVR3_STR2MI_MID2); in HAL_PVR_SetBuf()
5476 … REG32_W(&(_RegCtrl2->CFG_24_25), (phyMiuOffsetPvrBuf0>>MIU_BUS) & CFG_24_25_PVR4_STR2MI_HEAD); in HAL_PVR_SetBuf()
5478 REG32_W(&(_RegCtrl2->CFG_28_29), (u32EndAddr0>>MIU_BUS) & CFG_28_29_PVR4_STR2MI_TAIL); in HAL_PVR_SetBuf()
5480 … REG32_W(&(_RegCtrl2->CFG_26_27), (phyMiuOffsetPvrBuf0>>MIU_BUS) & CFG_26_27_PVR4_STR2MI_MID); in HAL_PVR_SetBuf()
5483 … REG32_W(&(_RegCtrl2->CFG_2A_2B), (phyMiuOffsetPvrBuf1>>MIU_BUS) & CFG_2A_2B_PVR4_STR2MI_HEAD2); in HAL_PVR_SetBuf()
5485 REG32_W(&(_RegCtrl2->CFG_2E_2F), (u32EndAddr1>>MIU_BUS) & CFG_2E_2F_PVR4_STR2MI_TAIL2); in HAL_PVR_SetBuf()
5487 … REG32_W(&(_RegCtrl2->CFG_2C_2D), (phyMiuOffsetPvrBuf1>>MIU_BUS) & CFG_2C_2D_PVR4_STR2MI_MID2); in HAL_PVR_SetBuf()
5517 REG32_W(&(_RegCtrl2->CFG_17_18), (u32StartAddr0>>MIU_BUS) & CFG_17_18_PVR3_STR2MI_HEAD); in HAL_PVR_SetStr2Miu_StartAddr()
5520 … REG32_W(&(_RegCtrl2->CFG_1D_1E), (u32StartAddr1>>MIU_BUS) & CFG_1D_1E_PVR3_STR2MI_HEAD2); in HAL_PVR_SetStr2Miu_StartAddr()
5524 REG32_W(&(_RegCtrl2->CFG_24_25), (u32StartAddr0>>MIU_BUS) & CFG_24_25_PVR4_STR2MI_HEAD); in HAL_PVR_SetStr2Miu_StartAddr()
5527 … REG32_W(&(_RegCtrl2->CFG_2A_2B), (u32StartAddr1>>MIU_BUS) & CFG_2A_2B_PVR4_STR2MI_HEAD2); in HAL_PVR_SetStr2Miu_StartAddr()
5575 REG32_W(&(_RegCtrl2->CFG_19_1A), (u32MidAddr0>>4) & CFG_19_1A_PVR3_STR2MI_MID); in HAL_PVR_SetStr2Miu_MidAddr()
5578 REG32_W(&(_RegCtrl2->CFG_1F_20), (u32MidAddr1>>4) & CFG_1F_20_PVR3_STR2MI_MID2); in HAL_PVR_SetStr2Miu_MidAddr()
5582 REG32_W(&(_RegCtrl2->CFG_26_27), (u32MidAddr0>>4) & CFG_26_27_PVR4_STR2MI_MID); in HAL_PVR_SetStr2Miu_MidAddr()
5585 REG32_W(&(_RegCtrl2->CFG_2C_2D), (u32MidAddr1>>4) & CFG_2C_2D_PVR4_STR2MI_MID2); in HAL_PVR_SetStr2Miu_MidAddr()
5612 REG32_W(&(_RegCtrl2->CFG_1B_1C), (u32EndAddr0>>MIU_BUS) & CFG_1B_1C_PVR3_STR2MI_TAIL); in HAL_PVR_SetStr2Miu_EndAddr()
5615 REG32_W(&(_RegCtrl2->CFG_21_22), (u32EndAddr1>>MIU_BUS) & CFG_21_22_PVR3_STR2MI_TAIL2); in HAL_PVR_SetStr2Miu_EndAddr()
5619 REG32_W(&(_RegCtrl2->CFG_28_29), (u32EndAddr0>>MIU_BUS) & CFG_28_29_PVR4_STR2MI_TAIL); in HAL_PVR_SetStr2Miu_EndAddr()
5622 REG32_W(&(_RegCtrl2->CFG_2E_2F), (u32EndAddr1>>MIU_BUS) & CFG_2E_2F_PVR4_STR2MI_TAIL2); in HAL_PVR_SetStr2Miu_EndAddr()
5648 WritePtr = REG32_R(&(_RegCtrl2->CFG_66_67)) << MIU_BUS; in HAL_PVR_GetWritePtr()
5651 WritePtr = REG32_R(&(_RegCtrl2->CFG_68_69)) << MIU_BUS; in HAL_PVR_GetWritePtr()
5679 *eSrc = ((REG16_R(&(_RegCtrl2->CFG_15 )) & CFG_15_PVR3_SRC) >> CFG_15_PVR3_SRC_SHIFT); in HAL_PVR_GetEngSrc()
5683 *eSrc = ((REG16_R(&(_RegCtrl2->CFG_15 )) & CFG_15_PVR4_SRC) >> CFG_15_PVR4_SRC_SHIFT); in HAL_PVR_GetEngSrc()
5931 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_PKT192_EN); in HAL_PVR_SetStrPacketMode()
5934 REG16_SET((&_RegCtrl2->CFG_23), CFG_23_PVR4_PKT192_EN); in HAL_PVR_SetStrPacketMode()
5951 REG16_CLR((&_RegCtrl2->CFG_16), CFG_16_PVR3_PKT192_EN); in HAL_PVR_SetStrPacketMode()
5954 REG16_CLR((&_RegCtrl2->CFG_23), CFG_23_PVR4_PKT192_EN); in HAL_PVR_SetStrPacketMode()
5983 REG16_CLR((&_RegCtrl2->CFG_16), CFG_16_PVR3_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
5985 u32lpcr = REG32_R((&_RegCtrl2->CFG_62_63)); in HAL_PVR_GetPVRTimeStamp()
5987 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
5990 REG16_CLR((&_RegCtrl2->CFG_23), CFG_23_PVR4_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
5992 u32lpcr = REG32_R((&_RegCtrl2->CFG_64_65)); in HAL_PVR_GetPVRTimeStamp()
5994 REG16_SET((&_RegCtrl2->CFG_23), CFG_23_PVR4_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
6021 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PVR3_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
6023 REG32_W((&_RegCtrl2->CFG_62_63), u32Stamp); in HAL_PVR_SetPVRTimeStamp()
6025 REG16_CLR(&_RegCtrl2->CFG_16, CFG_16_PVR3_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
6028 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PVR4_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
6030 REG32_W((&_RegCtrl2->CFG_64_65), u32Stamp); in HAL_PVR_SetPVRTimeStamp()
6032 REG16_CLR(&_RegCtrl2->CFG_23, CFG_23_PVR4_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
6044 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD0); in HAL_PVR_SetPVRTimeStamp_Stream()
6046 REG32_W(&_RegCtrl2->CFG_56_57, u32Stamp); in HAL_PVR_SetPVRTimeStamp_Stream()
6048 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD0); in HAL_PVR_SetPVRTimeStamp_Stream()
6051 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD1); in HAL_PVR_SetPVRTimeStamp_Stream()
6053 REG32_W(&_RegCtrl2->CFG_58_59, u32Stamp); in HAL_PVR_SetPVRTimeStamp_Stream()
6055 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD1); in HAL_PVR_SetPVRTimeStamp_Stream()
6058 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD2); in HAL_PVR_SetPVRTimeStamp_Stream()
6060 REG32_W(&_RegCtrl2->CFG_5A_5B, u32Stamp); in HAL_PVR_SetPVRTimeStamp_Stream()
6062 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD2); in HAL_PVR_SetPVRTimeStamp_Stream()
6065 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD3); in HAL_PVR_SetPVRTimeStamp_Stream()
6067 REG32_W(&_RegCtrl2->CFG_5C_5D, u32Stamp); in HAL_PVR_SetPVRTimeStamp_Stream()
6069 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD3); in HAL_PVR_SetPVRTimeStamp_Stream()
6089 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PVR3_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
6092 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PVR4_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
6109 REG16_CLR(&_RegCtrl2->CFG_16, CFG_16_PVR3_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
6112 REG16_CLR(&_RegCtrl2->CFG_23, CFG_23_PVR4_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
6203 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PVR3_BLOCK_DIS); in HAL_PVR_Block_Dis()
6206 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PVR4_BLOCK_DIS); in HAL_PVR_Block_Dis()
6223 REG16_CLR(&_RegCtrl2->CFG_16, CFG_16_PVR3_BLOCK_DIS); in HAL_PVR_Block_Dis()
6226 REG16_CLR(&_RegCtrl2->CFG_23, CFG_23_PVR4_BLOCK_DIS); in HAL_PVR_Block_Dis()
6246 …REG16_MSK_W(&_RegCtrl2->CFG_16, CFG_16_PVR3_BURST_LEN_MASK, (u16BurstMode << CFG_16_PVR3_BURST_LEN… in HAL_PVR_BurstLen()
6249 …REG16_MSK_W(&_RegCtrl2->CFG_23, CFG_23_PVR4_BURST_LEN_MASK, (u16BurstMode << CFG_23_PVR4_BURST_LEN… in HAL_PVR_BurstLen()
6265 REG16_SET((&_RegCtrl2->CFG_12), CFG_12_TIMESTAMP_SEL_PVR1 << (u32PVREng)); in HAL_PVR_TimeStamp_Sel()
6269 REG16_CLR((&_RegCtrl2->CFG_12), CFG_12_TIMESTAMP_SEL_PVR1 << (u32PVREng)); in HAL_PVR_TimeStamp_Sel()
6342 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_EN0 << (u32pktDmxId*2)); in HAL_PVR_TimeStamp_Stream_En()
6346 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_EN0 << (u32pktDmxId*2)); in HAL_PVR_TimeStamp_Stream_En()
6361 REG16_W(&_RegCtrl2->CFG_78_7B[0], (u32Key & CFG_78_PVR3_INDEX)); in HAL_PVR_MOBF_Enable()
6364 REG16_W(&_RegCtrl2->CFG_78_7B[2], (u32Key & CFG_78_PVR3_INDEX)); in HAL_PVR_MOBF_Enable()
6667 REG16_MSK_W(&_RegCtrl2->CFG_11, CFG_11_RECEIVE_BUF0_SRC, inputSrc<<(bufIdx * 2)); in HAL_TSP_Set_RcvBuf_Src()
6670 REG16_MSK_W(&_RegCtrl2->CFG_11, CFG_11_RECEIVE_BUF1_SRC, inputSrc<<(bufIdx * 2)); in HAL_TSP_Set_RcvBuf_Src()
6673 REG16_MSK_W(&_RegCtrl2->CFG_11, CFG_11_RECEIVE_BUF2_SRC, inputSrc<<(bufIdx * 2)); in HAL_TSP_Set_RcvBuf_Src()
6676 REG16_MSK_W(&_RegCtrl2->CFG_11, CFG_11_RECEIVE_BUF3_SRC, inputSrc<<(bufIdx * 2)); in HAL_TSP_Set_RcvBuf_Src()