Lines Matching refs:_RegCtrl
49 static REG_Ctrl* _RegCtrl = NULL; // TSP0 and TSP1 variable
184 REG32_W(&_RegCtrl->Idr_Addr, (MS_VIRT)preg); in TSP32_IdrW()
185 REG32_W(&_RegCtrl->Idr_Write, value); in TSP32_IdrW()
186 REG16_W(&_RegCtrl->Idr_Ctrl, TSP_IDR_START | TSP_IDR_WRITE); in TSP32_IdrW()
197 REG32_W(&_RegCtrl->Idr_Addr, (MS_VIRT)preg); in TSP32_IdrR()
198 REG16_W(&_RegCtrl->Idr_Ctrl, TSP_IDR_START | TSP_IDR_READ); in TSP32_IdrR()
200 return REG32_R(&_RegCtrl->Idr_Read); in TSP32_IdrR()
206 _RegCtrl = (REG_Ctrl*)(u32BankAddr + 0x2A00UL); // TSP0 0x1015, TSP1 0x1016 in HAL_TSP_SetBank()
335 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_HW_STANDBY_MODE); in HAL_TSP_HwPatch()
340 …REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_BYTE_ADDR_DMA|TSP_HW_CFG4_ALT_TS_SIZE|TSP_HW_CFG4_WST… in HAL_TSP_HwPatch()
346 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_STANDBY); in HAL_TSP_HwPatch()
349 REG16_SET(&_RegCtrl->reg15b4, TSP_PVR_PID_BYPASS|TSP_PVR_PID_BYPASS2); in HAL_TSP_HwPatch()
354 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_RLD); in HAL_TSP_HwPatch()
355 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_RLD); in HAL_TSP_HwPatch()
359 REG16_SET(&_RegCtrl->reg15b8, TSP_REMOVE_DUP_AV_PKT); in HAL_TSP_HwPatch()
362 …REG16_SET(&_RegCtrl->HW2_Config3, TSP_VQ2PINGPONG_EN | TSP_RM_PKT_DEMUX_PIPE /*| TSP_PVR1_ALIGN_EN… in HAL_TSP_HwPatch()
365 …REG16_SET(&_RegCtrl->reg160C, TSP_DOUBLE_BUF_DESC/*| TSP_VQTX0_BLOCK_DIS|TSP_VQTX2_BLOCK_DIS|TSP_V… in HAL_TSP_HwPatch()
366 REG16_SET(&_RegCtrl->reg160E, TSP_RM_DMA_GLITCH); in HAL_TSP_HwPatch()
370 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE); in HAL_TSP_HwPatch()
373 REG16_SET(&_RegCtrl->PVRConfig, TSP_MATCH_PID_LD | TSP_REC_NULL); in HAL_TSP_HwPatch()
381 REG16_SET(&_RegCtrl->reg15b8, TSP_SERIAL_EXT_SYNC_1T); in HAL_TSP_HwPatch()
382 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_SYNC_RISING_DETECT); in HAL_TSP_HwPatch()
383 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_VALID_FALLING_DETECT) in HAL_TSP_HwPatch()
386 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_DATA_CHK_2T); in HAL_TSP_HwPatch()
456 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE); in HAL_TSP_Reset()
461 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET); in HAL_TSP_Reset()
465 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_WB_DMA_RESET); in HAL_TSP_Reset()
466 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_SW_RST); in HAL_TSP_Reset()
470 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_SW_RST); in HAL_TSP_Reset()
472 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_WB_DMA_RESET); in HAL_TSP_Reset()
474 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET); in HAL_TSP_Reset()
488 REG16_SET(&_RegCtrl->reg160C,TSP_TIMESTAMP_RESET); in HAL_TSP_Path_Reset()
496 REG16_CLR(&_RegCtrl->reg160C,TSP_TIMESTAMP_RESET); in HAL_TSP_Path_Reset()
746 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN); in HAL_TSP_CPU()
750 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN); in HAL_TSP_CPU()
758 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN); in HAL_TSP_ResetCPU()
762 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN); in HAL_TSP_ResetCPU()
778 REG32_W(&_RegCtrl->Cpu_Base, 0); // 16 bytes address unit in HAL_TSP_LoadFW()
792 … REG16_W(&_RegCtrl->Dnld_Ctrl_Addr, (MS_U16)(u32DnldCtrl & TSP_DNLD_ADDR_MASK)); // oneway register in HAL_TSP_LoadFW()
793 REG16_MSK_W(&_RegCtrl->Dnld_AddrH, TSP_DMA_RADDR_MSB_MASK, (MS_U16)u32DnldCtrl1); in HAL_TSP_LoadFW()
794 REG16_W(&_RegCtrl->Dnld_Ctrl_Size, _TSP_QMEM_SIZE); in HAL_TSP_LoadFW()
795 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START| TSP_CTRL_DNLD_DONE); in HAL_TSP_LoadFW()
796 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START); in HAL_TSP_LoadFW()
800 while (!(REG16_R(&_RegCtrl->TSP_Ctrl) & TSP_CTRL_DNLD_DONE)) in HAL_TSP_LoadFW()
806 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START| TSP_CTRL_DNLD_DONE); in HAL_TSP_LoadFW()
808 REG32_W(&_RegCtrl->Qmem_Imask, _TSP_QMEM_I_MASK); in HAL_TSP_LoadFW()
809 REG32_W(&_RegCtrl->Qmem_Ibase, _TSP_QMEM_I_ADDR_HIT); in HAL_TSP_LoadFW()
810 REG32_W(&_RegCtrl->Qmem_Dmask, _TSP_QMEM_D_MASK); in HAL_TSP_LoadFW()
811 REG32_W(&_RegCtrl->Qmem_Dbase, _TSP_QMEM_D_ADDR_HIT); in HAL_TSP_LoadFW()
972 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF0_ENABLE); in HAL_TSP_TSIF_LiveEn()
975 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF1_ENABLE); in HAL_TSP_TSIF_LiveEn()
978 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TS_IF2_EN); in HAL_TSP_TSIF_LiveEn()
992 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF0_ENABLE); in HAL_TSP_TSIF_LiveEn()
995 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF1_ENABLE); in HAL_TSP_TSIF_LiveEn()
998 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TS_IF2_EN); in HAL_TSP_TSIF_LiveEn()
1661 …REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE); // for wishbone DMA (load firm… in HAL_TSP_TSIF_FileEn()
1662 … REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_DATA_PORT_SEL); //Tsif0 output is live TS in HAL_TSP_TSIF_FileEn()
1663 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_TSFILE_EN); //filein enable in HAL_TSP_TSIF_FileEn()
1692 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE); in HAL_TSP_TSIF_FileEn()
1693 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_DATA_PORT_SEL); in HAL_TSP_TSIF_FileEn()
1694 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_TSFILE_EN); in HAL_TSP_TSIF_FileEn()
1729 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA0_SWAP); in HAL_TSP_TSIF_BitSwap()
1732 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA1_SWAP); in HAL_TSP_TSIF_BitSwap()
1735 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TS_DATA2_SWAP); in HAL_TSP_TSIF_BitSwap()
1749 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA0_SWAP); in HAL_TSP_TSIF_BitSwap()
1752 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA1_SWAP); in HAL_TSP_TSIF_BitSwap()
1755 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TS_DATA2_SWAP); in HAL_TSP_TSIF_BitSwap()
1775 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_EXTSYNC); in HAL_TSP_TSIF_ExtSync()
1778 REG16_SET(&_RegCtrl->Hw_Config2, TSP_HW_CFG2_TSIF1_EXTSYNC); in HAL_TSP_TSIF_ExtSync()
1781 REG32_SET(&_RegCtrl->PVR2_Config, TSP_EXT_SYNC_SEL2); in HAL_TSP_TSIF_ExtSync()
1797 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_EXTSYNC); in HAL_TSP_TSIF_ExtSync()
1800 REG16_CLR(&_RegCtrl->Hw_Config2, TSP_HW_CFG2_TSIF1_EXTSYNC); in HAL_TSP_TSIF_ExtSync()
1803 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_EXT_SYNC_SEL2); in HAL_TSP_TSIF_ExtSync()
1821 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP); in HAL_TSP_Filein_Bypass()
1824 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP1); in HAL_TSP_Filein_Bypass()
1827 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP2); in HAL_TSP_Filein_Bypass()
1830 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP3); in HAL_TSP_Filein_Bypass()
1843 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP); in HAL_TSP_Filein_Bypass()
1846 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP1); in HAL_TSP_Filein_Bypass()
1849 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP2); in HAL_TSP_Filein_Bypass()
1852 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP3); in HAL_TSP_Filein_Bypass()
1869 REG16_SET(&(_RegCtrl->Hw_Config0), TSP_HW_CFG0_TSIF0_PARL); in HAL_TSP_TSIF_Parl()
1872 REG16_SET(&(_RegCtrl->Hw_Config2), TSP_HW_CFG2_TSIF1_PARL); in HAL_TSP_TSIF_Parl()
1875 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_P_SEL2); in HAL_TSP_TSIF_Parl()
1889 REG16_CLR(&(_RegCtrl->Hw_Config0), TSP_HW_CFG0_TSIF0_PARL); in HAL_TSP_TSIF_Parl()
1892 REG16_CLR(&(_RegCtrl->Hw_Config2), TSP_HW_CFG2_TSIF1_PARL); in HAL_TSP_TSIF_Parl()
1895 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_P_SEL2); in HAL_TSP_TSIF_Parl()
2305 REG16_SET(&_RegCtrl->reg15b4, TSP_BD_AUD_EN); in HAL_TSP_BD_AUD_En()
2308 REG16_SET(&_RegCtrl->reg15b4, TSP_BD2_AUD_EN); in HAL_TSP_BD_AUD_En()
2320 REG16_CLR(&_RegCtrl->reg15b4, TSP_BD_AUD_EN); in HAL_TSP_BD_AUD_En()
2323 REG16_CLR(&_RegCtrl->reg15b4, TSP_BD2_AUD_EN); in HAL_TSP_BD_AUD_En()
2476 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_ALT_TS_SIZE); in HAL_TSP_Filein_PktSize()
2477 …REG16_W(&_RegCtrl->PktChkSizeFilein, (REG16_R(&_RegCtrl->PktChkSizeFilein) & ~TSP_PKT_SIZE_MASK) |… in HAL_TSP_Filein_PktSize()
2504 REG32_W(&_RegCtrl->TsDma_Addr, phyMiuOffsetFileinAddr); in HAL_TSP_Filein_Addr()
2528 REG32_W(&_RegCtrl->TsDma_Size, size); in HAL_TSP_Filein_Size()
2549 REG16_SET(&_RegCtrl->TsDma_Ctrl, TSP_TSDMA_CTRL_START); in HAL_TSP_Filein_Start()
2570 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_FILEIN_PAUSE); in HAL_TSP_File_Pause()
2591 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_FILEIN_PAUSE); in HAL_TSP_File_Resume()
2612 REG16_SET(&_RegCtrl->TsDma_Ctrl, (TSP_TSDMA_INIT_TRUST | TSP_TSDMA_CTRL_START)); in HAL_TSP_Filein_Init_Trust_Start()
2679 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET); in HAL_TSP_Filein_CmdQRst()
2699 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET); in HAL_TSP_Filein_CmdQRst()
2721 …return (TSP_CMDQ_SIZE - ((REG16_R(&_RegCtrl->TsDma_mdQ) & TSP_CMDQ_CNT_MASK) >> TSP_CMDQ_CNT_SHFT)… in HAL_TSP_Filein_CmdQSlot()
2739 return ((REG16_R(&_RegCtrl->TsDma_mdQ) & TSP_CMDQ_CNT_MASK) >> TSP_CMDQ_CNT_SHFT); in HAL_TSP_Filein_CmdQCnt()
2756 … return ((REG16_R(&_RegCtrl->TsDma_Ctrl) & TSP_CMDQ_WR_LEVEL_MASK) >> TSP_CMDQ_WR_LEVEL_SHFT); in HAL_TSP_Filein_CmdQLv()
2775 REG32_W(&_RegCtrl->TsFileIn_Timer, delay & TSP_FILE_TIMER_MASK); in HAL_TSP_Filein_ByteDelay()
2776 REG16_SET(&_RegCtrl->reg15b4, TSP_FILEIN_BYTETIMER_ENABLE); in HAL_TSP_Filein_ByteDelay()
2799 REG16_CLR(&_RegCtrl->reg15b4, TSP_FILEIN_BYTETIMER_ENABLE); in HAL_TSP_Filein_ByteDelay()
2800 REG32_W(&_RegCtrl->TsFileIn_Timer, 0x0000); in HAL_TSP_Filein_ByteDelay()
2825 return !(REG16_R(&_RegCtrl->TsDma_Ctrl) & TSP_TSDMA_FILEIN_DONE); in HAL_TSP_Filein_Status()
2855 if (REG16_R(&_RegCtrl->TSP_Ctrl1) & TSP_CTRL1_FILEIN_PAUSE ) in HAL_TSP_Filein_GetState()
2924 REG16_SET(&_RegCtrl->reg160C, TSP_FILEIN192_EN); in HAL_TSP_Filein_PacketMode()
2944 REG16_CLR(&_RegCtrl->reg160C, TSP_FILEIN192_EN); in HAL_TSP_Filein_PacketMode()
2969 REG16_CLR(&_RegCtrl->PktChkSizeFilein, TSP_PKT192_BLK_DIS_FIN); in HAL_TSP_Filein_BlockTimeStamp()
2988 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_PKT192_BLK_DIS_FIN); in HAL_TSP_Filein_BlockTimeStamp()
3041 REG16_SET(&_RegCtrl->reg160C, TSP_LPCR2_WLD); in HAL_TSP_Filein_SetTimeStamp()
3042 REG32_W(&_RegCtrl->LPcr2, u32Stamp); in HAL_TSP_Filein_SetTimeStamp()
3043 REG16_CLR(&_RegCtrl->reg160C, TSP_LPCR2_WLD); in HAL_TSP_Filein_SetTimeStamp()
3123 REG16_CLR(&_RegCtrl->reg160C, TSP_LPCR2_RLD); in HAL_TSP_Filein_GetTimeStamp()
3124 u32Stamp = REG32_R(&_RegCtrl->LPcr2); in HAL_TSP_Filein_GetTimeStamp()
3125 REG16_SET(&_RegCtrl->reg160C, TSP_LPCR2_RLD); in HAL_TSP_Filein_GetTimeStamp()
3154 return REG32_R(&_RegCtrl->TimeStamp_FileIn); in HAL_TSP_Filein_PktTimeStamp()
3172 *pu32Addr = (MS_PHY)(REG32_R(&_RegCtrl->TsFileIn_RPtr) & TSP_FILE_RPTR_MASK); in HAL_TSP_Filein_GetCurAddr()
3242 REG16_W(&_RegCtrl->Mobf_Filein_Idx, (u32Key & TSP_MOBF_FILEIN_MASK)); in HAL_TSP_Filein_MOBF_Enable()
3262 REG16_W(&_RegCtrl->Mobf_Filein_Idx, 0); in HAL_TSP_Filein_MOBF_Enable()
3365 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SEC_DMA_BURST_EN); in HAL_TSP_SecFlt_BurstLen()
3366 REG16_MSK_W(&_RegCtrl->Hw_Config4, TSP_HW_DMA_MODE_MASK, (burstMode << TSP_HW_DMA_MODE_SHIFT)); in HAL_TSP_SecFlt_BurstLen()
3641 REG16_SET(&_RegCtrl->PIDFLT_PCR0, TSP_PIDFLT_PCR0_EN); in HAL_TSP_PcrFlt_Enable()
3645 REG16_CLR(&_RegCtrl->PIDFLT_PCR0, TSP_PIDFLT_PCR0_EN); in HAL_TSP_PcrFlt_Enable()
3651 REG16_SET(&_RegCtrl->PIDFLT_PCR1, TSP_PIDFLT_PCR1_EN); in HAL_TSP_PcrFlt_Enable()
3655 REG16_CLR(&_RegCtrl->PIDFLT_PCR1, TSP_PIDFLT_PCR1_EN); in HAL_TSP_PcrFlt_Enable()
3688 REG16_MSK_W(&_RegCtrl->PIDFLT_PCR0, TSP_PIDFLT_PCR0_PID_MASK, u32Pid); in HAL_TSP_PcrFlt_SetPid()
3691 REG16_MSK_W(&_RegCtrl->PIDFLT_PCR1, TSP_PIDFLT_PCR1_PID_MASK, u32Pid); in HAL_TSP_PcrFlt_SetPid()
3710 return (REG16_R(&_RegCtrl->PIDFLT_PCR0) & TSP_PIDFLT_PCR0_PID_MASK); in HAL_TSP_PcrFlt_GetPid()
3712 return (REG16_R(&_RegCtrl->PIDFLT_PCR1) & TSP_PIDFLT_PCR1_PID_MASK); in HAL_TSP_PcrFlt_GetPid()
3838 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR0_READ); in HAL_TSP_PcrFlt_GetPcr()
3839 *pu32Pcr = REG32_R(&_RegCtrl->HWPCR0_L); in HAL_TSP_PcrFlt_GetPcr()
3840 *pu32Pcr_H = REG32_R(&_RegCtrl->HWPCR0_H) & 0x1; in HAL_TSP_PcrFlt_GetPcr()
3841 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR0_READ); in HAL_TSP_PcrFlt_GetPcr()
3844 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR1_READ); in HAL_TSP_PcrFlt_GetPcr()
3845 *pu32Pcr = REG32_R(&_RegCtrl->HWPCR1_L); in HAL_TSP_PcrFlt_GetPcr()
3846 *pu32Pcr_H = REG32_R(&_RegCtrl->HWPCR1_H) & 0x1; in HAL_TSP_PcrFlt_GetPcr()
3847 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR1_READ); in HAL_TSP_PcrFlt_GetPcr()
3872 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR0_RESET); in HAL_TSP_PcrFlt_Reset()
3873 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR0_RESET); in HAL_TSP_PcrFlt_Reset()
3876 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR1_RESET); in HAL_TSP_PcrFlt_Reset()
3877 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR1_RESET); in HAL_TSP_PcrFlt_Reset()
3899 REG16_W(&_RegCtrl->HwInt2_Stat, in HAL_TSP_PcrFlt_ClearInt()
3900 (REG16_R(&_RegCtrl->HwInt2_Stat) & (~TSP_HWINT2_STATUS_MASK)) | in HAL_TSP_PcrFlt_ClearInt()
3905 REG16_W(&_RegCtrl->HwInt2_Stat, in HAL_TSP_PcrFlt_ClearInt()
3906 (REG16_R(&_RegCtrl->HwInt2_Stat) & (~TSP_HWINT2_STATUS_MASK)) | in HAL_TSP_PcrFlt_ClearInt()
3911 REG16_W(&_RegCtrl->HwInt3_Stat, in HAL_TSP_PcrFlt_ClearInt()
3912 (REG16_R(&_RegCtrl->HwInt3_Stat) & (~TSP_HWINT3_STATUS_MASK)) | in HAL_TSP_PcrFlt_ClearInt()
3917 REG16_W(&_RegCtrl->HwInt3_Stat, in HAL_TSP_PcrFlt_ClearInt()
3918 (REG16_R(&_RegCtrl->HwInt3_Stat) & (~TSP_HWINT3_STATUS_MASK)) | in HAL_TSP_PcrFlt_ClearInt()
4087 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE); in HAL_TSP_STC64_Mode_En()
4091 REG16_CLR(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE); in HAL_TSP_STC64_Mode_En()
4100 REG32_W(&_RegCtrl->Pcr_L, stcL); in HAL_TSP_STC64_Set()
4101 REG32_W(&_RegCtrl->Pcr_H, stcH); in HAL_TSP_STC64_Set()
4104 REG32_W(&_RegCtrl->PCR64_2_L, stcL); in HAL_TSP_STC64_Set()
4105 REG32_W(&_RegCtrl->PCR64_2_H, stcH); in HAL_TSP_STC64_Set()
4110 REG16_SET(&_RegCtrl->STC_Config, TSP_STC_CFG_SET_TIME_BASE_64b_3); in HAL_TSP_STC64_Set()
4111 REG16_CLR(&_RegCtrl->STC_Config, TSP_STC_CFG_SET_TIME_BASE_64b_3); in HAL_TSP_STC64_Set()
4116 REG16_SET(&_RegCtrl->STC_Config, TSP_STC_CFG_SET_TIME_BASE_64b_4); in HAL_TSP_STC64_Set()
4117 REG16_CLR(&_RegCtrl->STC_Config, TSP_STC_CFG_SET_TIME_BASE_64b_4); in HAL_TSP_STC64_Set()
4127 REG16_CLR(&_RegCtrl->reg15b8, TSP_cnt_33b_ld); in HAL_TSP_STC64_Get()
4128 *pStcH = REG32_R(&_RegCtrl->Pcr_H); in HAL_TSP_STC64_Get()
4129 *pStcL = REG32_R(&_RegCtrl->Pcr_L); in HAL_TSP_STC64_Get()
4130 REG16_SET(&_RegCtrl->reg15b8, TSP_cnt_33b_ld); in HAL_TSP_STC64_Get()
4133 REG16_CLR(&_RegCtrl->reg15b8, TSP_64bit_PCR2_ld); in HAL_TSP_STC64_Get()
4134 *pStcH = REG32_R(&_RegCtrl->PCR64_2_H); in HAL_TSP_STC64_Get()
4135 *pStcL = REG32_R(&_RegCtrl->PCR64_2_L); in HAL_TSP_STC64_Get()
4136 REG16_SET(&_RegCtrl->reg15b8, TSP_64bit_PCR2_ld); in HAL_TSP_STC64_Get()
4139 REG16_CLR(&_RegCtrl->STC_Config, TSP_STC_CFG_CNT64b_3_LD); in HAL_TSP_STC64_Get()
4142 REG16_SET(&_RegCtrl->STC_Config, TSP_STC_CFG_CNT64b_3_LD); in HAL_TSP_STC64_Get()
4145 REG16_CLR(&_RegCtrl->STC_Config, TSP_STC_CFG_CNT64b_4_LD); in HAL_TSP_STC64_Get()
4148 REG16_SET(&_RegCtrl->STC_Config, TSP_STC_CFG_CNT64b_4_LD); in HAL_TSP_STC64_Get()
4157 REG16_W(&_RegCtrl->Pcr_H_CmdQ, stcH & TSP_REG_PCR_CMDQ_H); in HAL_TSP_STC33_CmdQSet()
4158 REG32_W(&_RegCtrl->Pcr_L_CmdQ, stcL); in HAL_TSP_STC33_CmdQSet()
4163 REG16_CLR(&_RegCtrl->reg15b8, TSP_cnt_33b_ld); in HAL_TSP_STC33_CmdQGet()
4164 *pStcH = REG16_R(&_RegCtrl->Pcr_H_CmdQ) & TSP_REG_PCR_CMDQ_H; in HAL_TSP_STC33_CmdQGet()
4165 *pStcL = REG32_R(&_RegCtrl->Pcr_L_CmdQ); in HAL_TSP_STC33_CmdQGet()
4166 REG16_SET(&_RegCtrl->reg15b8, TSP_cnt_33b_ld); in HAL_TSP_STC33_CmdQGet()
4174 … REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_VID_SRC_MASK, ((MS_U16)pktDmxId) << TSP_VID_SRC_SHIFT); in HAL_TSP_FIFO_SetSrc()
4177 … REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_VID3D_SRC_MASK, ((MS_U16)pktDmxId) << TSP_VID3D_SRC_SHIFT); in HAL_TSP_FIFO_SetSrc()
4186 … REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_AUD_SRC_MASK, ((MS_U16)pktDmxId) << TSP_AUD_SRC_SHIFT); in HAL_TSP_FIFO_SetSrc()
4189 … REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_AUDB_SRC_MASK, ((MS_U16)pktDmxId) << TSP_AUDB_SRC_SHIFT); in HAL_TSP_FIFO_SetSrc()
4192 … REG16_MSK_W(&_RegCtrl->PCR_Cfg, TSP_AUDC_SRC_MASK, ((MS_U16)pktDmxId) << TSP_AUDC_SRC_SHIFT); in HAL_TSP_FIFO_SetSrc()
4195 … REG16_MSK_W(&_RegCtrl->PCR_Cfg, TSP_AUDD_SRC_MASK, ((MS_U16)pktDmxId) << TSP_AUDD_SRC_SHIFT); in HAL_TSP_FIFO_SetSrc()
4207 *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_VID_SRC_MASK) >> TSP_VID_SRC_SHIFT; in HAL_TSP_FIFO_GetSrc()
4210 … *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_VID3D_SRC_MASK) >> TSP_VID3D_SRC_SHIFT; in HAL_TSP_FIFO_GetSrc()
4219 *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_AUD_SRC_MASK) >> TSP_AUD_SRC_SHIFT; in HAL_TSP_FIFO_GetSrc()
4222 *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_AUDB_SRC_MASK) >> TSP_AUDB_SRC_SHIFT; in HAL_TSP_FIFO_GetSrc()
4225 *pktDmxId = ((REG16_R(&_RegCtrl->PCR_Cfg)) & TSP_AUDC_SRC_MASK) >> TSP_AUDC_SRC_SHIFT; in HAL_TSP_FIFO_GetSrc()
4228 *pktDmxId = ((REG16_R(&_RegCtrl->PCR_Cfg)) & TSP_AUDD_SRC_MASK) >> TSP_AUDD_SRC_SHIFT; in HAL_TSP_FIFO_GetSrc()
4238 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_VID_EN); in HAL_TSP_FIFO_ClearAll()
4239 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN); in HAL_TSP_FIFO_ClearAll()
4242 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUD_EN); in HAL_TSP_FIFO_ClearAll()
4243 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDB_EN); in HAL_TSP_FIFO_ClearAll()
4244 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDC_EN); in HAL_TSP_FIFO_ClearAll()
4245 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDD_EN); in HAL_TSP_FIFO_ClearAll()
4254 REG16_SET(&_RegCtrl->reg15b4,TSP_AVFIFO_RD_EN); in HAL_TSP_FIFO_ReadEn()
4258 REG16_CLR(&_RegCtrl->reg15b4,TSP_AVFIFO_RD_EN); in HAL_TSP_FIFO_ReadEn()
4265 return (REG16_R(&_RegCtrl->PKT_CNT) & TSP_PKT_CNT_MASK); in HAL_TSP_FIFO_ReadPkt()
4310 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_VPID_BYPASS); in HAL_TSP_Flt_Bypass()
4322 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_APID_BYPASS); in HAL_TSP_Flt_Bypass()
4342 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_VPID_BYPASS); in HAL_TSP_Flt_Bypass()
4354 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_APID_BYPASS); in HAL_TSP_Flt_Bypass()
4388 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_VID_EN); in HAL_TSP_FIFO_Bypass()
4391 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN); in HAL_TSP_FIFO_Bypass()
4400 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUD_EN); in HAL_TSP_FIFO_Bypass()
4403 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDB_EN); in HAL_TSP_FIFO_Bypass()
4406 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDC_EN); in HAL_TSP_FIFO_Bypass()
4409 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDD_EN); in HAL_TSP_FIFO_Bypass()
4420 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_VID_EN); in HAL_TSP_FIFO_Bypass()
4423 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN); in HAL_TSP_FIFO_Bypass()
4432 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUD_EN); in HAL_TSP_FIFO_Bypass()
4435 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDB_EN); in HAL_TSP_FIFO_Bypass()
4438 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDC_EN); in HAL_TSP_FIFO_Bypass()
4441 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDD_EN); in HAL_TSP_FIFO_Bypass()
4490 return REG16_R(&_RegCtrl->Vd_Pid_Hit) & TSP_VPID_MASK; in HAL_TSP_FIFO_PidHit()
4498 return REG16_R(&_RegCtrl->Aud_Pid_Hit) & TSP_APID_MASK; in HAL_TSP_FIFO_PidHit()
4517 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_VFIFO); in HAL_TSP_FIFO_Reset()
4520 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_VFIFO3D); in HAL_TSP_FIFO_Reset()
4529 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_AFIFO); in HAL_TSP_FIFO_Reset()
4532 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_AFIFO2); in HAL_TSP_FIFO_Reset()
4535 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_AFIFO3); in HAL_TSP_FIFO_Reset()
4538 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_RESET_AFIFO4); in HAL_TSP_FIFO_Reset()
4549 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_VFIFO); in HAL_TSP_FIFO_Reset()
4552 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_VFIFO3D); in HAL_TSP_FIFO_Reset()
4561 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_AFIFO); in HAL_TSP_FIFO_Reset()
4564 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_AFIFO2); in HAL_TSP_FIFO_Reset()
4567 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_AFIFO3); in HAL_TSP_FIFO_Reset()
4570 REG16_CLR(&_RegCtrl->PktChkSizeFilein, TSP_RESET_AFIFO4); in HAL_TSP_FIFO_Reset()
4657 REG32_SET(&_RegCtrl->PVR2_Config, TSP_V_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4660 REG32_SET(&_RegCtrl->PVR2_Config, TSP_V3d_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4669 REG32_SET(&_RegCtrl->PVR2_Config, TSP_A_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4672 REG32_SET(&_RegCtrl->PVR2_Config, TSP_AD_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4675 REG32_SET(&_RegCtrl->PVR2_Config, TSP_AC_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4678 REG32_SET(&_RegCtrl->PVR2_Config, TSP_ADD_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4689 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_V_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4692 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_V3d_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4701 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_A_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4704 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_AD_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4707 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_AC_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4710 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_ADD_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4724 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_VFIFO; in HAL_TSP_FIFO_IsReset()
4727 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_VFIFO3D; in HAL_TSP_FIFO_IsReset()
4736 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_AFIFO; in HAL_TSP_FIFO_IsReset()
4739 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_AFIFO2; in HAL_TSP_FIFO_IsReset()
4742 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_AFIFO3; in HAL_TSP_FIFO_IsReset()
4745 u32Matched = REG16_R(&_RegCtrl->PktChkSizeFilein) & TSP_RESET_AFIFO4; in HAL_TSP_FIFO_IsReset()
4791 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO_LEVEL) >> TSP_VFIFO_LEVEL_SHFT; in HAL_TSP_FIFO_Level()
4793 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO3D_LEVEL) >> TSP_VFIFO3D_LEVEL_SHFT; in HAL_TSP_FIFO_Level()
4799 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFO_LEVEL) >> TSP_AFIFO_LEVEL_SHFT; in HAL_TSP_FIFO_Level()
4801 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFOB_LEVEL) >> TSP_AFIFOB_LEVEL_SHFT; in HAL_TSP_FIFO_Level()
4816 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO_FULL) >> TSP_VFIFO_FULL_SHFT; in HAL_TSP_FIFO_Overflow()
4818 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO3D_FULL) >> TSP_VFIFO3D_FULL_SHFT; in HAL_TSP_FIFO_Overflow()
4824 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFO_FULL) >> TSP_AFIFO_FULL_SHFT; in HAL_TSP_FIFO_Overflow()
4826 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFOB_FULL) >> TSP_AFIFOB_FULL_SHFT; in HAL_TSP_FIFO_Overflow()
4841 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO_EMPTY) >> TSP_VFIFO_EMPTY_SHFT; in HAL_TSP_FIFO_Empty()
4843 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO3D_EMPTY) >> TSP_VFIFO3D_EMPTY_SHFT; in HAL_TSP_FIFO_Empty()
4849 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFO_EMPTY) >> TSP_AFIFO_EMPTY_SHFT; in HAL_TSP_FIFO_Empty()
4851 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFOB_EMPTY) >> TSP_AFIFOB_EMPTY_SHFT; in HAL_TSP_FIFO_Empty()
4869 …REG16_W(&_RegCtrl->VQ0_CTRL, (REG16_R(&_RegCtrl->VQ0_CTRL) & (~TSP_VQ0_WR_THRESHOLD_MASK)) | ((0x8… in _HAL_TSP_VQ_TxConfig()
4870 …REG16_W(&_RegCtrl->VQ0_CTRL, (REG16_R(&_RegCtrl->VQ0_CTRL) & (~TSP_VQ0_FORCE_FIRE_CNT_1K_MASK)) | … in _HAL_TSP_VQ_TxConfig()
4873 …REG16_W(&_RegCtrl->VQ1_Config, (REG16_R(&_RegCtrl->VQ1_Config) & (~TSP_VQ1_WR_THRESHOLD_MASK)) | (… in _HAL_TSP_VQ_TxConfig()
4874 …REG16_W(&_RegCtrl->VQ1_Config, (REG16_R(&_RegCtrl->VQ1_Config) & (~TSP_VQ1_FORCEFIRE_CNT_1K_MASK))… in _HAL_TSP_VQ_TxConfig()
4877 …REG16_W(&_RegCtrl->VQ2_Config, (REG16_R(&_RegCtrl->VQ2_Config) & (~TSP_VQ2_WR_THRESHOLD_MASK)) | (… in _HAL_TSP_VQ_TxConfig()
4878 …REG16_W(&_RegCtrl->VQ2_Config, (REG16_R(&_RegCtrl->VQ2_Config) & (~TSP_VQ2_FORCEFIRE_CNT_1K_MASK))… in _HAL_TSP_VQ_TxConfig()
4881 …REG16_W(&_RegCtrl->VQ3_Config, (REG16_R(&_RegCtrl->VQ3_Config) & (~TSP_VQ3_WR_THRESHOLD_MASK)) | (… in _HAL_TSP_VQ_TxConfig()
4882 …REG16_W(&_RegCtrl->VQ3_Config, (REG16_R(&_RegCtrl->VQ3_Config) & (~TSP_VQ3_FORCEFIRE_CNT_1K_MASK))… in _HAL_TSP_VQ_TxConfig()
4930 REG32_W(&_RegCtrl->VQ0_BASE, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
4931 REG16_W(&_RegCtrl->VQ0_SIZE, u32VQ_PktNum); in HAL_TSP_VQ_Buffer()
4934 REG32_W(&_RegCtrl->VQ1_Base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
4935 REG16_W(&_RegCtrl->VQ1_Size, u32VQ_PktNum); in HAL_TSP_VQ_Buffer()
4938 REG32_W(&_RegCtrl->VQ2_Base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
4939 REG16_W(&_RegCtrl->VQ2_Size, u32VQ_PktNum); in HAL_TSP_VQ_Buffer()
4942 REG32_W(&_RegCtrl->VQ3_Base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
4943 REG16_W(&_RegCtrl->VQ3_Size, u32VQ_PktNum); in HAL_TSP_VQ_Buffer()
4958 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX0_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
4961 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX1_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
4964 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX2_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
4967 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX3_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
4978 REG16_CLR(&_RegCtrl->reg160E, TSP_VQTX0_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
4981 REG16_CLR(&_RegCtrl->reg160E, TSP_VQTX1_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
4984 REG16_CLR(&_RegCtrl->reg160E, TSP_VQTX2_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
4987 REG16_CLR(&_RegCtrl->reg160E, TSP_VQTX3_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
5001 REG16_SET(&_RegCtrl->HW2_Config3, TSP_VQ_EN|TSP_VQ2PINGPONG_EN); in HAL_TSP_VQ_Enable()
5005 REG16_CLR(&_RegCtrl->HW2_Config3, TSP_VQ_EN|TSP_VQ2PINGPONG_EN); in HAL_TSP_VQ_Enable()
5015 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_RESET); in HAL_TSP_VQ_Reset()
5018 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_RESET); in HAL_TSP_VQ_Reset()
5021 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_RESET); in HAL_TSP_VQ_Reset()
5024 REG16_SET(&_RegCtrl->VQ3_Config, TSP_VQ3_RESET); in HAL_TSP_VQ_Reset()
5035 REG16_CLR(&_RegCtrl->VQ0_CTRL, TSP_VQ0_RESET); in HAL_TSP_VQ_Reset()
5038 REG16_CLR(&_RegCtrl->VQ1_Config, TSP_VQ1_RESET); in HAL_TSP_VQ_Reset()
5041 REG16_CLR(&_RegCtrl->VQ2_Config, TSP_VQ2_RESET); in HAL_TSP_VQ_Reset()
5044 REG16_CLR(&_RegCtrl->VQ3_Config, TSP_VQ3_RESET); in HAL_TSP_VQ_Reset()
5059 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_OVERFLOW_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
5062 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_OVF_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
5065 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_OVF_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
5068 REG16_SET(&_RegCtrl->VQ3_Config, TSP_VQ3_OVF_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
5079 REG16_CLR(&_RegCtrl->VQ0_CTRL, TSP_VQ0_OVERFLOW_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
5082 REG16_CLR(&_RegCtrl->VQ1_Config, TSP_VQ1_OVF_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
5085 REG16_CLR(&_RegCtrl->VQ2_Config, TSP_VQ2_OVF_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
5088 REG16_CLR(&_RegCtrl->VQ3_Config, TSP_VQ3_OVF_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
5103 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_CLR_OVERFLOW_INT); in HAL_TSP_VQ_OverflowInt_Clr()
5106 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_CLR_OVF_INT); in HAL_TSP_VQ_OverflowInt_Clr()
5109 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_CLR_OVF_INT); in HAL_TSP_VQ_OverflowInt_Clr()
5112 REG16_SET(&_RegCtrl->VQ3_Config, TSP_VQ3_CLR_OVF_INT); in HAL_TSP_VQ_OverflowInt_Clr()
5123 REG16_CLR(&_RegCtrl->VQ0_CTRL, TSP_VQ0_CLR_OVERFLOW_INT); in HAL_TSP_VQ_OverflowInt_Clr()
5126 REG16_CLR(&_RegCtrl->VQ1_Config, TSP_VQ1_CLR_OVF_INT); in HAL_TSP_VQ_OverflowInt_Clr()
5129 REG16_CLR(&_RegCtrl->VQ2_Config, TSP_VQ2_CLR_OVF_INT); in HAL_TSP_VQ_OverflowInt_Clr()
5132 REG16_CLR(&_RegCtrl->VQ3_Config, TSP_VQ3_CLR_OVF_INT); in HAL_TSP_VQ_OverflowInt_Clr()
5146 REG16_SET(&(_RegCtrl->reg15b8), TSP_PVR1_PINGPONG); in HAL_PVR_Init()
5147 …REG16_W(&(_RegCtrl->FIFO_Src), (REG16_R(&(_RegCtrl->FIFO_Src)) & ~TSP_PVR1_SRC_MASK) | (((MS_U16)p… in HAL_PVR_Init()
5151 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_REG_PINGPONG_EN); in HAL_PVR_Init()
5152 …REG16_W(&(_RegCtrl->FIFO_Src), (REG16_R(&(_RegCtrl->FIFO_Src)) & ~TSP_PVR2_SRC_MASK_L) | ((((MS_U1… in HAL_PVR_Init()
5153 …REG16_W(&(_RegCtrl->PCR_Cfg), (REG16_R(&(_RegCtrl->PCR_Cfg)) & ~TSP_PVR2_SRC_MASK_H) | ((((MS_U16)… in HAL_PVR_Init()
5176 REG16_CLR(&(_RegCtrl->reg15b8), TSP_PVR1_PINGPONG); in HAL_PVR_Exit()
5177 REG16_CLR(&(_RegCtrl->FIFO_Src), TSP_PVR1_SRC_MASK); in HAL_PVR_Exit()
5180 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Exit()
5181 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Exit()
5185 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_REG_PINGPONG_EN); in HAL_PVR_Exit()
5186 REG16_CLR(&(_RegCtrl->FIFO_Src), TSP_PVR2_SRC_MASK_L); in HAL_PVR_Exit()
5187 REG16_CLR(&(_RegCtrl->PCR_Cfg), TSP_PVR2_SRC_MASK_H); in HAL_PVR_Exit()
5190 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Exit()
5191 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Exit()
5231 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Start()
5232 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Start()
5235 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_ENABLE); in HAL_PVR_Start()
5239 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Start()
5240 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Start()
5243 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_EN); in HAL_PVR_Start()
5278 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_ENABLE); in HAL_PVR_Stop()
5281 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_EN); in HAL_PVR_Stop()
5303 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_PAUSE); in HAL_PVR_Pause()
5306 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_PAUSE); in HAL_PVR_Pause()
5323 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_PAUSE); in HAL_PVR_Pause()
5326 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_PAUSE); in HAL_PVR_Pause()
5347 REG16_SET(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS); in HAL_PVR_RecPid()
5348 REG16_CLR(&(_RegCtrl->PVRConfig), TSP_PVR1_REC_ALL_EN); in HAL_PVR_RecPid()
5351 REG16_SET(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS2); in HAL_PVR_RecPid()
5352 REG16_CLR(&(_RegCtrl->PVRConfig), TSP_PVR2_REC_ALL_EN); in HAL_PVR_RecPid()
5371 REG16_CLR(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS); in HAL_PVR_RecPid()
5372 REG16_SET(&(_RegCtrl->PVRConfig), TSP_PVR1_REC_ALL_EN); in HAL_PVR_RecPid()
5375 REG16_CLR(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS2); in HAL_PVR_RecPid()
5376 REG16_SET(&(_RegCtrl->PVRConfig), TSP_PVR2_REC_ALL_EN); in HAL_PVR_RecPid()
5396 REG16_SET(&(_RegCtrl->PVRConfig), TSP_REC_NULL); in HAL_PVR_RecNull()
5400 REG16_CLR(&(_RegCtrl->PVRConfig), TSP_REC_NULL); in HAL_PVR_RecNull()
5422 … REG32_W(&_RegCtrl->TsRec_Head, (phyMiuOffsetPvrBuf0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5424 REG32_W(&(_RegCtrl->TsRec_Tail), (u32EndAddr0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5426 …REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (phyMiuOffsetPvrBuf0 >>MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5429 …REG32_W(&_RegCtrl->Str2mi_head2pvr1, (phyMiuOffsetPvrBuf1>> MIU_BUS) & TSP_HW_PVR1_BUF_HEAD2_MASK); in HAL_PVR_SetBuf()
5431 … REG32_W(&(_RegCtrl->Str2mi_tail2pvr1), (u32EndAddr1 >> MIU_BUS) &TSP_HW_PVR1_BUF_TAIL2_MASK); in HAL_PVR_SetBuf()
5433 … REG32_W(&(_RegCtrl->Str2mi_mid2pvr1), (phyMiuOffsetPvrBuf1>>MIU_BUS) & TSP_HW_PVR1_BUF_MID2_MASK); in HAL_PVR_SetBuf()
5440 … REG32_W(&_RegCtrl->Str2mi_head1_pvr2, (phyMiuOffsetPvrBuf0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5442 REG32_W(&_RegCtrl->Str2mi_tail1_pvr2, (u32EndAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5444 …REG32_W(&(_RegCtrl->Str2mi_mid1_wptr_pvr2), (phyMiuOffsetPvrBuf0 >>MIU_BUS) & TSP_STR2MI2_ADDR_MAS… in HAL_PVR_SetBuf()
5447 … REG32_W(&_RegCtrl->Str2mi_head2_pvr2, (phyMiuOffsetPvrBuf1 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5449 REG32_W(&_RegCtrl->Str2mi_tail2_pvr2, (u32EndAddr1 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5451 … REG32_W(&(_RegCtrl->Str2mi_mid2_pvr2), (phyMiuOffsetPvrBuf1 >>MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5502 REG32_W(&_RegCtrl->TsRec_Head, (u32StartAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_StartAddr()
5505 … REG32_W(&_RegCtrl->Str2mi_head2pvr1, (u32StartAddr1>> MIU_BUS) & TSP_HW_PVR1_BUF_HEAD2_MASK); in HAL_PVR_SetStr2Miu_StartAddr()
5509 … REG32_W(&_RegCtrl->Str2mi_head1_pvr2, (u32StartAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_StartAddr()
5512 … REG32_W(&_RegCtrl->Str2mi_head2_pvr2, (u32StartAddr1>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_StartAddr()
5561 REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (u32MidAddr0>>4) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_MidAddr()
5564 REG32_W(&(_RegCtrl->Str2mi_mid2pvr1), (u32MidAddr1>>4) & TSP_HW_PVR1_BUF_MID2_MASK); in HAL_PVR_SetStr2Miu_MidAddr()
5568 REG32_W(&(_RegCtrl->Str2mi_mid1_wptr_pvr2), (u32MidAddr0>>4) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_MidAddr()
5571 REG32_W(&(_RegCtrl->Str2mi_mid2_pvr2), (u32MidAddr1>>4) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_MidAddr()
5598 REG32_W(&(_RegCtrl->TsRec_Tail), (u32EndAddr0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_EndAddr()
5601 … REG32_W(&(_RegCtrl->Str2mi_tail2pvr1), (u32EndAddr1 >> MIU_BUS) &TSP_HW_PVR1_BUF_TAIL2_MASK); in HAL_PVR_SetStr2Miu_EndAddr()
5605 REG32_W(&_RegCtrl->Str2mi_tail1_pvr2, (u32EndAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_EndAddr()
5608 REG32_W(&_RegCtrl->Str2mi_tail2_pvr2, (u32EndAddr1>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_EndAddr()
5642 WritePtr = REG32_R(&_RegCtrl->TsRec_Mid_PVR1_WPTR) << MIU_BUS; in HAL_PVR_GetWritePtr()
5645 WritePtr = REG32_R(&_RegCtrl->Str2mi_mid1_wptr_pvr2) << MIU_BUS; in HAL_PVR_GetWritePtr()
5669 *eSrc = ((REG16_R(&(_RegCtrl->FIFO_Src)) & TSP_PVR1_SRC_MASK) >> TSP_PVR1_SRC_SHIFT); in HAL_PVR_GetEngSrc()
5673 … u16Value = (REG16_R(&(_RegCtrl->FIFO_Src)) & TSP_PVR2_SRC_MASK_L) >> TSP_PVR2_SRC_SHIFT_L; in HAL_PVR_GetEngSrc()
5674 u16Value |= ((REG16_R(&(_RegCtrl->PCR_Cfg)) & TSP_PVR2_SRC_MASK_H) << 1); in HAL_PVR_GetEngSrc()
5925 REG16_SET(&_RegCtrl->reg160C, TSP_RECORD192_EN); in HAL_PVR_SetStrPacketMode()
5928 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_PKT192_EN); in HAL_PVR_SetStrPacketMode()
5945 REG16_CLR(&_RegCtrl->reg160C, TSP_RECORD192_EN); in HAL_PVR_SetStrPacketMode()
5948 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_PKT192_EN); in HAL_PVR_SetStrPacketMode()
5968 REG16_CLR(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
5970 u32lpcr = REG32_R(&_RegCtrl->PVR1_LPcr1); in HAL_PVR_GetPVRTimeStamp()
5972 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
5976 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
5978 u32lpcr = REG32_R(&_RegCtrl->PVR2_LPCR1); in HAL_PVR_GetPVRTimeStamp()
5980 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
6007 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
6009 REG32_W(&_RegCtrl->PVR1_LPcr1, u32Stamp); in HAL_PVR_SetPVRTimeStamp()
6011 REG16_CLR(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
6014 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
6016 REG32_W(&_RegCtrl->PVR2_LPCR1, u32Stamp); in HAL_PVR_SetPVRTimeStamp()
6018 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
6083 REG16_SET(&_RegCtrl->HW2_Config3, TSP_PVR1_ALIGN_EN); in HAL_PVR_Alignment_Enable()
6086 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
6103 REG16_CLR(&_RegCtrl->HW2_Config3, TSP_PVR1_ALIGN_EN); in HAL_PVR_Alignment_Enable()
6106 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
6197 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR1_BLOCK_DIS); in HAL_PVR_Block_Dis()
6200 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_BLOCK_DIS); in HAL_PVR_Block_Dis()
6217 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR1_BLOCK_DIS); in HAL_PVR_Block_Dis()
6220 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_BLOCK_DIS); in HAL_PVR_Block_Dis()
6240 … REG16_MSK_W(&_RegCtrl->reg15b8, TSP_BURST_LEN_MASK, (u16BurstMode << TSP_BURST_LEN_SHIFT)); in HAL_PVR_BurstLen()
6243 …REG32_MSK_W(&_RegCtrl->PVR2_Config, TSP_PVR2_BURST_LEN_MASK, (u16BurstMode << TSP_PVR2_BURST_LEN_S… in HAL_PVR_BurstLen()
6355 REG16_W(&_RegCtrl->MOBF_PVR1_Index[0], (u32Key & TSP_MOBF_PVR1_INDEX_MASK)); in HAL_PVR_MOBF_Enable()
6358 REG16_W(&_RegCtrl->MOBF_PVR2_Index[0], (u32Key & TSP_MOBF_PVR2_INDEX_MASK)); in HAL_PVR_MOBF_Enable()
6436 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_VERSION); in HAL_TSP_HCMD_GetInfo()
6439 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_DATE); in HAL_TSP_HCMD_GetInfo()
6442 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_VERSION); in HAL_TSP_HCMD_GetInfo()
6447 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_INFO); in HAL_TSP_HCMD_GetInfo()
6450 u32Data = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_GetInfo()
6451 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_HCMD_GetInfo()
6460 REG32_W(&_RegCtrl->MCU_Data0 , u32Value); in HAL_TSP_HCMD_BufRst()
6461 REG32_W(&_RegCtrl->MCU_Cmd , TSP_MCU_CMD_BUFRST); in HAL_TSP_HCMD_BufRst()
6471 REG32_W(&_RegCtrl->MCU_Data0, u32Addr); in HAL_TSP_HCMD_Read()
6472 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_READ); in HAL_TSP_HCMD_Read()
6475 u32Data = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_Read()
6476 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_HCMD_Read()
6486 REG32_W(&_RegCtrl->MCU_Data0, u32Addr); in HAL_TSP_HCMD_Write()
6487 REG32_W(&_RegCtrl->MCU_Data1, u32Value); in HAL_TSP_HCMD_Write()
6488 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_WRITE); in HAL_TSP_HCMD_Write()
6491 u32Data = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_Write()
6492 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_HCMD_Write()
6502 REG32_W(&_RegCtrl->MCU_Data1, 0); in HAL_TSP_HCMD_Alive()
6503 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_ALIVE); //@TODO check FW HCMD in HAL_TSP_HCMD_Alive()
6505 u32Data = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_Alive()
6506 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_HCMD_Alive()
6513 REG32_W(&_RegCtrl->MCU_Data0, mcu_data0); in HAL_TSP_HCMD_SET()
6514 REG32_W(&_RegCtrl->MCU_Data1, mcu_data1); in HAL_TSP_HCMD_SET()
6515 REG32_W(&_RegCtrl->MCU_Cmd, mcu_cmd); in HAL_TSP_HCMD_SET()
6520 *pmcu_cmd = REG32_R(&_RegCtrl->MCU_Cmd); in HAL_TSP_HCMD_GET()
6521 *pmcu_data0 = REG32_R(&_RegCtrl->MCU_Data0); in HAL_TSP_HCMD_GET()
6522 *pmcu_data1 = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_GET()
6529 REG32_W(&_RegCtrl->MCU_Data0, FltId); in HAL_TSP_HCMD_SecRdyInt_Disable()
6530 REG32_W(&_RegCtrl->MCU_Data1,u32Data); in HAL_TSP_HCMD_SecRdyInt_Disable()
6531 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_SECRDYINT_DISABLE); // @TODO add HCMD list here in HAL_TSP_HCMD_SecRdyInt_Disable()
6533 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_HCMD_SecRdyInt_Disable()
6542 REG32_W(&_RegCtrl->MCU_Data0, u32Enable); in HAL_TSP_HCMD_Dbg()
6543 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_DBG); in HAL_TSP_HCMD_Dbg()
6546 u32Data = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_Dbg()
6547 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_HCMD_Dbg()
6549 return REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_Dbg()
6554 REG16_CLR(&_RegCtrl->DBG_SEL, TSP_DBG_SEL_MASK); in HAL_TSP_GetDBGStatus()
6555 REG16_SET(&_RegCtrl->DBG_SEL, ((u16Sel << TSP_DBG_SEL_SHIFT) & TSP_DBG_SEL_MASK)); in HAL_TSP_GetDBGStatus()
6557 return REG32_R(&_RegCtrl->TSP_Debug); in HAL_TSP_GetDBGStatus()
6574 REG16_SET(&_RegCtrl->HwInt_Stat, (TSP_HWINT_EN_MASK & u32Mask) | TSP_HWINT_STATUS_MASK); in HAL_TSP_INT_Enable()
6587 … REG16_SET(&_RegCtrl->HwInt2_Stat, (TSP_HWINT2_EN_MASK & (u32Mask >> 8)) | TSP_HWINT2_STATUS_MASK); in HAL_TSP_INT_Enable()
6595 …REG16_SET(&_RegCtrl->HwInt3_Stat, (TSP_HWINT3_EN_MASK & (u32Mask >> 16)) | TSP_HWINT3_STATUS_MASK); in HAL_TSP_INT_Enable()
6605 REG16_W(&_RegCtrl->HwInt_Stat, in HAL_TSP_INT_Disable()
6606 (REG16_R(&_RegCtrl->HwInt_Stat) & ~(TSP_HWINT_EN_MASK & (u32Mask))) | in HAL_TSP_INT_Disable()
6609 REG16_W(&_RegCtrl->HwInt2_Stat, in HAL_TSP_INT_Disable()
6610 (REG16_R(&_RegCtrl->HwInt2_Stat) & ~(TSP_HWINT2_EN_MASK & (u32Mask >> 8))) | in HAL_TSP_INT_Disable()
6613 REG16_W(&_RegCtrl->HwInt3_Stat, in HAL_TSP_INT_Disable()
6614 (REG16_R(&_RegCtrl->HwInt3_Stat) & ~(TSP_HWINT3_EN_MASK & (u32Mask >> 16))) | in HAL_TSP_INT_Disable()
6625 REG16_W(&_RegCtrl->HwInt_Stat, in HAL_TSP_INT_ClrHW()
6626 (REG16_R(&_RegCtrl->HwInt_Stat) & (~TSP_HWINT_STATUS_MASK)) | in HAL_TSP_INT_ClrHW()
6629 REG16_W(&_RegCtrl->HwInt2_Stat, in HAL_TSP_INT_ClrHW()
6630 (REG16_R(&_RegCtrl->HwInt2_Stat) & (~TSP_HWINT2_STATUS_MASK)) | in HAL_TSP_INT_ClrHW()
6633 REG16_W(&_RegCtrl->HwInt3_Stat, in HAL_TSP_INT_ClrHW()
6634 (REG16_R(&_RegCtrl->HwInt3_Stat) & (~TSP_HWINT3_STATUS_MASK)) | in HAL_TSP_INT_ClrHW()
6643 …status = (MS_U32)(((REG16_R(&_RegCtrl->HwInt3_Stat) & TSP_HWINT3_STATUS_MASK) >> TSP_HWINT3_STATUS… in HAL_TSP_INT_GetHW()
6645 …status |= ((MS_U32)(((REG16_R(&_RegCtrl->HwInt2_Stat) & TSP_HWINT2_STATUS_MASK) >> TSP_HWINT2_STAT… in HAL_TSP_INT_GetHW()
6647 …status |= ((MS_U32)((REG16_R(&_RegCtrl->HwInt_Stat) & TSP_HWINT_STATUS_MASK) >> TSP_HWINT_STATUS_S… in HAL_TSP_INT_GetHW()
6654 REG32_W(&_RegCtrl->SwInt_Stat, 0); in HAL_TSP_INT_ClrSW()
6659 return REG32_R(&_RegCtrl->SwInt_Stat); in HAL_TSP_INT_GetSW()
6950 REG16_SET(&_RegCtrl->reg15b8, TSP_REMOVE_DUP_AV_PKT); in HAL_TSP_PktDmx_RmDupAVPkt()
6954 REG16_CLR(&_RegCtrl->reg15b8, TSP_REMOVE_DUP_AV_PKT); in HAL_TSP_PktDmx_RmDupAVPkt()
6965 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_APES_ERR_RM_EN); in HAL_TSP_TEI_RemoveErrorPkt()
6968 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_VPES_ERR_RM_EN); in HAL_TSP_TEI_RemoveErrorPkt()
6979 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_APES_ERR_RM_EN); in HAL_TSP_TEI_RemoveErrorPkt()
6982 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_VPES_ERR_RM_EN); in HAL_TSP_TEI_RemoveErrorPkt()
6997 REG16_SET(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID0); in HAL_TSP_TEI_SKIP()
7000 REG16_SET(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID1); in HAL_TSP_TEI_SKIP()
7003 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TEI_SKIP_PKT2); in HAL_TSP_TEI_SKIP()
7006 REG16_SET(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID3); in HAL_TSP_TEI_SKIP()
7017 REG16_CLR(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID0); in HAL_TSP_TEI_SKIP()
7020 REG16_CLR(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID1); in HAL_TSP_TEI_SKIP()
7023 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TEI_SKIP_PKT2); in HAL_TSP_TEI_SKIP()
7026 REG16_CLR(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID3); in HAL_TSP_TEI_SKIP()
7089 REG16_SET(&_RegCtrl->reg160C,TSP_ORZ_DMAW_PROT_EN); in HAL_TSP_OR_Address_Protect_En()
7093 REG16_CLR(&_RegCtrl->reg160C,TSP_ORZ_DMAW_PROT_EN); in HAL_TSP_OR_Address_Protect_En()
7101 …REG32_W(&_RegCtrl->ORZ_DMAW_LBND,(MS_U32)(((u32AddrL - phyMiuOffset) >> MIU_BUS) & TSP_ORZ_DMAW_LB… in HAL_TSP_OR_Address_Protect()
7102 …REG32_W(&_RegCtrl->ORZ_DMAW_UBND,(MS_U32)(((u32AddrH - phyMiuOffset) >> MIU_BUS) & TSP_ORZ_DMAW_UB… in HAL_TSP_OR_Address_Protect()
7110 REG16_SET(&_RegCtrl->reg15b4,TSP_SEC_CB_PVR2_DAMW_PROTECT_EN); in HAL_TSP_SEC_Address_Protect_En()
7114 REG16_CLR(&_RegCtrl->reg15b4,TSP_SEC_CB_PVR2_DAMW_PROTECT_EN); in HAL_TSP_SEC_Address_Protect_En()
7127 REG32_W(&_RegCtrl->DMAW_LBND0,u32LBnd); in HAL_TSP_SEC_Address_Protect()
7128 REG32_W(&_RegCtrl->DMAW_UBND0,u32UBnd); in HAL_TSP_SEC_Address_Protect()
7131 REG32_W(&_RegCtrl->DMAW_LBND1,u32LBnd); in HAL_TSP_SEC_Address_Protect()
7132 REG32_W(&_RegCtrl->DMAW_UBND1,u32UBnd); in HAL_TSP_SEC_Address_Protect()
7192 REG32_W(&_RegCtrl->DMAW_LBND2, u32LBnd); in HAL_TSP_PVR_Address_Protect()
7193 REG32_W(&_RegCtrl->DMAW_UBND2, u32UBnd); in HAL_TSP_PVR_Address_Protect()
7196 REG32_W(&_RegCtrl->DMAW_LBND3, u32LBnd); in HAL_TSP_PVR_Address_Protect()
7197 REG32_W(&_RegCtrl->DMAW_UBND3, u32UBnd); in HAL_TSP_PVR_Address_Protect()
7200 REG32_W(&_RegCtrl->DMAW_LBND4, u32LBnd); in HAL_TSP_PVR_Address_Protect()
7201 REG32_W(&_RegCtrl->DMAW_UBND4, u32UBnd); in HAL_TSP_PVR_Address_Protect()
7376 REG32_W(&_RegCtrl->MCU_Data1, u32Config0); in HAL_TSP_CMD_Run()
7377 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_SEC_CC_CHECK_DISABLE); in HAL_TSP_CMD_Run()
7379 u32Data = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_CMD_Run()
7380 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_CMD_Run()
7567 u16PktDmxSrc = _CLR_(REG16_R(&_RegCtrl->reg15b8), TSP_MATCH_PID_SRC_MASK); in HAL_DSCMB_GetStatus()
7587 REG16_W(&_RegCtrl->reg15b8, u16PktDmxSrc); in HAL_DSCMB_GetStatus()
7589 …REG16_W(&_RegCtrl->PVRConfig, _SET_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // Set 1 to… in HAL_DSCMB_GetStatus()
7592 REG16_W(&_RegCtrl->PVRConfig, _CLR_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // freeze in HAL_DSCMB_GetStatus()
7594 u16WordId = _CLR_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_SEL_MASK); in HAL_DSCMB_GetStatus()
7599 REG16_MSK_W(&_RegCtrl->PVRConfig,TSP_MATCH_PID_SEL_MASK,u16WordId); in HAL_DSCMB_GetStatus()
7606 *pu32ScmbSts = _AND_(REG32_R(&_RegCtrl->TsPidScmbStatTsin), u32PIDFltMask); in HAL_DSCMB_GetStatus()
7608 …REG16_W(&_RegCtrl->PVRConfig, _SET_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // re-enable in HAL_DSCMB_GetStatus()