Lines Matching refs:PVR2_Config
355 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_RLD); in HAL_TSP_HwPatch()
978 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TS_IF2_EN); in HAL_TSP_TSIF_LiveEn()
998 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TS_IF2_EN); in HAL_TSP_TSIF_LiveEn()
1735 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TS_DATA2_SWAP); in HAL_TSP_TSIF_BitSwap()
1755 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TS_DATA2_SWAP); in HAL_TSP_TSIF_BitSwap()
1781 REG32_SET(&_RegCtrl->PVR2_Config, TSP_EXT_SYNC_SEL2); in HAL_TSP_TSIF_ExtSync()
1803 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_EXT_SYNC_SEL2); in HAL_TSP_TSIF_ExtSync()
1875 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_P_SEL2); in HAL_TSP_TSIF_Parl()
1895 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_P_SEL2); in HAL_TSP_TSIF_Parl()
4657 REG32_SET(&_RegCtrl->PVR2_Config, TSP_V_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4660 REG32_SET(&_RegCtrl->PVR2_Config, TSP_V3d_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4669 REG32_SET(&_RegCtrl->PVR2_Config, TSP_A_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4672 REG32_SET(&_RegCtrl->PVR2_Config, TSP_AD_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4675 REG32_SET(&_RegCtrl->PVR2_Config, TSP_AC_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4678 REG32_SET(&_RegCtrl->PVR2_Config, TSP_ADD_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4689 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_V_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4692 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_V3d_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4701 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_A_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4704 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_AD_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4707 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_AC_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4710 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_ADD_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
5151 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_REG_PINGPONG_EN); in HAL_PVR_Init()
5185 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_REG_PINGPONG_EN); in HAL_PVR_Exit()
5190 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Exit()
5191 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Exit()
5239 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Start()
5240 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Start()
5243 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_EN); in HAL_PVR_Start()
5281 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_EN); in HAL_PVR_Stop()
5306 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_PAUSE); in HAL_PVR_Pause()
5326 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_PAUSE); in HAL_PVR_Pause()
5928 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_PKT192_EN); in HAL_PVR_SetStrPacketMode()
5948 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_PKT192_EN); in HAL_PVR_SetStrPacketMode()
5976 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
5980 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
6014 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
6018 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
6086 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
6106 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
6197 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR1_BLOCK_DIS); in HAL_PVR_Block_Dis()
6200 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_BLOCK_DIS); in HAL_PVR_Block_Dis()
6217 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR1_BLOCK_DIS); in HAL_PVR_Block_Dis()
6220 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_BLOCK_DIS); in HAL_PVR_Block_Dis()
6243 …REG32_MSK_W(&_RegCtrl->PVR2_Config, TSP_PVR2_BURST_LEN_MASK, (u16BurstMode << TSP_PVR2_BURST_LEN_S… in HAL_PVR_BurstLen()
7003 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TEI_SKIP_PKT2); in HAL_TSP_TEI_SKIP()
7023 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TEI_SKIP_PKT2); in HAL_TSP_TEI_SKIP()