Lines Matching refs:CFG_16
350 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PID_BYPASS3_REC); in HAL_TSP_HwPatch()
356 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_LPCR1_RLD); in HAL_TSP_HwPatch()
5158 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_REG_PINGPONG_EN); in HAL_PVR_Init()
5196 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_REG_PINGPONG_EN); in HAL_PVR_Exit()
5199 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR); in HAL_PVR_Exit()
5200 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR); in HAL_PVR_Exit()
5247 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR); in HAL_PVR_Start()
5248 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR); in HAL_PVR_Start()
5251 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_EN); in HAL_PVR_Start()
5285 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_EN); in HAL_PVR_Stop()
5309 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_PAUSE); in HAL_PVR_Pause()
5329 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_PAUSE); in HAL_PVR_Pause()
5355 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PID_BYPASS3_REC); in HAL_PVR_RecPid()
5356 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_REC_ALL3); in HAL_PVR_RecPid()
5379 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PID_BYPASS3_REC); in HAL_PVR_RecPid()
5380 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_REC_ALL3); in HAL_PVR_RecPid()
5931 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_PKT192_EN); in HAL_PVR_SetStrPacketMode()
5951 REG16_CLR((&_RegCtrl2->CFG_16), CFG_16_PVR3_PKT192_EN); in HAL_PVR_SetStrPacketMode()
5983 REG16_CLR((&_RegCtrl2->CFG_16), CFG_16_PVR3_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
5987 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
6021 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PVR3_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
6025 REG16_CLR(&_RegCtrl2->CFG_16, CFG_16_PVR3_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
6089 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PVR3_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
6109 REG16_CLR(&_RegCtrl2->CFG_16, CFG_16_PVR3_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
6203 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PVR3_BLOCK_DIS); in HAL_PVR_Block_Dis()
6223 REG16_CLR(&_RegCtrl2->CFG_16, CFG_16_PVR3_BLOCK_DIS); in HAL_PVR_Block_Dis()
6246 …REG16_MSK_W(&_RegCtrl2->CFG_16, CFG_16_PVR3_BURST_LEN_MASK, (u16BurstMode << CFG_16_PVR3_BURST_LEN… in HAL_PVR_BurstLen()