Lines Matching refs:CFG3_35
336 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PREVENT_SRAM_COLLISION); in HAL_TSP_HwPatch()
368 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PUSI_3BYTE_MODE); //Enable audio 3 byte mode in HAL_TSP_HwPatch()
374 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BLK_AD_SCMBTIS_TSP); in HAL_TSP_HwPatch()
653 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PREVENT_SRAM_COLLISION); in HAL_TSP_Power()
6280 REG16_CLR(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL1); in HAL_PVR_PauseTime_En()
6283 REG16_CLR(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL2); in HAL_PVR_PauseTime_En()
6286 REG16_CLR(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL3); in HAL_PVR_PauseTime_En()
6289 REG16_CLR(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL4); in HAL_PVR_PauseTime_En()
6300 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL1); in HAL_PVR_PauseTime_En()
6303 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL2); in HAL_PVR_PauseTime_En()
6306 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL3); in HAL_PVR_PauseTime_En()
6309 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL4); in HAL_PVR_PauseTime_En()