156 #define TSO_CLKGEN2_REG(addr)       (*((volatile MS_U16*)(_u32TSORegBase + 0x1400UL + ((addr)<<2))))  macro
428             u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO1_IN) & REG_CLKGEN0_TSO_IN_MASK;  in HAL_TSO_GetInputTSIF_Status()
432             u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO2_IN) & REG_CLKGEN0_TSO_IN_MASK;  in HAL_TSO_GetInputTSIF_Status()
436             u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO3_IN) & REG_CLKGEN0_TSO_IN_MASK;  in HAL_TSO_GetInputTSIF_Status()
440             u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO4_IN) & REG_CLKGEN0_TSO_IN_MASK;  in HAL_TSO_GetInputTSIF_Status()
444             u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO5_IN) & REG_CLKGEN0_TSO_IN_MASK;  in HAL_TSO_GetInputTSIF_Status()
502         u16value = TSO_CLKGEN2_REG(u16Reg) & ~REG_CLKGEN0_TSO_IN_MASK;  in HAL_TSO_Set_InClk()
527         TSO_CLKGEN2_REG(u16Reg) = u16value;  in HAL_TSO_Set_InClk()
2156         TSO_CLKGEN2_REG(REG_CLKGEN2_TSO1_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;  in HAL_TSO_PowerCtrl()
2157         TSO_CLKGEN2_REG(REG_CLKGEN2_TSO2_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;  in HAL_TSO_PowerCtrl()
2158         TSO_CLKGEN2_REG(REG_CLKGEN2_TSO3_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;  in HAL_TSO_PowerCtrl()
2159         TSO_CLKGEN2_REG(REG_CLKGEN2_TSO4_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;  in HAL_TSO_PowerCtrl()
2160         TSO_CLKGEN2_REG(REG_CLKGEN2_TSO5_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;  in HAL_TSO_PowerCtrl()
2172         TSO_CLKGEN2_REG(REG_CLKGEN2_TSO1_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;  in HAL_TSO_PowerCtrl()
2173         TSO_CLKGEN2_REG(REG_CLKGEN2_TSO2_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;  in HAL_TSO_PowerCtrl()
2174         TSO_CLKGEN2_REG(REG_CLKGEN2_TSO3_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;  in HAL_TSO_PowerCtrl()
2175         TSO_CLKGEN2_REG(REG_CLKGEN2_TSO4_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;  in HAL_TSO_PowerCtrl()
2176         TSO_CLKGEN2_REG(REG_CLKGEN2_TSO5_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;  in HAL_TSO_PowerCtrl()