Lines Matching refs:_u32TSORegBase
48 static MS_VIRT _u32TSORegBase = 0; variable
101 #define TSO_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x1600UL + ((addr)<<2))))
147 …#define TSO_CLKGEN1_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x6600UL + ((addr)<<2))…
156 #define TSO_CLKGEN2_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x1400UL + ((addr)<<2))))
163 #define TSP_TOP_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x3c00UL + ((addr)<<2))))
200 #define TSO_MIUDIG0_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x0C00UL + ((addr)<<2))))
201 #define TSO_MIUDIG1_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x2400UL + ((addr)<<2))))
225 _u32TSORegBase = u32BankAddr; in HAL_TSO_SetBank()
226 _TSOCtrl = (REG_Ctrl_TSO*)(_u32TSORegBase+ REG_CTRL_BASE_TSO); // 0x1706 in HAL_TSO_SetBank()
227 _TSOCtrl1 = (REG_Ctrl_TSO1*)(_u32TSORegBase+ REG_CTRL_BASE_TSO1); // 0x1612 in HAL_TSO_SetBank()
602 u32Speed = (MS_U32)((volatile MS_U16*)(_u32TSORegBase))[NPM_REG_MIPS_PLLCLK];