191     H265eSyntax_new     *syn;  member
260 static void vepu580_h265_set_me_ram(H265eSyntax_new *syn, hevc_vepu580_base *regs,  in vepu580_h265_set_me_ram()  argument
270     if (!syn->pp.tiles_enabled_flag) {  in vepu580_h265_set_me_ram()
285         RK_S32 tile_ctu_endx = tile_start_x + syn->pp.column_width_minus1[index];  in vepu580_h265_set_me_ram()
1630 vepu580_h265_set_patch_info(MppDevRegOffCfgs *cfgs, H265eSyntax_new *syn,  in vepu580_h265_set_patch_info()  argument
1634     RK_U32 hor_stride = syn->pp.hor_stride;  in vepu580_h265_set_patch_info()
1635     RK_U32 ver_stride = syn->pp.ver_stride ? syn->pp.ver_stride : syn->pp.pic_height;  in vepu580_h265_set_patch_info()
1892     H265eSyntax_new *syn = ctx->syn;  in vepu580_h265_set_rc_regs()  local
1901     mb_wd64 = (syn->pp.pic_width + 63) / 64;  in vepu580_h265_set_rc_regs()
1902     mb_h64 = (syn->pp.pic_height + 63) / 64;  in vepu580_h265_set_rc_regs()
2064 static void vepu580_h265_set_slice_regs(H265eSyntax_new *syn, hevc_vepu580_base *regs)  in vepu580_h265_set_slice_regs()  argument
2066 …regs->reg0237_synt_sps.smpl_adpt_ofst_e    = syn->pp.sample_adaptive_offset_enabled_flag;//slice->…  in vepu580_h265_set_slice_regs()
2067     regs->reg0237_synt_sps.num_st_ref_pic       = syn->pp.num_short_term_ref_pic_sets;  in vepu580_h265_set_slice_regs()
2068     regs->reg0237_synt_sps.num_lt_ref_pic       = syn->pp.num_long_term_ref_pics_sps;  in vepu580_h265_set_slice_regs()
2069     regs->reg0237_synt_sps.lt_ref_pic_prsnt     = syn->pp.long_term_ref_pics_present_flag;  in vepu580_h265_set_slice_regs()
2070     regs->reg0237_synt_sps.tmpl_mvp_e          = syn->pp.sps_temporal_mvp_enabled_flag;  in vepu580_h265_set_slice_regs()
2071     regs->reg0237_synt_sps.log2_max_poc_lsb     = syn->pp.log2_max_pic_order_cnt_lsb_minus4;  in vepu580_h265_set_slice_regs()
2072     regs->reg0237_synt_sps.strg_intra_smth      = syn->pp.strong_intra_smoothing_enabled_flag;  in vepu580_h265_set_slice_regs()
2074     regs->reg0238_synt_pps.dpdnt_sli_seg_en     = syn->pp.dependent_slice_segments_enabled_flag;  in vepu580_h265_set_slice_regs()
2075     regs->reg0238_synt_pps.out_flg_prsnt_flg    = syn->pp.output_flag_present_flag;  in vepu580_h265_set_slice_regs()
2076     regs->reg0238_synt_pps.num_extr_sli_hdr     = syn->pp.num_extra_slice_header_bits;  in vepu580_h265_set_slice_regs()
2077     regs->reg0238_synt_pps.sgn_dat_hid_en       = syn->pp.sign_data_hiding_enabled_flag;  in vepu580_h265_set_slice_regs()
2078     regs->reg0238_synt_pps.cbc_init_prsnt_flg   = syn->pp.cabac_init_present_flag;  in vepu580_h265_set_slice_regs()
2079     regs->reg0238_synt_pps.pic_init_qp          = syn->pp.init_qp_minus26 + 26;  in vepu580_h265_set_slice_regs()
2080     regs->reg0238_synt_pps.cu_qp_dlt_en         = syn->pp.cu_qp_delta_enabled_flag;  in vepu580_h265_set_slice_regs()
2081     regs->reg0238_synt_pps.chrm_qp_ofst_prsn    = syn->pp.pps_slice_chroma_qp_offsets_present_flag;  in vepu580_h265_set_slice_regs()
2082 …  regs->reg0238_synt_pps.lp_fltr_acrs_sli     = syn->pp.pps_loop_filter_across_slices_enabled_flag;  in vepu580_h265_set_slice_regs()
2083     regs->reg0238_synt_pps.dblk_fltr_ovrd_en    = syn->pp.deblocking_filter_override_enabled_flag;  in vepu580_h265_set_slice_regs()
2084     regs->reg0238_synt_pps.lst_mdfy_prsnt_flg   = syn->pp.lists_modification_present_flag;  in vepu580_h265_set_slice_regs()
2085 … regs->reg0238_synt_pps.sli_seg_hdr_extn     = syn->pp.slice_segment_header_extension_present_flag;  in vepu580_h265_set_slice_regs()
2086     regs->reg0238_synt_pps.cu_qp_dlt_depth      = syn->pp.diff_cu_qp_delta_depth;  in vepu580_h265_set_slice_regs()
2087     regs->reg0238_synt_pps.lpf_fltr_acrs_til    = syn->pp.loop_filter_across_tiles_enabled_flag;  in vepu580_h265_set_slice_regs()
2089     regs->reg0239_synt_sli0.cbc_init_flg        = syn->sp.cbc_init_flg;  in vepu580_h265_set_slice_regs()
2090     regs->reg0239_synt_sli0.mvd_l1_zero_flg     = syn->sp.mvd_l1_zero_flg;  in vepu580_h265_set_slice_regs()
2091     regs->reg0239_synt_sli0.mrg_up_flg          = syn->sp.merge_up_flag;  in vepu580_h265_set_slice_regs()
2092     regs->reg0239_synt_sli0.mrg_lft_flg         = syn->sp.merge_left_flag;  in vepu580_h265_set_slice_regs()
2093     regs->reg0239_synt_sli0.ref_pic_lst_mdf_l0  = syn->sp.ref_pic_lst_mdf_l0;  in vepu580_h265_set_slice_regs()
2095     regs->reg0239_synt_sli0.num_refidx_l1_act   = syn->sp.num_refidx_l1_act;  in vepu580_h265_set_slice_regs()
2096     regs->reg0239_synt_sli0.num_refidx_l0_act   = syn->sp.num_refidx_l0_act;  in vepu580_h265_set_slice_regs()
2098     regs->reg0239_synt_sli0.num_refidx_act_ovrd = syn->sp.num_refidx_act_ovrd;  in vepu580_h265_set_slice_regs()
2100     regs->reg0239_synt_sli0.sli_sao_chrm_flg    = syn->sp.sli_sao_chrm_flg;  in vepu580_h265_set_slice_regs()
2101     regs->reg0239_synt_sli0.sli_sao_luma_flg    = syn->sp.sli_sao_luma_flg;  in vepu580_h265_set_slice_regs()
2102     regs->reg0239_synt_sli0.sli_tmprl_mvp_e     = syn->sp.sli_tmprl_mvp_en;  in vepu580_h265_set_slice_regs()
2103     regs->reg0192_enc_pic.num_pic_tot_cur       = syn->sp.tot_poc_num;  in vepu580_h265_set_slice_regs()
2105     regs->reg0239_synt_sli0.pic_out_flg         = syn->sp.pic_out_flg;  in vepu580_h265_set_slice_regs()
2106     regs->reg0239_synt_sli0.sli_type            = syn->sp.slice_type;  in vepu580_h265_set_slice_regs()
2107     regs->reg0239_synt_sli0.sli_rsrv_flg        = syn->sp.slice_rsrv_flg;  in vepu580_h265_set_slice_regs()
2108     regs->reg0239_synt_sli0.dpdnt_sli_seg_flg   = syn->sp.dpdnt_sli_seg_flg;  in vepu580_h265_set_slice_regs()
2109     regs->reg0239_synt_sli0.sli_pps_id          = syn->sp.sli_pps_id;  in vepu580_h265_set_slice_regs()
2110     regs->reg0239_synt_sli0.no_out_pri_pic      = syn->sp.no_out_pri_pic;  in vepu580_h265_set_slice_regs()
2113     regs->reg0240_synt_sli1.sp_tc_ofst_div2       = syn->sp.sli_tc_ofst_div2;  in vepu580_h265_set_slice_regs()
2114     regs->reg0240_synt_sli1.sp_beta_ofst_div2     = syn->sp.sli_beta_ofst_div2;  in vepu580_h265_set_slice_regs()
2115     regs->reg0240_synt_sli1.sli_lp_fltr_acrs_sli  = syn->sp.sli_lp_fltr_acrs_sli;  in vepu580_h265_set_slice_regs()
2116     regs->reg0240_synt_sli1.sp_dblk_fltr_dis      = syn->sp.sli_dblk_fltr_dis;  in vepu580_h265_set_slice_regs()
2117     regs->reg0240_synt_sli1.dblk_fltr_ovrd_flg    = syn->sp.dblk_fltr_ovrd_flg;  in vepu580_h265_set_slice_regs()
2118 … regs->reg0240_synt_sli1.sli_cb_qp_ofst        = syn->pp.pps_slice_chroma_qp_offsets_present_flag ?  in vepu580_h265_set_slice_regs()
2119 …                                                 syn->sp.sli_cb_qp_ofst : syn->pp.pps_cb_qp_offset;  in vepu580_h265_set_slice_regs()
2120     regs->reg0240_synt_sli1.max_mrg_cnd           = syn->sp.max_mrg_cnd;  in vepu580_h265_set_slice_regs()
2122     regs->reg0240_synt_sli1.col_ref_idx           = syn->sp.col_ref_idx;  in vepu580_h265_set_slice_regs()
2123     regs->reg0240_synt_sli1.col_frm_l0_flg        = syn->sp.col_frm_l0_flg;  in vepu580_h265_set_slice_regs()
2124     regs->reg0241_synt_sli2.sli_poc_lsb           = syn->sp.sli_poc_lsb;  in vepu580_h265_set_slice_regs()
2125     regs->reg0241_synt_sli2.sli_hdr_ext_len       = syn->sp.sli_hdr_ext_len;  in vepu580_h265_set_slice_regs()
2129 static void vepu580_h265_set_ref_regs(H265eSyntax_new *syn, hevc_vepu580_base *regs)  in vepu580_h265_set_ref_regs()  argument
2131     regs->reg0242_synt_refm0.st_ref_pic_flg = syn->sp.st_ref_pic_flg;  in vepu580_h265_set_ref_regs()
2132     regs->reg0242_synt_refm0.poc_lsb_lt0 = syn->sp.poc_lsb_lt0;  in vepu580_h265_set_ref_regs()
2133     regs->reg0242_synt_refm0.num_lt_pic = syn->sp.num_lt_pic;  in vepu580_h265_set_ref_regs()
2135     regs->reg0243_synt_refm1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0;  in vepu580_h265_set_ref_regs()
2136     regs->reg0243_synt_refm1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0;  in vepu580_h265_set_ref_regs()
2137     regs->reg0243_synt_refm1.used_by_lt_flg0 = syn->sp.used_by_lt_flg0;  in vepu580_h265_set_ref_regs()
2138     regs->reg0243_synt_refm1.used_by_lt_flg1 = syn->sp.used_by_lt_flg1;  in vepu580_h265_set_ref_regs()
2139     regs->reg0243_synt_refm1.used_by_lt_flg2 = syn->sp.used_by_lt_flg2;  in vepu580_h265_set_ref_regs()
2140     regs->reg0243_synt_refm1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0;  in vepu580_h265_set_ref_regs()
2141     regs->reg0243_synt_refm1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0;  in vepu580_h265_set_ref_regs()
2142     regs->reg0243_synt_refm1.dlt_poc_msb_prsnt1 = syn->sp.dlt_poc_msb_prsnt1;  in vepu580_h265_set_ref_regs()
2143     regs->reg0243_synt_refm1.num_negative_pics = syn->sp.num_neg_pic;  in vepu580_h265_set_ref_regs()
2144     regs->reg0243_synt_refm1.num_pos_pic = syn->sp.num_pos_pic;  in vepu580_h265_set_ref_regs()
2146     regs->reg0243_synt_refm1.used_by_s0_flg = syn->sp.used_by_s0_flg;  in vepu580_h265_set_ref_regs()
2147     regs->reg0244_synt_refm2.dlt_poc_s0_m10 = syn->sp.dlt_poc_s0_m10;  in vepu580_h265_set_ref_regs()
2148     regs->reg0244_synt_refm2.dlt_poc_s0_m11 = syn->sp.dlt_poc_s0_m11;  in vepu580_h265_set_ref_regs()
2149     regs->reg0245_synt_refm3.dlt_poc_s0_m12 = syn->sp.dlt_poc_s0_m12;  in vepu580_h265_set_ref_regs()
2150     regs->reg0245_synt_refm3.dlt_poc_s0_m13 = syn->sp.dlt_poc_s0_m13;  in vepu580_h265_set_ref_regs()
2152     regs->reg0246_synt_long_refm0.poc_lsb_lt1 = syn->sp.poc_lsb_lt1;  in vepu580_h265_set_ref_regs()
2153     regs->reg0247_synt_long_refm1.dlt_poc_msb_cycl1 = syn->sp.dlt_poc_msb_cycl1;  in vepu580_h265_set_ref_regs()
2154     regs->reg0246_synt_long_refm0.poc_lsb_lt2 = syn->sp.poc_lsb_lt2;  in vepu580_h265_set_ref_regs()
2155     regs->reg0243_synt_refm1.dlt_poc_msb_prsnt2 = syn->sp.dlt_poc_msb_prsnt2;  in vepu580_h265_set_ref_regs()
2156     regs->reg0247_synt_long_refm1.dlt_poc_msb_cycl2 = syn->sp.dlt_poc_msb_cycl2;  in vepu580_h265_set_ref_regs()
2157     regs->reg0240_synt_sli1.lst_entry_l0 = syn->sp.lst_entry_l0;  in vepu580_h265_set_ref_regs()
2158     regs->reg0239_synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0;  in vepu580_h265_set_ref_regs()
2314 static void vepu580_h265_set_me_regs(H265eV580HalContext *ctx, H265eSyntax_new *syn, hevc_vepu580_b…  in vepu580_h265_set_me_regs()  argument
2320     RK_S32 pic_wd64 = MPP_ALIGN(syn->pp.pic_width, 64) >> 6;  in vepu580_h265_set_me_regs()
2329     if (syn->pp.pic_width  < merangx + 60 || syn->pp.pic_width  <= 352) {  in vepu580_h265_set_me_regs()
2330         if (merangx > syn->pp.pic_width ) {  in vepu580_h265_set_me_regs()
2331             merangx = syn->pp.pic_width;  in vepu580_h265_set_me_regs()
2336     if (syn->pp.pic_height < merangy + 60 || syn->pp.pic_height <= 288) {  in vepu580_h265_set_me_regs()
2337         if (merangy > syn->pp.pic_height) {  in vepu580_h265_set_me_regs()
2338             merangy = syn->pp.pic_height;  in vepu580_h265_set_me_regs()
2374     if (syn->pp.sps_temporal_mvp_enabled_flag &&  in vepu580_h265_set_me_regs()
2384     if (syn->pp.pic_width > 2688) {  in vepu580_h265_set_me_regs()
2386     } else if (syn->pp.pic_width > 2048) {  in vepu580_h265_set_me_regs()
2451     H265eSyntax_new *syn = ctx->syn;  in vepu580_h265_set_hw_address()  local
2462     if (!syn->sp.non_reference_flag) {  in vepu580_h265_set_hw_address()
2477     if (syn->pp.tiles_enabled_flag) {  in vepu580_h265_set_hw_address()
2478 …      RK_U32 tile_num = (syn->pp.num_tile_columns_minus1 + 1) * (syn->pp.num_tile_rows_minus1 + 1);  in vepu580_h265_set_hw_address()
2480         RK_U32 max_tile_buf_size = MPP_ALIGN(((MPP_ALIGN(syn->pp.pic_height, 64) + 64) << 5), 256);  in vepu580_h265_set_hw_address()
2679     H265eSyntax_new *syn = ctx->syn;  in hal_h265e_v580_gen_regs()  local
2691     pic_width_align8 = (syn->pp.pic_width + 7) & (~7);  in hal_h265e_v580_gen_regs()
2692     pic_height_align8 = (syn->pp.pic_height + 7) & (~7);  in hal_h265e_v580_gen_regs()
2693     pic_wd64 = (syn->pp.pic_width + 63) / 64;  in hal_h265e_v580_gen_regs()
2694     pic_h64 = (syn->pp.pic_height + 63) / 64;  in hal_h265e_v580_gen_regs()
2743     reg_base->reg0197_src_fill.pic_wfill    = (syn->pp.pic_width & 0x7)  in hal_h265e_v580_gen_regs()
2744                                               ? (8 - (syn->pp.pic_width & 0x7)) : 0;  in hal_h265e_v580_gen_regs()
2746     reg_base->reg0197_src_fill.pic_hfill    = (syn->pp.pic_height & 0x7)  in hal_h265e_v580_gen_regs()
2747                                               ? (8 - (syn->pp.pic_height & 0x7)) : 0;  in hal_h265e_v580_gen_regs()
2750 …reg_base->reg0192_enc_pic.cur_frm_ref   = !syn->sp.non_reference_flag; //current frame will be ref…  in hal_h265e_v580_gen_regs()
2757     reg_base->reg0203_src_proc.afbcd_en = (MPP_FRAME_FMT_IS_FBC(syn->pp.mpp_format)) ? 1 : 0;  in hal_h265e_v580_gen_regs()
2762     vepu580_h265_set_me_regs(ctx, syn, reg_base);  in hal_h265e_v580_gen_regs()
2768     if (syn->pp.num_long_term_ref_pics_sps) {  in hal_h265e_v580_gen_regs()
2777     reg_base->reg0232_rdo_cfg.scl_lst_sel = syn->pp.scaling_list_enabled_flag;  in hal_h265e_v580_gen_regs()
2778     reg_base->reg0236_synt_nal.nal_unit_type = h265e_get_nal_type(&syn->sp, ctx->frame_type);  in hal_h265e_v580_gen_regs()
2783     vepu580_h265_set_slice_regs(syn, reg_base);  in hal_h265e_v580_gen_regs()
2784     vepu580_h265_set_ref_regs(syn, reg_base);  in hal_h265e_v580_gen_regs()
2804     vepu580_setup_split(regs, cfg, syn->pp.tiles_enabled_flag);  in hal_h265e_v580_gen_regs()
2810 void hal_h265e_v580_set_uniform_tile(hevc_vepu580_base *regs, H265eSyntax_new *syn,  in hal_h265e_v580_set_uniform_tile()  argument
2813     if (syn->pp.tiles_enabled_flag) {  in hal_h265e_v580_set_uniform_tile()
2814         RK_S32 mb_h = MPP_ALIGN(syn->pp.pic_height, 64) / 64;  in hal_h265e_v580_set_uniform_tile()
2815         RK_S32 tile_width = syn->pp.column_width_minus1[index] + 1;  in hal_h265e_v580_set_uniform_tile()
2840         if (index == syn->pp.num_tile_columns_minus1) {  in hal_h265e_v580_set_uniform_tile()
2847         regs->reg0252_tile_cfg.tile_en = syn->pp.tiles_enabled_flag;  in hal_h265e_v580_set_uniform_tile()
2860     H265eSyntax_new *syn = ctx->syn;  in hal_h265e_v580_start()  local
2861     RK_U32 tile_num = (syn->pp.num_tile_columns_minus1 + 1) * (syn->pp.num_tile_rows_minus1 + 1);  in hal_h265e_v580_start()
2903         vepu580_h265_set_me_ram(syn, reg_base, k, tile_start_x);  in hal_h265e_v580_start()
2906         vepu580_h265_set_patch_info(frm->reg_cfg, syn, (VepuFmt)fmt->format, enc_task);  in hal_h265e_v580_start()
2908             hal_h265e_v580_set_uniform_tile(reg_base, syn, k, tile_start_x);  in hal_h265e_v580_start()
2942             vepu580_h265e_save_pass1_patch(hw_regs, ctx, syn->pp.tiles_enabled_flag);  in hal_h265e_v580_start()
2977         tile_start_x += (syn->pp.column_width_minus1[k] + 1);  in hal_h265e_v580_start()
3101     H265eSyntax_new *syn = ctx->syn;  in dump_files()  local
3102     HalBuf *hal_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.ref_pic.slot_idx);  in dump_files()
3121     hal_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.recon_pic.slot_idx);  in dump_files()
3330         ctx->syn = (H265eSyntax_new *)task->syntax.data;  in hal_h265e_v580_get_task()
3331         ctx->dpb = (H265eDpb*)ctx->syn->dpb;  in hal_h265e_v580_get_task()
3362         frm_cfg->hal_curr_idx = ctx->syn->sp.recon_pic.slot_idx;  in hal_h265e_v580_get_task()
3363         frm_cfg->hal_refr_idx = ctx->syn->sp.ref_pic.slot_idx;  in hal_h265e_v580_get_task()
3389     H265eSyntax_new *syn = (H265eSyntax_new *) enc_task->syntax.data;  in hal_h265e_v580_ret_task()  local
3408                     if (syn->sp.temporal_id && len > 5)  in hal_h265e_v580_ret_task()
3409                         tile1_ptr[5] = (tile1_ptr[5] & 0xf8) | ((syn->sp.temporal_id + 1) & 0x7);  in hal_h265e_v580_ret_task()
3419                     if (syn->sp.temporal_id) {  in hal_h265e_v580_ret_task()
3420                         stream_ptr[5] = (stream_ptr[5] & 0xf8) | ((syn->sp.temporal_id + 1) & 0x7);  in hal_h265e_v580_ret_task()