2274     cfg1.reg = &reg_out->st;  in hal_h265e_v580_send_regs()
2965                 stream_len += reg_out->st.bs_lgth_l32;  in hal_h265e_v580_start()
2966                 fb->qp_sum += reg_out->st.qp_sum;  in hal_h265e_v580_start()
2967                 fb->out_strm_size += reg_out->st.bs_lgth_l32;  in hal_h265e_v580_start()
2968                 fb->sse_sum += (RK_S64)(reg_out->st.sse_h32 << 16) +  in hal_h265e_v580_start()
2969                                (reg_out->st.st_sse_bsl.sse_l16 & 0xffff);  in hal_h265e_v580_start()
2970                 fb->st_madi += reg_out->st.madi;  in hal_h265e_v580_start()
2971                 fb->st_madp += reg_out->st.madp;  in hal_h265e_v580_start()
2972                 fb->st_mb_num += reg_out->st.st_bnum_b16.num_b16;  in hal_h265e_v580_start()
2973                 fb->st_ctu_num += reg_out->st.st_bnum_cme.num_ctu;  in hal_h265e_v580_start()
3002     fb->qp_sum += elem->st.qp_sum;  in vepu580_h265_set_feedback()
3004     fb->out_strm_size += elem->st.bs_lgth_l32;  in vepu580_h265_set_feedback()
3006     fb->sse_sum += (RK_S64)(elem->st.sse_h32 << 16) +  in vepu580_h265_set_feedback()
3007                    (elem->st.st_sse_bsl.sse_l16 & 0xffff);  in vepu580_h265_set_feedback()
3038     fb->st_madi += elem->st.madi;  in vepu580_h265_set_feedback()
3039     fb->st_madp += elem->st.madp;  in vepu580_h265_set_feedback()
3040     fb->st_mb_num += elem->st.st_bnum_b16.num_b16;  in vepu580_h265_set_feedback()
3041     fb->st_ctu_num += elem->st.st_bnum_cme.num_ctu;  in vepu580_h265_set_feedback()
3043     fb->st_lvl64_inter_num += elem->st.st_pnum_p64.pnum_p64;  in vepu580_h265_set_feedback()
3044     fb->st_lvl32_inter_num += elem->st.st_pnum_p32.pnum_p32;  in vepu580_h265_set_feedback()
3045     fb->st_lvl32_intra_num += elem->st.st_pnum_i32.pnum_i32;  in vepu580_h265_set_feedback()
3046     fb->st_lvl16_inter_num += elem->st.st_pnum_p16.pnum_p16;  in vepu580_h265_set_feedback()
3047     fb->st_lvl16_intra_num += elem->st.st_pnum_i16.pnum_i16;  in vepu580_h265_set_feedback()
3048     fb->st_lvl8_inter_num  += elem->st.st_pnum_p8.pnum_p8;  in vepu580_h265_set_feedback()
3049     fb->st_lvl8_intra_num  += elem->st.st_pnum_i8.pnum_i8;  in vepu580_h265_set_feedback()
3050     fb->st_lvl4_intra_num  += elem->st.st_pnum_i4.pnum_i4;  in vepu580_h265_set_feedback()
3051     memcpy(&fb->st_cu_num_qp[0], &elem->st.st_b8_qp0, 52 * sizeof(RK_U32));  in vepu580_h265_set_feedback()
3291             RK_U32 tile_size = elem_ret->st.bs_lgth_l32;  in hal_h265e_v580_wait()