1337     hevc_vepu580_wgt *reg_wgt = &regs->reg_wgt;  in vepu580_h265_global_cfg_set()  local
1340     vepu580_h265_sobel_cfg(reg_wgt);  in vepu580_h265_global_cfg_set()
1345     memcpy(&reg_wgt->iprd_wgt_qp_hevc_0_51[0], lamd_satd_qp, sizeof(lamd_satd_qp));  in vepu580_h265_global_cfg_set()
1352         memcpy(&reg_wgt->rdo_wgta_qp_grpa_0_51[0], lamd_moda_qp, sizeof(lamd_moda_qp));  in vepu580_h265_global_cfg_set()
1358         memcpy(&reg_wgt->rdo_wgta_qp_grpa_0_51[0], lamd_modb_qp, sizeof(lamd_modb_qp));  in vepu580_h265_global_cfg_set()
1369     reg_wgt->reg1484_qnt_bias_comb.qnt_bias_i = 171;  in vepu580_h265_global_cfg_set()
1370     reg_wgt->reg1484_qnt_bias_comb.qnt_bias_p = 85;  in vepu580_h265_global_cfg_set()
1372     memcpy(&reg_wgt->lvl32_intra_CST_THD0, lvl32_intra_cst_thd, sizeof(lvl32_intra_cst_thd));  in vepu580_h265_global_cfg_set()
1373     memcpy(&reg_wgt->lvl16_intra_CST_THD0, lvl16_intra_cst_thd, sizeof(lvl16_intra_cst_thd));  in vepu580_h265_global_cfg_set()
1374     memcpy(&reg_wgt->lvl32_intra_CST_WGT0, lvl32_intra_cst_wgt, sizeof(lvl32_intra_cst_wgt));  in vepu580_h265_global_cfg_set()
1375     memcpy(&reg_wgt->lvl16_intra_CST_WGT0, lvl16_intra_cst_wgt, sizeof(lvl16_intra_cst_wgt));  in vepu580_h265_global_cfg_set()
1377     reg_wgt->cime_sqi_cfg.cime_sad_mod_sel      = 0;  in vepu580_h265_global_cfg_set()
1378     reg_wgt->cime_sqi_cfg.cime_sad_use_big_block = 0;  in vepu580_h265_global_cfg_set()
1379     reg_wgt->cime_sqi_cfg.cime_pmv_set_zero     = 1;  in vepu580_h265_global_cfg_set()
1380     reg_wgt->cime_sqi_cfg.cime_pmv_num          = 3;  in vepu580_h265_global_cfg_set()
1381     reg_wgt->cime_sqi_thd.cime_mvd_th0 = 32;  in vepu580_h265_global_cfg_set()
1382     reg_wgt->cime_sqi_thd.cime_mvd_th1 = 80;  in vepu580_h265_global_cfg_set()
1383     reg_wgt->cime_sqi_thd.cime_mvd_th2 = 128;  in vepu580_h265_global_cfg_set()
1384     reg_wgt->cime_sqi_multi0.cime_multi0 = 16;  in vepu580_h265_global_cfg_set()
1385     reg_wgt->cime_sqi_multi0.cime_multi1 = 32;  in vepu580_h265_global_cfg_set()
1386     reg_wgt->cime_sqi_multi1.cime_multi2 = 96;  in vepu580_h265_global_cfg_set()
1387     reg_wgt->cime_sqi_multi1.cime_multi3 = 96;  in vepu580_h265_global_cfg_set()
1388     reg_wgt->rime_sqi_thd.cime_sad_th0 = 48;  in vepu580_h265_global_cfg_set()
1389     reg_wgt->rime_sqi_thd.rime_mvd_th0 = 3;  in vepu580_h265_global_cfg_set()
1390     reg_wgt->rime_sqi_thd.rime_mvd_th1 = 8;  in vepu580_h265_global_cfg_set()
1391     reg_wgt->rime_sqi_multi.rime_multi0 = 16;  in vepu580_h265_global_cfg_set()
1392     reg_wgt->rime_sqi_multi.rime_multi1 = 16;  in vepu580_h265_global_cfg_set()
1393     reg_wgt->rime_sqi_multi.rime_multi2 = 128;  in vepu580_h265_global_cfg_set()
1394     reg_wgt->fme_sqi_thd0.cime_sad_pu16_th = 16;  in vepu580_h265_global_cfg_set()
1395     reg_wgt->fme_sqi_thd0.cime_sad_pu32_th = 16;  in vepu580_h265_global_cfg_set()
1396     reg_wgt->fme_sqi_thd1.cime_sad_pu64_th = 16;  in vepu580_h265_global_cfg_set()
1397     reg_wgt->fme_sqi_thd1.move_lambda = 1;  in vepu580_h265_global_cfg_set()
2227     cfg.reg = &hw_regs->reg_wgt;  in hal_h265e_v580_send_regs()
2238         regs = (RK_U32*)&hw_regs->reg_wgt;  in hal_h265e_v580_send_regs()